Abstract: A network multifunction peripheral includes an NIC that conducts communication with a LAN and a recording unit that can be put in a normal power state and a low-power consumption state. The recording unit processes received data when the recording unit is in the normal power state. The NIC includes a transmit-receive unit that transmits and receives data, a power state determining unit that determines the power state of the recording unit, a start-up signal output unit that outputs a start-up signal when a session establishment request signal is received from a PC and when determined that the recording unit is in the low-power consumption state, and a persistent connection control unit that performs persistent connection control to prohibit the PC from transmitting the data while a session is maintained with the PC until the recording unit is started up.

Abstract: According to one embodiment, a server system includes a motherboard partition that includes a motherboard and at least one processor coupled to the motherboard, with each processor being coupled to a memory. The server system also includes a storage partition that includes the memory, and a power circuit being capable of supplying current to the motherboard partition and the storage partition independently, the power circuit including at least two redundant power supplies in parallel in the power circuit, with each redundant power supply being capable of providing an amount of current necessary to operate the server system, and the motherboard partition is adapted to run a server OS. In another embodiment, an active cluster system may include two server systems, with the motherboard partition from each server system being capable of communicating with the other server system's storage partition even if power is removed from the other system's motherboard partition.

Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

Abstract: A power supply unit for providing power to servers and a power supply system for servers is disclosed. The power supply unit for providing power to servers, comprises a housing; a plurality of power supplies arranged in the housing, the plurality of power supplies comprising a first output end and a second output end; a circuit board comprising a first conductive plate and a second conductive plate, the first conductive plate being electrically connected with the first output end, and the second conductive plate being electrically connected with the second output end; and an integrated management module electrically connected with the circuit board.

Abstract: A motherboard includes a central processing unit (CPU), a drive, and a voltage-state display system to display a voltage mode of the CPU. The voltage-state display system includes a power management chip, a first transistor, a second transistor, a first light emitting diode (LED), and a second LED. A first phase output terminal of the power management chip is connected to the first LED through the first transistor. A second phase output terminal of the power management chip is connected to the second LED through the second transistor. The LEDs indicate the voltage mode of the CPU.

Abstract: Systems and methods are disclosed for providing supplemental power to a battery powered information handling systems. The disclosed systems and methods may be implemented to intelligently control the selected use of supplemental power so as to reduce or substantially prevent an increase in battery usage cycle count by only allowing use of supplemental power above a given minimum supplemental battery charge level threshold. Battery cycle count may be further enhanced by only again allowing recharging of the system battery pack when its charge level drops below the minimum supplemental battery charge level threshold, and then recharging to a maximum recharge battery charge level threshold which also may be selectable by a user and/or provider of the information handling system.

Abstract: A method for reducing power consumption based on a motion sensor and a portable terminal adapted to the method are disclosed. The method includes terminating driving of a motion recognition program according to whether an input is detected by at least one sensor unit disposed in the portable terminal, and switching a mode of a controller included in the portable terminal into a motion recognition deactivation mode. The motion sensor-based portable terminal can reduce the power consumption, thereby lengthening the life span of the battery. The user can use the motion sensor-based portable terminal for a long period of time without frequently recharging its battery.

Abstract: A method for modifying one or more characteristics of a mobile electronic device in order to save or reduce power consumption of the device. The method includes determining by, a processor of the mobile electronic device, an estimated use of the mobile electronic device during an upcoming time period; using the estimated use, determining, by the processor, whether an internal power source of the mobile electronic device has sufficient power to continue operation of the mobile electronic device in a first state during the upcoming time period; based on the estimated use and the internal power source, if the internal power source does not have sufficient power, adjusting the one or more characteristics to reduce a power consumption of the mobile electronic device during the upcoming time period.

Abstract: An image forming apparatus includes a communication interface receiving data; a buffer storing the data; a main system processing the stored data; a subsystem controlled by the main system to perform a function of the image forming apparatus; a system control unit; and a data processing unit. The system control unit switches an operation status mode of the image forming apparatus between a normal status mode and a deep sleep status mode. When the image forming apparatus is in the deep sleep status mode, the data processing unit processes the data received from the buffer if the data is determined to be processable by the data processing unit and causes the system control unit to switch the operation status mode from the deep sleep status mode to the normal status mode if the received data is determined not to be processable by the data processing unit.

Abstract: Embodiments of the invention relates generally to electrical and electronic hardware, computer software, wired and wireless network communications, and computing devices, and more specifically to structures and techniques for managing power generation, power consumption, and other power-related functions in a data-capable strapband. Embodiments relate to a band including sensors, a controller coupled to the sensors, an energy storage device, a connector configured to receive power and control signals, and a power manager. The power manager includes at least a transitory power manager configured to manage power consumption of the band during a first power mode and a second mode. The band can be configured as a wearable communications device and sensor platform.

Abstract: An interface card is capable of communicating with an external device and includes a power supplier; a non-volatile memory which stores executable instructions to operate in an active-mode and a sleep-mode; a small-capacity volatile memory which is supplied with power in the sleep mode; a transmitter-receiver which transmits and receives packet data to/from the external device; and a controller which retrieves sleep-mode instructions stored in the non-volatile memory and loads the sleep mode instructions in the small-capacity volatile memory to transition the interface card into the sleep mode if the transmitter-receiver does not receive the packet data for predetermined time period in an active mode. The interface card processes certain packet data in the sleep mode and transitions back into the active mode when sleep mode operations determine that the packet data cannot be processed in the sleep mode.

Abstract: A method of determining the downstream propagation time of signals from a USB Host Controller across one or more USB cables and one or more USB Hubs to a SuperSpeed USB device, including locking a clock of the SuperSpeed USB device to information that includes a first timestamp, transmitting a plurality of signals to the USB Host Controller, each of the signals containing a second timestamp indicative of a local time of the SuperSpeed USB device when the respective signal was generated by the SuperSpeed device; the USB Host Controller creating a third timestamp indicative of a time of reception from the SuperSpeed USB device; determining a time period from one or more respective time differences between corresponding second and third timestamps, the time period being indicative of a sum of a downstream propagation time and an upstream propagation time; and determining the downstream propagation time from the time period.

Abstract: Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.

Abstract: Managing firmware in a computing system storing a plurality of different firmware images for the same firmware includes: calculating, for each firmware image in dependence upon a plurality of predefined factors, a preference score; responsive to a failure of a particular firmware image, selecting a firmware image having a highest preference score; and failing over to the selected firmware image.

Abstract: A method, for handling partially inconsistent states among members of a cluster in an erratic storage network that responds to requests from a client, includes assigning a unique commit identifier corresponding to each successive modification of state of the cluster when an update request has been successfully completed and correlating an incoming request to a given member of the cluster with any commit identifiers necessary to satisfy the request. The method further includes detecting, on the incoming request to the given member of the cluster, whether the commit identifiers necessary to satisfy the request have been applied to the given member, and processing the incoming request based on whether the commit identifiers necessary to satisfy the request have been applied to the given member. Operation of the members can be asynchronous.

Abstract: A method for managing multiple nodes hosting multiple memory segments, including: identifying a failure of a first node hosting a first memory segment storing a hypervisor; identifying a second memory segment storing a shadow of the hypervisor and hosted by a second node; intercepting, after the failure, a hypervisor access request (HAR) generated by a core of a third node and comprising a physical memory address comprising multiple node identification (ID) bits identifying the first node; modifying the multiple node ID bits of the physical memory address to identify the second node; and accessing a location in the shadow of the hypervisor specified by the physical address of the HAR after the multiple node ID bits are modified.

Abstract: A method includes establishing an expected traffic load for a plurality of servers, wherein each server has a respective actual capacity. The method further includes limiting the actual capacity of each server to respective available capacities, wherein a combined available capacity that is based on the available capacities corresponds to the expected traffic load. The method also includes dynamically altering the respective available capacity of the servers based on the failure of at least one server.

Abstract: A mechanism is provided for controlling a solid state disk. A failure detector detects a failure in the solid state disk. Responsive to failure detector detecting a failure, a status degrader sets a degraded status indicator for the solid state disk. Responsive to the degraded status indicator, a degraded status controller maintains the solid state disk in operation in a degraded operation mode.

Abstract: Approaches for recovering nodes and adding new nodes to object stores maintained on one or more solid state devices. At a surviving node, in a cluster of nodes, replicating, to a recovering node in the cluster of nodes, all requests to modify data stored in a first data store thereon that are received by the surviving node. The surviving node performing a bulk copy operation to copy data, stored in the first data store, to a second data store maintained on the recovering node. The surviving node (a) replicates all requests to modify data received by the surviving node and (b) performs a bulk copy operation in parallel.

Abstract: The application discloses systems that can include a monitoring module that is operative to provide an event indicator of an event occurring on a hard-disk drive. The systems can include a recording module that is operative to create an event record based on a logging instruction to log the event indicator. The systems can include an event linkage module that is operative to link the event record to a hard-disk drive activity indicator. The systems can include an error log formatting module that is operative to format the event record and a hard-disk drive activity indicator into a hard-disk drive error log. The systems can include a configuration module to set configuration flags and/or values. The error log can be stored on various areas of the hard-disk drive. The application also discloses related methods.

Abstract: A method and device offering a software diversity of the cited type for floating-point arithmetic, which is applicable in a realtime environment, wherein the method and a device for high-performance validation of the calculation use floating-point numbers of any accuracy within the context of functional safety in accordance with International Electrotechnical Commission (IEC) standard 61508. The method utilizes a specific form of software diversity and has effects on both the runtime environment and the engineering environment.

Abstract: Computer-implemented methods and systems are provided for scanning web sites and/or parsing web content, including for testing online opt-out systems and/or cookies used by online systems. In accordance with one implementation, a computer-implemented method is provided for testing an opt-out system associated with at least one advertising system that uses cookies. The method includes transmitting a first request to an opt-out system, wherein the first request corresponds to a first test for testing at least one of the opt-out system and an advertising system; receiving a first stream sent in response to the first request; determining a first outcome of the first test based on the first stream; and generating a report based on the first outcome.

Abstract: In one embodiment, a digital asset testing system 200 may test a digital asset 202 before posting at a digital distribution store. A communication interface 180 may receive a digital asset 202. A processor 120 may execute testing of the digital asset 202 on a testing virtual machine 212 of a virtual machine set. The processor 120 may execute testing of the digital asset 202 simultaneous with testing executed on each virtual machine 212 of the virtual machine set. The processor 120 may delay testing of the digital asset 202 on the testing virtual machine 212 if a testing virtual machine configuration 214 is stale.

Abstract: Embodiments of the invention include methods, apparatuses, and systems for automatically identifying a synchronization sub-pattern associated with a test pattern. A test and measurement instrument is triggered in response to a first instance of a trigger pattern in a data stream. A trigger-to-trigger counter begins counting at the time of the first trigger event. The test and measurement instrument is again triggered in response to a second instance of the trigger pattern in the data stream. The count is ended at this time. The count is then compared to a predefined length of the test pattern, and if equal, it is automatically determined that the trigger pattern is the unique synchronization sub-pattern associated with the test pattern.

Abstract: In a method for detecting memory errors occurring in a computing device, a channel number of an error memory module is obtained from a first register of a memory controller of the computing device. The method analyzes an error type to obtain a rank number of the memory module from one or more specified registers of the memory controller, and finds a serial number of a memory slot into which the memory module has been inserted. According to the serial number of the memory slot and a distribution list, the method can detect the memory slot which is carrying the memory module.

Abstract: An example system includes a bus, a logic device, a controller, and a non-volatile memory. The bus is configured to propagate data including at least system console output data. The logic device is configured to monitor the data on the bus and to store the system console output data in a buffer. The controller is configured to detect a system error, and, in response to the system error, to acquire at least a portion of the system console output data from the buffer. The non-volatile memory is configured to store the portion of the system console output data acquired by the controller.

Abstract: Method, computer program product, and system for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination.

Abstract: Provided is a test apparatus including: an address generator that generates an address of a memory under test; a selector that selects whether to perform bit inversion on the address generated by the address generator before supplying the address to the memory under test; an inversion processing section that outputs the address generated by the address generator after performing bit inversion on the address if the selector has selected in the affirmative, and outputs the address generated by the address generator without performing any bit inversion on the address if the selector has selected in the negative; and a supply section that supplies, to the memory under test, the address having undergone inversion control outputted from the inversion processing section and an inversion cycle signal that indicates whether the address outputted from the inversion processing section is bit inverted or not.

Abstract: A method and an apparatus for performing link equalization testing via a physical layer test and measurement system. The system includes a protocol aware test apparatus for transmitting testing data, a device under test for receiving the transmitted testing data, and an oscilloscope for receiving an output waveform from the device under test. The protocol aware test apparatus selects a first of a plurality of preset values, sends an equalization signal from the protocol aware test apparatus to the device under test, and changes a speed of communication to a predetermined speed and sends a compliance pattern to the device under test after placing the device under test in a loopback mode. A waveform output from the device under test is captured by the oscilloscope, and is analyzed to determine compliance of the device under test with a predetermined link equalization speed in accordance with a predetermined protocol.

Abstract: Provided are techniques for receiving a packet transmitted in conjunction with a security association associated with Internet Protocol Security (IPSec); determining, based upon the security Association that the packet is faulty; incrementing a count corresponding to previous faulty packets received; determining that the count exceeds a threshold; and disabling IPSec accelerator hardware in response to the determining that the count exceeds the threshold.

Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values.

Abstract: Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.

Abstract: A method and apparatus for detecting clock glitches during at-speed testing of integrated circuits is disclosed. In one embodiment, an integrated circuit includes a scan chain having a number of scan elements coupled in a series configuration. Each of the scan elements is coupled to receive a clock signal that may be cycled during a test operation. A subset of the scan elements are arranged to form, along with other components, a counter. Test stimulus data shifted into the scan chain to perform a test may include an initial count value that is shifted into the scan elements of the counter. When the test is performed, the count value is updated responsive to cycling of the clock signal. The updated count value is shifted from the counter along with other test result data, and may be used to determine if the number of clock cycles received during the test.

Abstract: An integrated circuit comprises scan test circuitry and additional internal circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, with each such scan chain comprising a plurality of flip-flops configurable to operate as a serial shift register. The plurality of scan chains are arranged in sets of two or more parallel scan chains. The scan test circuitry further comprises multiplexing circuitry, including a plurality of multiplexers each associated with a corresponding one of the sets of parallel scan chains and configured to multiplex scan test outputs from the parallel scan chains within the corresponding one of the sets of parallel scan chains. In one embodiment, one or more of the sets of parallel scan chains comprise respective pairs of parallel scan chains with each such pair corresponding to a single original scan chain.

Abstract: Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described mechanisms and techniques can function to detect defects in interconnects which vertically connect different layers of a 3D device, as well as to detect defects on a 2D layer of a 3D integrated circuit. Additionally, according to an embodiment of the present disclosure, techniques and mechanisms are provided for determining not only the presence of a defect in a given set of interfaces of an integrated circuit, but the particular interface at which a defect may exist.

Abstract: The disclosed device performs a control of generating a test pattern for the delay test of LSI. The input pattern control circuit counts a cycle number of an input pattern supplied to a test object circuit, and stops supply of the input pattern to the test object circuit when the cycle number of the input pattern coincides with a certain count number. The scan control circuit receives a control signal from the input pattern control circuit, and supplies a scan shift signal to the test object circuit to shift a scan chain in the test object circuit.

Abstract: A self-test module for use in an electronic device includes a test controller and a memory. The memory is configured to receive test vectors from the test controller. A comparator is configured to receive the test data from the memory via an output data path. A strobing buffer is located in the output data path between an output from the memory and an input to the comparator. The strobing buffer is configured to selectively enable the test vectors to propagate from the memory output to the comparator input.

Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 20 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 20-bit length corresponding to columns of the code generation matrix. If “A” is 10, individual basis sequences of the code generation matrix correspond to column-directional sequences of a specific matrix composed of 20 rows and 10 columns. The specific matrix is made from 20 rows of the (32,10) code matrix used for TFCI coding were selected.

Abstract: A concatenated coded modulation communication system and method combines Trellis Coded Modulation with non-Gray code constellation mapping, interleaving, and non-binary Low Density Parity Check coded channel modulation with Gray code constellation mapping to improve error performance.

Abstract: In one embodiment, a system includes logic adapted to read a plurality of data sets from a medium one or more times; logic adapted to store portions of some of the data sets to a reserved data buffer when the portions are correctable using C1-error correction code (ECC); logic adapted to aggregate all stored portions for each of the complete data sets to form assembled data sets; logic adapted to determine whether C2-ECC is capable of correcting all errors in the assembled data sets, to correct any remaining errors in the assembled data sets, and to send the corrected data sets to a host when C2-ECC is capable of correcting all errors in the assembled data sets; and logic adapted to reread at least a first uncorrected data set from the medium using a different setting when an error in the first uncorrected data set is not correctable.

Abstract: The ability to accurately and efficiently calculate and report communication errors is becoming more important than ever in today's communications environment. More specifically calculating and reporting CRC anomalies in a consistent manner across a plurality of communications connections in a network is crucial to accurate error reporting. Through a normalization technique applied to a CRC computation period (e.g., the PERp value), accurate error identification and reporting for each individual connection can be achieved.

Abstract: Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die.

Abstract: A method of controlling a nonvolatile semiconductor memory includes checking, at a first interval period, an error count of data stored in a first group, the first group including a plurality of blocks/units, and when a first block/unit in the first group satisfies a first condition, assigning the first block/unit to a second group. The method includes checking, at a second interval period, an error count of data stored in the second group, the second interval period being shorter than the first interval period, and when a second block/unit in the second group satisfies a second condition, moving data stored in the second block/unit to an erased block/unit in which stored data is erased among the plurality of blocks/units.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.

Abstract: An adaptive controller for a configurable audio coding system including a fuzzy logic controller modified to use reinforcement learning to create an intelligent control system. With no knowledge of the external system into which it is placed the audio coding system, under the control of the adaptive controller, is capable of adapting its coding configuration to achieve user set performance goals.

Abstract: Adaptive error correction for non-volatile memories is disclosed that dynamically adjusts sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The adaptive error correction can also be used with respect to memories that are not non-volatile memories.

Abstract: A method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. In one embodiment of the invention, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction.

Abstract: Techniques for efficiently and accurately computing log-likelihood ratio (LLRs) for code bits are described. A set of code bits may be mapped to a modulation symbol in a signal constellation. Different code bits in the set may be associated with different LLR functions. A receiver obtains received symbols for a transmission sent via a communication channel. The receiver derives LLRs for code bits based on the received symbols and piecewise linear approximation of at least one LLR function. The piecewise linear approximation of each LLR function may comprise one or more linear functions for one or more ranges of input values. The receiver may select one of the linear functions for each code bit based on a corresponding received symbol component value. The receiver may then derive an LLR for each code bit based on the linear function selected for that first code bit.

Abstract: One aspect provides a method. The method comprises receiving a signal comprising a sequence of encoded symbols, each corresponding to one of a plurality of possible states. For each symbol in the sequence, the method further comprises determining a set of state metrics, each representing a probability that the respective symbol corresponds to the plurality of states. The method further comprises decoding the signal by processing runs of recursions using runs of forward recursions, whereby a later state metric in the sequence is updated based on a preceding state metric, and runs of recursions using runs of reverse recursions, whereby a preceding state metric in the sequence is updated based on a later state metric. The method further comprises outputting the decoded signal to a device. The decoding comprises performing a plurality of repeated iterations over the sequence.

Abstract: An apparatus and method for reducing power consumption of a receiver by performing a Hybrid Automatic Repeat reQuest (HARQ) according to a detected decoding error are provided. The apparatus includes a decoding reliability metric generator for setting a decoding result as a decoding reliability metric, which is a reference value for determining a code block having a decoding error, based on a decoding result, a decoding reliability metric buffer for storing the decoding reliability metric set by the decoding reliability metric generator and a code block controller for, when the decoding error occurs, identifying code blocks having the decoding error by checking the decoding reliability metric and for controlling to decode the identified code blocks.