Abstract: An adaptive slope generator can include a current mirror configured to receive a multiplied current that varies as a function of an output voltage and a switching frequency of a switching current. The output voltage can characterize the switching current provided to a load coupled to an inductor. The current mirror can also be configured to receive an oscillation current. The oscillation current can have an amplitude that corresponds to the switching frequency of the switching current. The current mirror can be further configured to generate an output current substantially equivalent to the product of the oscillation current and the output voltage. The adaptive slope generator can also include a ramp generator configured to generate a compensation signal based on the output current. The compensation signal can have a sawtooth shape and a slope that varies as a function of the output voltage.

Abstract: A radio frequency (RF) system is disclosed. The RF system includes an RF sensor, an analog to digital converter (ADC) module, a processing module, and a synchronization module. The RF sensor measures a parameter of an RF output and generates an RF signal based on the parameter. The ADC module converts samples of the RF signal into digital values. The processing module generates processed values based on the digital values. The synchronization module outputs one of the processed values in response to a transition in the RF output.

Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

Abstract: Aspects of enhanced recovery mechanisms are described. A predetermined operating parameter for a power rail is set at the outset of system start. Afterwards, a processor is released to start with a power management circuit. In turn, the power management circuit receives a default operating parameter for the power rail from the processor, and stores the default operating parameter. The power management circuit also receives a runtime operating parameter for the power rail from the processor and modifies the operating parameter for the power rail according to the runtime operating parameter. If an error condition in the processor is encountered, the power management circuit may modify the operating parameter for the power rail according to the default operating parameter in response to a reset control signal from the processor. Use of the default operating parameter for the power rail may assist the processor to recover from the error condition.

Abstract: A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.

Abstract: A reconfigurable circuit is disclosed. The reconfigurable circuit comprises a pause detector mechanism, a clock extractor, and a multiplexer. The multiplexer is configured to receive a reference clock and is coupled to the clock extractor to receive a clock extracted from a carrier of a near field communication (NFC) field. The reconfigurable circuit also comprises a phase locked loop (PLL) coupled to the pause detector mechanism and the multiplexer, and the PLL can be configured in a first mode to be locked to the reference clock, in a second mode to be locked to the extracted clock, and in a third mode wherein the PLL can switch between being locked to the reference clock and being locked to the extracted clock.

Abstract: A semiconductor device includes a latch circuit. The latch circuit includes a sampling section that latches a differential input signal applied from a differential input node to the gates of a differential pair of transistors, a common adjusting section that adjusts a common potential of the differential input signal by adjusting based on a current control signal the amount of current that is drawn from the differential input node, and a common control section that controls the current control signal so that the differential pair of transistors operate in a saturated region, and supplies the controlled current control signal to the common adjusting section.

Abstract: A loop filter is described. The loop filter has first and second inputs and an output. A loop filter capacitor is coupled to the loop filter output. Sample switches are coupled to the second loop filter input. A voltage divider is coupled to reset switches. Switched capacitors are coupled to sample switches, the reset switches, the loop filter capacitor, and the loop filter output.

Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.

Abstract: An approach is provided for modulating an input clock signal of a clock source. In one example, a modulated clock device receives the input clock signal from the clock source, applies a sequence of digital delay devices to the input clock signal to generate one or more delayed phases of the input clock signal, sends the input clock signal and the one or more delayed phases of the input clock signal to an output phase multiplexer, selects an appropriate phase of the input clock signal from among the input clock signal and the one or more delayed phases of the input clock signal, and generates an output clock signal based on the appropriate phase of the input clock signal.

Abstract: Fast phase coordinating systems and methods are disclosed. An example system includes a phase locator configured to detect a first phase of a reference signal and a first phase of a coordinating signal after the first phase of the reference signal. An integrator is configured to integrate from the first phase of the reference signal to a location phase of the coordinating signal and integrate oppositely from the first phase of the coordinating signal to a time-shifted phase of the reference signal and output the result. A control function is configured to shift the phase of the coordinating signal in response to output from the integrator.

Abstract: Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.

Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.

Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.

Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.

Abstract: Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.

Abstract: A method for converting a sine wave signal into a square wave signal includes inputting the sine wave signal at an input of a threshold-value device that generates the square wave signal. The square wave signal is generated by comparing a sine wave signal value to a predefined threshold value, and the square wave signal is output at an output of the threshold-value device. An actuating signal is superposed on the sine wave signal at the input of the threshold-value device. The actuating signal is generated by forming an average-value signal representing an average value of the square wave signal and inputting the average-value signal at an input of a control amplifier device for generating, as the actuating signal, a signal representing a difference between an average-value signal actual value and a predefined average-value signal nominal value.

Abstract: The present disclosure presents a signal regulation device for an oxygen sensor which features a voltage regulation module connected between an automobile system and an oxygen sensor in series through an input module and an output module, changing initial voltage generated by the oxygen sensor, transmitting regulated voltage to the automobile system via the output module, and interfering with a catalytic converter for processed oxygen content to be detected by the oxygen sensor.

Abstract: An electronic USB or similar device 101 with a CMOS audio output stage 105 for driving, in a first mode, e.g., a headset via a port commonly used also in a second mode by a digital data transmission stage 103 for digital data and supply, the audio output stage P-channel transistor MP being switchably back-gate biased by a bias circuit 107 according to the operating mode to achieve high-voltage tolerance.

Abstract: In accordance with an embodiment, a method of operating a gate driving circuit includes monitoring a signal integrity at an output of the gate driving circuit. If the signal integrity is poor based on the monitoring, output of the gate driving circuit is placed in a high impedance state and an external signal integrity failure signal is asserted.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing uniform voltage swing across a transmit switch for improved device performance. A switching circuit includes a switch having field effect transistors (FETs) defining an RF signal path between the input port and the output port, the switch configured to be capable of being in a first state corresponding to the input and output ports being electrically connected so as to allow passage of the RF signal therebetween, and a second state corresponding to the input and output ports being electrically isolated. The switching circuit includes a voltage distribution circuit configured to reduce voltage distribution variation across the switch, including one or more elements coupled to a selected body node of one or more FETs so as to reduce voltage distribution variation across the switch when the switch is in the first state and encountered by an RF signal at the input port.

Abstract: An electronic apparatus is provided which includes switching elements, resonance suppression resistors which have first ends connected to control terminals of the switching elements and second ends having a common connection, an on-drive circuit which has an on-drive resistor and is connected to a drive power circuit, and which is supplied with voltage from the drive power circuit and applies electric charge to the control terminals of the switching elements via the on-drive resistor to turn on the switching elements, and an off-drive circuit which has an off-drive resistor and releases electric charge from the control terminals of the switching elements via the off-drive resistor to turn off the switching elements. A resistance of the off-drive resistor is set to be smaller than a resistance of the resonance suppression resistors. The off-drive circuit releases electric charge from the control terminals of the switching elements not via the resonance suppression resistors.

Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

Abstract: A period signal generation circuit including a control voltage generator and a period controller. The control voltage generator selecting one of temperature-dependent voltages to output the selected temperature-dependent voltage as a control voltage. The first and second temperature-dependent voltages varying according to a temperature and the third temperature-dependent voltage is constant regardless of variation of the temperature. The period controller configured to determine an amount of a current discharging from an internal node in response to the control voltage and outputs a periodic signal whose cycle time is determined according to a level of an internal signal induced at the internal node.

Abstract: An integrated circuit (IC) including a high-speed signal input pin, a common node, a high-speed signal output pin, and a core circuit is provided. The high-speed signal input pin and the high-speed signal output pin are disposed on a package of the IC. The common node and the core circuit are disposed in the IC. The common node is directly and electrically coupled to the high-speed signal input pin. The high-speed signal output pin is directly and electrically coupled to the common node. A high-speed signal input terminal of the core circuit is directly and electrically coupled to the common node.

Abstract: The presented device is the combination of a lock-in amplifier unit (1) and a phase-synchronous processing unit (2). This combination leads to a multitude of valuable signal analysis and conditioning possibilities. Amongst others, these possibilities include (i) extraction of time-domain properties of the input signal, (ii) extraction of statistical properties of the input signal, (iii) extraction of frequency-domain properties of the input signal, and (iv) preconditioning of the lock-in input signal.

Abstract: An object of the present invention is to provide a power amplification device having high power efficiency for an input signal even in a power region in a large back-off. A power amplification device of the present invention includes a delta-sigma modulator which performs a multilevel delta sigma modulation on amplitude signals of input signals, a plurality of power amplifiers which amplify carrier signals, an encoder which generates a first control signal that controls ON/OFF of the outputs from said plurality of power amplifiers in accordance with the output from said delta-sigma modulator, and a combiner which combines at least two power output from said plurality of power amplifiers in accordance with said first control signal.

Abstract: An amplifier includes: an amplifying device configured to amplify an input signal; and a matching circuit coupled to the amplifying device, and including an impedance transformer and a parallel resonance circuit coupled to a wiring which spans from the impedance transformer to the amplifying device, wherein a circuit length of the impedance transformer is longer than one-fourth of wavelength of an electronic wave having a frequency which is substantially equal to a resonance frequency of the parallel resonance circuit.

Abstract: A power amplifier power controller in the power amplifier system monitors various operating conditions of the power amplifier, and controls the output transmit power of the power amplifier by coordinated control of both the input drive level to the power amplifier and the gain of the power amplifier. The power amplifier power controller controls the input drive level to the power amplifier so that the input drive level does not change substantially while adjusting the gain of the power amplifier to maximize the transmit power. The power amplifier power controller may also adjust the input drive level by some portion of the overall change required to the power of the power amplifier, while adjusting the gain of the power amplifier by the remaining portion of such overall change.

Abstract: Aspects disclosed herein relate to providing an efficiently predistorted input signal to a high-efficiency PA. A wireless communications device may be include a power amplifier and a processor that is associated with a predistortion module. In an aspect, the processor may be a modem, a RF chip, etc. In one example, the pre-distortion module may be configured to receive an input signal and a supply voltage associated with the input signal. The predistortion module may be further configured to apply predistortion to the input signal using a linear manipulation associated with the predistortion lookup table. In an aspect, the linear manipulation may adjust the input signal based on one or more non-linear device characteristics associated with the supply voltage.

Abstract: There is described a method of controlling signal alignment in a power amplifier, comprising: receiving an input signal to be amplified; receiving a supply voltage for the power amplifier, the supply voltage being derived in dependence on the signal to be amplified; amplifying the input signal to produce an output signal; comparing the output signal with a plurality of distorted versions of the input signal, each distorted version of the input signal being associated with a different time delay value; and adjusting the timing of either the input signal or the supply voltage by an amount in dependence on a time delay value determined to be associated with a distorted version of the input signal which most closely matches the output signal.

Abstract: There is provided an amplification stage including an envelope tracking modulated supply for tracking a reference signal, comprising a low frequency path for tracking low frequency variations in the reference signal and for providing a first output voltage, and a high frequency path for tracking high frequency variations in the reference signal and for providing a second output voltage, and a combiner for combining the first and second output voltages to provide a third output voltage, the amplification stage further comprising a first amplifier arranged to receive the first output voltage as a supply voltage, and a second amplifier arranged to receive the third output voltage as a supply voltage, wherein the first and second amplifiers are enabled in different modes of operation.

Abstract: A sensing amplifier using capacitive coupling and a dynamic reference voltage, where the sensing amplifier circuit includes a bit line, configured to receive charging and discharging signals; a sensing amplifier, connected to the bit line and configured to receive the bit line and a reference voltage for comparison and configured to enlarge the voltage difference between a high point and a low point; and a reference voltage generator, connected to the sensing amplifier to generate the reference voltage required for the sensing amplifier to compare. The sensing amplifier effectively enhances sensing margin of the sensing amplifier circuit; and in addition, to accelerate the access speed, the sensing amplifier can easily determine the correct stored data and further quickly solve the problems of high-speed storing the data by the storage units.

Abstract: An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided.

Abstract: An operational amplifier (10) capable of driving a capacitive load (CLOAD) and/or a resistive load (RLOAD) includes a first gain stage (2) having an output coupled to a high impedance node (3) and a second gain stage (5) having an input coupled to the first high impedance node. A gain reduction resistor (RD) and an AC coupling capacitor (CD) are coupled in series between the high impedance node and a reference voltage. A Miller feedback capacitor (CM) is coupled between an output conductor (7) of the second gain stage and the high impedance node. The output of the second gain stage may be coupled to the high impedance node by a cascode transistor (MCASCODE).

Abstract: A dynamic feed-forward OPAMP-based circuit is provided. A first amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. A second amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is coupled to a non-inverting input terminal of the first amplifying stage. A second capacitor is coupled to an inverting input terminal of the first amplifying stage. A feed-forward transconductance stage is coupled between the first and second capacitors and the second amplifying stage. The first and second capacitors and the feed-forward stage form a high-frequency path with a first gain curve, and the first amplifying stage and the second amplifying stage form a high-gain path with a second gain curve. The operational amplifier provides an open-loop gain according to the first and second gain curves.

Abstract: A method includes, in at least one aspect, receiving, at both an input node of a first input stage and in input node of a second input stage, a single-ended voltage signal; providing, by at least one of the first input stage or the second input stage, inductive degeneration to the single-ended voltage signal; converting an output from the first input stage into a first single-ended current signal; converting an output from the second input stage into a second single-ended current signal; and outputting, by an output stage, a differential output including the first single-ended current signal and the second single-ended current signal.

Abstract: Disclosed is a current compensation circuit. During calibration of a compensation current, a digital control circuit delivers a digital signal with values varying over time to a current compensation array, the current compensation array outputs different amounts of compensation current based on the digital signal with values varying over time, the digital control circuit latches a value of the digital signal, which results in a best compensation current, based on influences of the different amounts of compensation current on a parameter to be calibrated, to complete the calibration. Upon and after completion of the calibration, the digital control circuit continuously delivers the digital signal with the latched value to the current compensation array, and the current compensation array outputs the best compensation current based on the digital signal with the latched value.

Abstract: The present invention relates to a power amplifier apparatus and a power amplifier circuit thereof, the power amplifier circuit uses Doherty circuit structure, and the final stage power amplifier circuit uses high electron mobility transistor (HEMT) power amplifiers to achieve a Carrier amplifier with the Doherty circuit structure and a Peak amplifier with the Doherty circuit structure. The power amplifier apparatus and a power amplifier circuit thereof in the present invention improves the efficiency of the power amplifier.

Abstract: The present invention relates to a voltage regulating device comprising a power stage (30) comprising an inductor (L) between a first node (P1) and a second node (P2); a first switch (A) between the first node (Pi) and a power supply node (P3) for which the potential (Vbat) is non-zero and of constant polarity; a first capacitor (CNEG) between a node (P5) at a reference potential and a second switch (B) coupled to the first node (P1); a second capacitor (CPOS) between a node (P7) at the reference potential and a third switch (C) coupled to the second node (P2); a fourth switch (D) between the second node (P2) and a node (P8) at the reference potential; a fifth switch (E) between the first node (P1 and a node (P9) at the reference potential; a first output (P4) for delivering a first voltage corresponding to the voltage at the terminals of the first capacitor (CNEG); a second output (P6) for delivering a second voltage corresponding to the voltage at the terminals of the second capacitor (CPOS); The power stag

Abstract: A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.

Abstract: One embodiment of communication system comprises a crystal oscillator configured to output a reference clock; cellular radio frequency (RF) and baseband phase locked loops configured to receive the reference clock within a cellular module and compensate for calculated frequency errors between a received cellular downlink signal and a cellular local oscillator signal during operation of the cellular module; global positioning system (GPS) frequency compensation circuitry configured to receive the reference clock within a GPS module and compensate for calculated frequency errors during operation of the GPS module; and a temperature sensing circuit which includes a plurality of sensing resistors and is configured to output a signal corresponding to a temperature of a reference crystal which is translated to a frequency deviation, wherein the (GPS) frequency compensation circuitry is configured to offset the frequency deviation and output a temperate compensated signal to meet GPS clock frequency requirements.

Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.

Abstract: A surface mount device-type low-profile oscillator is provided. A main surface of an IC chip unit is joined to a bottom surface where the external terminals of a crystal unit section are formed. An integrated circuit portion includes a circuit forming, together with the crystal unit of the crystal unit section, an oscillator circuit on the main surface of the IC chip unit, and IC terminals formed with a plurality of IC electrode terminals, and two connection terminals connecting the external terminals of the crystal unit section are provided. The IC electrode terminals and mounting terminals are electrically connected with electrical columns provided in via holes penetrating in the direction of thickness of a silicon plate of a bare chip. The crystal unit section and the IC chip unit are joined with an anisotropic conductive adhesive applied to the main surface of the IC chip unit.

Abstract: An oscillator is provided including a nanopillar and current injector for injecting a power supply current through the nanopillar, the nanopillar including at least one pattern including first and second layers made from a ferromagnetic material separated from each other by an intermediate layer made from a non-magnetic material. Each of the first and second ferromagnetic layers is prepared such that its remanent magnetic configuration corresponds to a vortex configuration and the polarity of the vortex core of the first layer is opposite the polarity of the vortex core of the second layer. The intermediate layer can allow repellant magnetic coupling between the two vortices of the first and second layers, for a zero intensity of the power supply current and a zero amplitude of the outside magnetic field.

Abstract: A temperature compensation apparatus may include a sense circuit configured to produce a sense voltage that is dependent on temperature and a temperature compensation circuit configured to receive the sense voltage and produce a temperature compensation control signal to control a compensation capacitor array of an oscillator. The temperature compensation circuit may be configured to calibrate the control signal to have a first value at a first temperature. The temperature compensation circuit may also be configured to calibrate a trimming level (e.g., slope) of the control signal.

Abstract: An apparatus for generating an oscillating output signal includes an inductive-capacitive (LC) circuit and a current tuning circuit. The LC circuit includes a primary inductor and a varactor coupled to the primary inductor. A capacitance of the varactor is responsive to a voltage at a control input of the varactor. The current tuning circuit includes a secondary inductor and a current driving circuit coupled to the secondary inductor. The current driving circuit is responsive to a current at a control input of the current driving circuit. An effective inductance of the primary inductor is adjustable via magnetic coupling to the secondary inductor, and a frequency of the oscillating output signal is responsive to the effective inductance of the primary inductor and to the capacitance of the varactor.