Abstract: A power conversion system with adjustable frequency includes an electric transformer, a pulse width modulation driving controller, a switching transistor, a first and second voltage division resistors connected in series, an output diode and an output capacitor. The electric transformer receives the input power and generates the sensing current and induced current. The sensing current flows through the first and second voltage division resistors to generate the feedback signal. The induced current flows through the output diode and output capacitor to generate the output voltage to supply the load. The pulse width modulation driving controller determine whether the loading state of the load based on the feedback signal, and change the switching frequency according to the loading state and the input power, thereby increasing the whole efficiency of the power conversion system and achieving the aim of dynamically adjusting the optimal frequency.

Abstract: System and method for regulating a power conversion system. An example system controller includes: a first controller terminal and a second controller terminal. The system controller is configured to: receive an input signal at the first controller terminal and generate a first drive signal at the second controller terminal based on at least information associated with the input signal to turn on or off a transistor to affect a current associated with a secondary winding of the power conversion system. The system controller is further configured to: in response to the input signal changing from a first value larger than a first threshold to a second value smaller than the first threshold, change the first drive signal from a first logic level to a second logic level to turn on the transistor.

Abstract: A switching power supply circuit includes a switching element that switches power fed to a primary winding of a transformer and thus induces a voltage in the secondary winding, and an oscillation circuit that oscillates to generate a pulse signal to control switching action. The oscillation circuit repeatedly performs intermittent oscillation of the pulse signal, and in each of the intermittent oscillation cycles, increases or decreases the number of pulses in the pulse signal to lengthen or shorten the oscillating portion of the pulse signal, and at the time of lengthening or shortening, the oscillation circuit respectively lengthens or shortens an oscillation-halted portion, thus varying the period of the intermittent oscillation cycles.

Abstract: A converter is suggested comprising a transformer providing a galvanic isolation between a primary side and a secondary side of the converter; at least one switching element; a converter control unit comprising a first pin for controlling the at least one switching element and a second pin for detecting a current signal in the at least one switching element during a first phase; and for detecting an output voltage signal of the secondary side of the converter and an information regarding a current in a secondary winding of the transformer during a second phase.

Abstract: A power conversion device has a power module that switches the ON/OFF state of a switching element and converts and outputs input power, a metal housing that houses the power module, and a conductive member connected to the housing. The conductive member is connected to the housing at a position having a length of n?/4 from the open end. More specifically, “n” is an odd number of 1 or greater, “?” is the wavelength of noise generated by switching the switching element ON or OFF.

Abstract: An inverter circuit comprises an inverter which can be configurable for controlling the supply of mains current from a grid to an electric machine in a start-up mode whereby the machine drives the prime mover for initialisation. Thereafter the same inverter is reconfigurable as part of the circuit to supply reactive power to the grid when the machine is running as a generator powered by the prime mover.

Abstract: A power supply system includes: a switching power supply; a control device; an auxiliary power supply circuit, which is connected in parallel with the switching power supply with respect to an AC power supply, which includes an electricity storage unit for storing electricity by charging current fed from the alternating current power supply, and which feeds power to the control device; and a first switching unit for switching a connection state of the auxiliary power supply circuit to the alternating current power supply. The control device is configured to, upon starting up the switching power supply, switch the first switching unit into a state where the auxiliary power supply circuit is separated from the alternating current power supply.

Abstract: Design of a T-connected autotransformer based 20-pulse ac-dc converter is presented in this invention. The 20-pulse topology is obtained via two paralleled ten-pulse ac-dc converters each of them consisting of a five-phase (five-leg) diode bridge rectifier. For independent operation of paralleled diode-bridge rectifiers, a zero sequence blocking transformer (ZSBT) is designed and implemented. Connection of a tapped inter-phase transformer (IPT) at the output of ZSBT results in doubling the number of output voltage pulses to 40. Experimental results are obtained using the designed and constructed laboratory prototype of the proposed converter to validate the design procedure and the simulation results under varying loads. The VA rating of the magnetic in the proposed topology are calculated to confirm the savings in space, volume, weight, and cost of the proposed configuration.

Abstract: An additional electric power receiving method replacing conventional grounding with a negative voltage source includes the step of transmitting electromagnetic wave or current from a power supply source to a rectifier, wherein a grounding end of the rectifier is in electrical communication with the negative voltage source, and the negative voltage source is selected from a negative potential intrinsic of an organism. A device applicable to the electric power receiving method includes a rectifier having an input end and two output ends, wherein the input end is in electrical communication with a power supply source, and rectified direct current is transmitted from the output ends. With the method and device, not only an increase in additional electric power obtained is achieved, but conversion efficiency and stability of current and electromagnetic wave is enhanced.

Abstract: An inverter control module electrically connected to an inverter module is disclosed to include an error detection unit for receiving a control signal and a feedback signal from an external source and processing these signals and then outputting a corresponding error signal, a signal amplifier module electrically coupled to the error detection unit for receiving the error signal and amplifying the error signal or raising the frequency of the error signal and then outputting the processed signal, and a driver module electrically coupled to the signal amplifier module for receiving the amplified or frequency-raised error signal and generating a corresponding driving signal and then outputting the driving signal to a power module of the inverter module for driving the power module to work.

Abstract: A system that manages a supplemental energy source connected to a power grid uses a two stage control strategy to manage power transfers in and out of the power grid as well as in and out of an energy storage system, such as a battery bank. One stage uses a non-linear transfer function to control an output frequency of a DC-to-AC inverter to limit undesired effects of power transients that occur on the grid. A second stage uses control strategy for transferring energy between the energy storage system and an internal DC link based on a relationship between a voltage on a DC link connecting the first and second stages and a DC link reference voltage, the voltage on the DC link, and a voltage at the energy storage system. The control strategy includes rapid charging, over-charging protection, and grid transient stabilization.

Abstract: A multilevel converter for controlling a multilevel converter is provided. The multilevel converter is a single phase converter with one phase leg, or a three phase converter with three phase legs, the phase legs of the three phase converter are interconnected in a star-configuration. The single phase converter with one phase leg, or each three phase converter with three phase legs, phase leg includes switching cells, and each switching cell includes semi-conductor switches arranged to selectively provide a connection to a corresponding energy storage element. The converter also includes a controller, which is provided to monitor the DC voltage of the energy storage elements, and the controller is provided to control the switching of each switching cell. The phase leg of the single phase converter, or each phase leg of the three phase converter, includes two parallel branches of switching cells, the branches being configured in a closed circuit.

Abstract: A power supply circuit includes an input configured to receive an input voltage, an output configured to supply an output voltage, at least one inductor, at least one diode, and at least one switch. The inductor may have a parasitic capacitance less than about 100 pF. Related inductors are also disclosed.

Abstract: A current limiting comparator generates a current limiting signal SLIM which is asserted when a detection voltage Vs at a detection terminal CS is higher than a predetermined threshold voltage VTH. A mask signal generating unit generates a mask signal SMSK which is asserted after a predetermined delay time TMSK elapses after a switching transistor is turned on. A pulse signal generating unit has: a function (a) in which, when the set signal SSET is asserted in a period in which the current limiting signal SLIM is negated, a pulse signal SPWM is switched to a first level; and a function (b) in which, when the reset signal SRST is asserted, or when the current limiting signal SLIM is asserted in a period in which the mask signal SMSK is negated, the pulse signal SPWM is switched to a second level.

Abstract: Rectifier circuit including a pair of input terminals, a pair of output terminals, and a first circuit interconnecting the pair of input terminals. The first circuit includes an energy storing element and a rectifier bridge, wherein the rectifier bridge includes at least one controllable switching element per bridge branch. An output of the rectifier bridge supplies the pair of output terminals and wherein the at least one controllable switching element per bridge branch is configured to provide a temporary conducting path via the rectifier bridge which bypasses the pair of output terminals and which short-circuits a series connection of the energy storing element and an energy source connectable to the pair of input terminals. A converter for synchronized switch harvesting on inductor including such a rectifier circuit and a method for rectifying an electrical current generated by an energy source are also described.

Abstract: A power factor correction device comprises a power stage circuit converting input alternating current voltage into input current according to a pulse width modulation signal and outputs the input current to a load generating output voltage on the load, and sampling the input current outputting a correcting current; a current compensating circuit receiving and comparing the correcting current with a reference current signal generating a compensating current signal; a voltage compensating circuit receiving and comparing the output voltage with a reference voltage generating a compensating voltage signal; a multiplication amplifier receiving the compensating current signal and the compensating voltage signal generating an updated reference current signal by multiplying the compensating current signal with the compensating voltage signal; and a pulse width modulation converter receiving the compensating current signal and the compensating voltage signal generating the pulse width modulation signal to synchronize

Abstract: In some aspects of the invention, multiple insulating substrates each mounting thereon at least one each of at least four semiconductor devices that form at least one of three-level electric power inverter circuits and a base plate on the one surface of which a plurality of the insulating plates are arranged are provided. On the one surface of the base plate, at least four regions are established and multiple insulating substrates are arranged to be distributed so that at least one each of the at least four semiconductor devices is arranged in each of the four regions established on the base plate. This can make the semiconductor devices arranged to be distributed so that heat generating sections determined according to the operation mode of the semiconductor system comes to be partial to disperse generated heat, by which a semiconductor system is provided which can enhance heat dispersion efficiency.

Abstract: An AlGaN/GaN-HEMT has a structure including: compound semiconductor layers formed on a substrate; a gate electrode, a gate pad that has a current path formed between the gate electrode and itself, and a semiconductor layer that is spontaneously polarized and piezoelectrically polarized, which are formed on the compound semiconductor layer; and a gate electrode connection layer formed on the semiconductor layer, wherein the gate electrode connection layer and the gate electrode are electrically connected with each other. This structure which is relatively simple allows the AlGaN/GaN-HEMT to realize an intended normally-off operation without causing such inconveniences as increase in a sheet resistance, increase in an on-resistance, and increase in a leakage current.

Abstract: A system for converting a first electric voltage into a second electric voltage, comprising: at least two input terminals and two output terminals; and switching members disposed between the terminals, which can convert the first voltage into the second voltage. At least one switching member comprises at least two arms connected in parallel and each arm includes an electronic switch that can be controlled such as to occupy either an on-state or an off-state, said switch comprising a control electrode and two conduction electrodes that conduct current in the on-state. The switching member comprises a common control terminal connected to the control electrode of the switch of each arm, as well as a first common conduction terminal and a second common conduction terminal connected respectively to a first conduction electrode and a second conduction electrode of the switch of each of the arms.

Abstract: A CAM device for comparing a search key with a plurality of ternary words stored in a CAM array includes one or more population counters, a pre-compare memory, and a pre-compare circuit. The present embodiments reduce the power consumption of CAM devices during compare operations between a search key and ternary words stored in a CAM array by selectively enabling the match lines in the CAM array in response to pre-compare operations between a set of population counts corresponding to the masked search key and a set of population counts corresponding to the ternary words stored in the CAM array.

Abstract: A semiconductor chip includes a core region having a plurality of first memory cells and a first edge adjacent to a first side of the core region. The first edge includes a first region and a second region. The first region includes a plurality of second memory cells, and the second region includes a first pad portion through which at least one of an address signal, a command signal, a clock signal, a data signal and a control signal is inputted or outputted.

Abstract: An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.

Abstract: An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.

Abstract: In a semiconductor package, a circuit pattern is arranged in a circuit board and contact pads on the circuit board are connected with the circuit pattern. Contact terminals contact external contact elements on a first surface of the circuit board. An integrated circuit (IC) chip structure is mounted on the circuit board and electrically connected to the inner circuit pattern. An operation controller on the circuit board controls operation of the semiconductor package according to the package users' individual choice.

Abstract: With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.

Abstract: A method of programming a memory device including a one-time programmable (OTP) cell array configured to include at least one of a protected area and a programmable area are disclosed. The method includes receiving a fuse-program command to initiate a fuse-programming operation; checking whether the programmable area exists in the OTP cell array, terminating the fuse-programming operation when the OTP cell array does not include the programmable area, performing a fuse-programming operation on the programmable area when the OTP cell array includes the programmable area thereby programming fuses to create a fuse-programmed area; setting the fuse-programmed area of the OTP cell array as the protected area.

Abstract: Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells. In response to the activity metric satisfying a threshold, a bias signal is applied to the cells to reverse a resistance shift of the cells.

Abstract: A bit line, which is coupled to a resistive element of a memory cell is set to a first voltage level. The memory cell may be an MRAM cell or an RRAM cell. The resistive element is configured to have a first resistance in a first state of the memory cell and a second resistance in a second state of the memory cell. A source line, which is selectively coupled to the memory cell by an access transistor, is set to a second voltage level. A word line signal is asserted to apply a first bias voltage across the resistive element. The applied first bias voltage initiates a write operation at the memory cell. The word line signal is deasserted after a variable time duration based on a detection, during the write operation, of a current through the resistive element.

Abstract: A data storage device may generally be constructed and operated with at least one variable resistance memory cell having a first logic state threshold that is replaced with a second logic state threshold by a controller. The first and second logic states respectively corresponding to a predicted resistance shift that is based upon an operating temperature profile.

Abstract: A memory cell array comprises memory cells disposed at intersections of a plurality of first lines disposed in parallel and a plurality of second lines disposed intersecting the first lines. The memory cell includes a variable resistance element. A set operation-dedicated first driver circuit, when executing on the memory cell a set operation for switching a memory cell from a high-resistance state to a low-resistance state, supplies a voltage to the first lines. A reset operation-dedicated first driver circuit, when executing on the memory cell a reset operation for switching the memory cell from a low-resistance state to a high-resistance state, supplies a voltage to the first lines. A length of a wiring line between the set operation-dedicated first driver circuit and the memory cell array is longer compared to a length of a wiring line between the reset operation-dedicated first driver circuit and the memory cell array.

Abstract: A control circuit is configured to perform a state determination operation to sense voltages of a plurality of first wiring lines, the voltages changing based on current flowing from the first wiring lines to a plurality of second wiring lines via a plurality of variable resistive elements. Then, the control circuit is configured to adjust voltages to be applied to the first and second wiring lines in a reset operation or a set operation based on the voltages of the first wiring lines sensed in the state determination operation.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.

Abstract: This description is directed to a dynamic random access memory (DRAM) array having a plurality of rows and a plurality of columns. The array further includes a plurality of cells, each of which are associated with one of the columns and one of the rows. Each cell includes a capacitor that is selectively coupled to a bit line of its associate column so as to share charge with the bit line when the cell is selected. There is a segmented word line circuit for each row, which is controllable to cause selection of only a portion of the cells in the row.

Abstract: A dynamic random access memory (DRAM) device has a hierarchical bitline structure with local bitlines and global bitlines formed on different metal layers. The local bitlines are separated into a plurality of local bitline sections, and bitline isolation switches are configured to connect or disconnect the local bitline sections to or from the global bitlines. As a result, the local bitlines with higher per-length capacitance can be made shorter, since the global bitline with lower per-length capacitance is used to route the signal from the cell capacitances of the memory cells to the remote sense amplifiers.

Abstract: Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection circuit, a first write driver circuit, a second write driver circuit, and a boost circuit. Each of the columns may include a plurality of data storage cells. The write selection circuit may select a column of the plurality of columns. Each of the write driver circuits may configured to discharge a data line of a selected column into a common node. The boost circuit may be configured to initialize the common node to the first voltage level and couple the common node to a second voltage level, where the second voltage level is lower than the first voltage level.

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.

Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic demultiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.

Abstract: A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ there through for small time intervals thereby avoiding read disturbance to the MTJ.

Abstract: A writing method of a nonvolatile memory device is provided which receiving data, a target time, and a target resistance value; writing the data at a memory cell; calculating a resistance drift coefficient based on resistance values of the memory cell read on at least two times; calculating a resistance value of the memory cell on the target time using the resistance drift coefficient; and determining whether the resistance value calculated satisfies the target resistance value.

Abstract: A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of the semiconductor transistor structure while maintaining a second voltage difference between the gate and the channel region at less than the breakdown voltage.

Abstract: A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Abstract: A non-volatile memory device comprising a memory cell array including memory cells distributed among a plurality of sectors; a controller operable to program, read, and erase memory cells in said memory array, said controller further operable to generate and store EPLI values for programming a number of EPLI bits in one of said plurality of sectors with said stored EPLI values; and a comparator to compare said stored EPLI values with EPLI values programmed in said EPLI bits.

Abstract: A data erasing method of a solid state drive is provided. The solid state drive includes a memory module. The memory module includes a block. A data to be erased is stored in the block. The data erasing method includes steps of performing a first erasing operation to erase the block, programming the block after the first erasing operation, and performing a second erasing operation to erase the block.

Abstract: A memory system includes a nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device such that memory cells connected with a selected row of the nonvolatile memory device are programmed by one of a first program mode and a second program mode. At the first program mode, a plurality of logical pages corresponding in number to a maximum page number is stored at the memory cells, and at the second program mode, one or more logical pages the number of which is less than the maximum page number are stored at the memory cells using a bias condition that is different from that used in the first program mode.

Abstract: A data storage device receives a write data command and data. The data is stored in a buffer of the data storage device. The data storage device issues a command complete status indication. After the command complete status indication is issued, the data are stored in a primary memory of the data storage device. The primary memory comprises a first type of non-volatile memory and the buffer comprises a second type of non-volatile memory that is different from the first type of non-volatile memory.

Abstract: An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells.

Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described.

Abstract: Word lines extend in a first direction and are commonly connected to memory cells in a plurality of NAND cell units. Bit lines extend in a second direction crossing to the first direction and connected to one ends of the NAND cell units. In one block, both a first and a second NAND cell unit are connected to one of the bit lines. A bit-line-side select transistor in the first NAND cell unit and a source-line-side select transistor in the second NAND cell unit are disposed adjacently to each other. The source-line-side select transistor in the first NAND cell unit and the bit-line-side select transistor in the second NAND cell unit are disposed adjacently to each other.