Abstract: A diagnostic analyzer system includes a linear track, at least one pipetting device, and at least one diagnostic module. The linear track includes a pre-treatment lane disposed parallel to at least one processing lane. The linear track moves reaction vessels, containing samples, held by the pre-treatment lane and by the at least one processing lane. The pre-treatment lane pre-treats the samples in the reaction vessels of the pre-treatment lane. The pre-treatment lane is not connected to any diagnostic module for testing the samples in the reaction vessels of the pre-treatment lane. The at least one pipetting device transfers the pre-treated samples from the reaction vessels in the pre-treatment lane to the reaction vessels in the at least one processing lane. The at least one diagnostic module is connected to the at least one processing lane for testing the pre-treated samples transferred into the reaction vessels in the at least one processing lane.

Abstract: A microfluidic device and a control method, the microfluidic device including a platform including a chamber configured to accommodate a sample, a channel connected to the chamber, and a metering unit connected to the chamber by the channel and configured to meter an amount of the sample, wherein the metering unit includes a metering chamber configured to measure the amount of the sample, and an accommodation chamber connected to the metering chamber and configured to accommodate the sample to prevent the sample from overflowing out of the metering chamber.

Abstract: A reagent container pack for storing, preserving, and automatically unsealing and resealing a plurality of reagent containers in a reagent container pack on-board an automated clinical sample analyzer for analyzing analytes in a body fluid.

Abstract: Nanotube based lateral flow test device described herein is a lateral flow based diagnostic device, which uses arrays of fragments of single wall carbon nanotubes as sensor to detect the biomarkers at ultralow concentration (below picogram per milliliter). The device is consisted of the following components: (1). an lateral flow strip which typically is consisted of a backing film laminated with conjugate/sample pads, nitrocellulose membrane, wicking pad, (2). the arrays of single wall carbon nanotube conjugate with antibody which is immobilized on the membrane of the lateral flow device as the test line, (3). pairs of micro-electrode are installed on top part of the cassette, (4). a cassette which holds the lateral flow strip. The device can be used in clinical environments for biomarker detection.

Abstract: A method and apparatus for assaying to detect the presence or quantity of an analyte in a test sample, comprising: forming an unbounded aqueous mixture of a first test sample with a defined amount of a nanosphere probe which is conjugate of an analyte capturing member and a long emission fluorescent label, contacting a contacting zone of a test strip with the aqueous mixture, the test area having bound thereat a test binding moiety that for a competition assay binds any sample in competition with the analyte capturing member; or for a sandwich assay binds any sample analyte non-competitively with the analyte capturing member, the control area having bound a control binding moiety to nanosphere probe, selectively measuring long emission fluorescence at the test and control areas, and for a given test strip, determining a test zone value normalized with the total of test and control area signals.

Abstract: The invention relates to A method of making a polypeptide comprising at least one N?-methyl-lysine at a specific site in said polypeptide, said method comprising (a) genetically directing the incorporation of R—N?-methyl-lysine into said polypeptide, wherein R comprises an auxiliary group; and (b) catalysing the removal of R from the polypeptide of (a). In particular the invention relates to such a method wherein genetically directing the incorporation of R—N?-methyl-lysine into said polypeptide comprises arranging for the translation of a RNA encoding said polypeptide, wherein said RNA comprises an amber codon, and wherein said translation is carried out in the presence of an amber tRNA charged with R—N?-methyl-lysine.

Abstract: Methods for monitoring subject compliance with a prescribed treatment regimen are disclosed. In an embodiment, the method comprises measuring a drug level in fluid of a subject and normalizing the measured drug level as a function of one or more parameters associated with the subject. The drug level can be normalized using second order quantile regression. Embodiments of the methods can use both primary and secondary metabolites in the normalization; allow changing variance by dose; allow asymmetry in variance above and below the estimated median values; and/or use analytic variables with stable estimates, such as, for example, variables associated with the percentile for ?1 standard deviation, the percentile for 0 standard deviation, and the percentile for +1 standard deviation.

Abstract: The invention provides methods of preparation of lipoproteins from a biological sample, including HDL, LDL, Lp(a), IDL, and VLDL, for diagnostic purposes utilizing differential charged particle mobility analysis methods. Further provided are methods for analyzing the size distribution of lipoproteins by differential charged particle mobility, which lipoproteins are prepared by methods of the invention. Further provided are methods for assessing lipid-related health risk, cardiovascular condition, risk of cardiovascular disease, and responsiveness to a therapeutic intervention, which methods utilize lipoprotein size distributions determined by methods of the invention.

Abstract: The present invention provides methods for assaying binding of compounds to G-quadruplex structures. Also provided are methods for screening candidate compounds for use as modulators of G-quadruplex activity, and methods for screening candidate compounds for telomerase inhibitory activity. The invention further provides novel compounds useful in the assays of the invention.

Abstract: To provide a more convenient and more accurate method of assaying ProGRP by improving the stability of ProGRP which is known to be unstable in a biological sample. By using a blood sample in a condition in which a blood coagulation factor is not activated is used as a sample, the degradation of ProGRP is suppressed, whereby it is possible to store a sample for a long period of time and to improve the accuracy of an assay.

Abstract: The invention relates to a method and a sensor device (100) for the detection of magnetic particles (1) bound to the binding surface (111) of a sample chamber (112), wherein said detection is made during and/or immediately after the action of an attractive magnetic field. Preferably, the attractive magnetic field (B) is preceded by a repulsive magnetic field (B) which removes unbound magnetic particles away from the binding surface (111). Due to the attractive magnetic field (B), bound magnetic particles (1) come closer to the binding surface (111), which increases the signal of surface specific detection techniques like frustrated total internal reflection. A further enhancement of the signal can be achieved by an attractive magnetic field that is parallel to the binding surface (111), thus inducing the generation of chains between unbound and bound magnetic particles.

Abstract: The present invention discloses highly sensitive magnetic heterojunction device consisting of a composite comprising ferromagnetic (La0.66Sr0.34MnO3) LSMO layer with ultra-thin ferrimagnetic CoFe2O4 (CFO) layer capable of giant resistive switching (RS) which can be tuned at micro tesla magnetic field at room temperature.

Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.

Abstract: A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer.

Abstract: A method of fabricating a magnetoresistive element, the method comprising: forming a first plurality of layers without breaking a vacuum, the first plurality of layers sequentially comprising: a first nonmagnetic conductive layer; a first ferromagnetic layer comprising an amorphous structure and a first magnetization direction; a nonmagnetic tunnel barrier layer; a second ferromagnetic layer comprising an amorphous structure and a second magnetization direction, and a getter layer having a direct contact with the second ferromagnetic layer; annealing the first plurality of layers; removing the getter layer and a portion of the second ferromagnetic layer adjacent to the getter layer; forming above the second ferromagnetic layer a second plurality of layers such that interface between the second ferromagnetic layer and the second plurality of layers is formed without breaking a vacuum after removing the getter layer and the portion of the second ferromagnetic layer, the second plurality of layers sequentially c

Abstract: A warp correction apparatus includes an injection mechanism including a nozzle that performs injection treatment, an adsorption table that holds the substrate by adsorption at a principal surface side or a film surface side, a moving mechanism that moves the adsorption table so that the substrate relatively moves with respect to an injection area of an injection particle by the nozzle, an injection treatment chamber that houses the substrate held on the adsorption table and in the interior of which injection treatment is performed, a measurement mechanism that measures a warp of the substrate, and a control device that, based on a difference between a target warp amount and a warp amount measured by the measurement mechanism, performs at least either one of a setting processing of an injection treatment condition of the injection mechanism and an accept/reject determination of the substrate for which injection treatment has been performed.

Abstract: At the time of transporting a substrate into or from a space where a film formation process is performed, the space where the film formation process is performed, a space where a lower heater 16 is provided, and a space where an upper heater 19 is provided are made in an inert gas atmosphere.

Abstract: A deposition apparatus and a method for recycling a solution. The deposition apparatus includes a bath in which a solution used in a chemical bath deposition (CBD) method is filled, a tank in which the solution used in the CBD method is temporarily stored, and a filter unit for filtering the solution stored in the tank to be reused in the CBD method again. Thus, when a buffer layer is formed by the CBD method, the number of times of reusing the solution for forming the buffer layer may be increased.

Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Abstract: An IR sensing transistor according to an exemplary embodiment of the present invention includes: a light blocking layer formed on a substrate; a gate insulating layer formed on the light blocking layer; a semiconductor formed on the gate insulating layer; a pair of ohmic contact members formed on the semiconductor; a source electrode and a drain electrode formed on respective ones of the ohmic contact members; a passivation layer formed on the source electrode and the drain electrode; and a gate electrode formed on the passivation layer, wherein substantially all of the gate insulating layer lies on the light blocking layer.

Abstract: Disclosed is an organic light emitting diode (OLED) display comprising a substrate; an organic light emitting element disposed on the substrate; an encapsulation substrate disposed on the organic light emitting element; and an adhesive layer formed on the substrate, covering the organic light emitting element, and bonding the substrate on which the organic light emitting element is formed with the encapsulation substrate.

Abstract: Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device.

Abstract: Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device.

Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.

Abstract: A microelectromechanical systems (MEMS) device (58) includes a structural layer (78) having a top surface (86). The top surface (86) includes surface regions (92, 94) that are generally parallel to one another but are offset relative to one another such that a stress concentration location (90) is formed between them. Laterally propagating shallow surface cracks (44) have a tendency to form in the structural layer (78), especially near the joints (102) between the surface regions (92, 94). A method (50) entails fabricating (52) the MEMS device (58) and forming (54) trenches (56) in the top surface (86) of the structural layer (78) of the MEMS device (58). The trenches (56) act as a crack inhibition feature to largely prevent the formation of deep cracks in structural layer (78) which might otherwise result in MEMS device failure.

Abstract: The present disclosure provides a method of fabricating a micro-electro-mechanical systems (MEMS) device. In an embodiment, a method includes providing a substrate including a first sacrificial layer, forming a micro-electro-mechanical systems (MEMS) structure above the first sacrificial layer, and forming a release aperture at substantially a same level above the first sacrificial layer as the MEMS structure. The method further includes forming a second sacrificial layer above the MEMS structure and within the release aperture, and forming a first cap over the second sacrificial layer and the MEMS structure, wherein a leg of the first cap is disposed between the MEMS structure and the release aperture. The method further includes removing the first sacrificial layer, removing the second sacrificial layer through the release aperture, and plugging the release aperture. A MEMS device formed by such a method is also provided.

Abstract: A method for producing a thermoelectric module with a plurality of thermoelectric leg elements, which are electrically connected in series at opposite ends, includes arranging the leg elements on an electrically conducting plate, connecting the leg elements to the electrically conducting plate, and cutting up the electrically conducting plate into a plurality of conductor tracks, which respectively connect two of the leg elements to one another. From a further aspect, a pre-product for the production of a thermoelectric module by such a method includes an electrically conducting plate with a plurality of conductor track regions for the formation of conductor tracks. The electrically conducting plate has a lower mechanical stability in at least one zone of weakness between two conductor track regions than in the conductor track regions.

Abstract: The present invention generally provides a method for forming a photovoltaic device including evaporating a source material to form a large molecule processing gas and flowing the large molecule processing gas through a gas distribution showerhead and into a processing area of a processing chamber having a substrate therein. The method includes generating a small molecule processing gas, and reacting the small molecule processing gas with a film already deposited on a substrate surface to form a semiconductor film. Additionally, apparatuses that may use the methods are also provided to enable continuous inline CIGS type solar cell formation.

Abstract: A method for fabricating a thin film solar cell includes providing a soda lime glass substrate comprising a surface region, treating the surface region with one or more cleaning process including an aqueous solution to remove one or more contaminants and/or particulates, and forming a lower electrode layer overlying the surface region. The method also includes performing a thermal treatment process to remove any residual water species to substantially less than a monolayer of water species from the lower electrode layer and soda lime glass substrate. The thermal treatment process changes a temperature of the soda lime glass substrate from a first temperature to a second temperature to pre-heat the soda lime glass substrate. Additionally, the method includes transferring the soda lime glass substrate, which has been preheated, to a deposition chamber and forming a layer of photovoltaic material overlying the lower electrode layer within the deposition chamber.

Abstract: A stable and minute processing method of a thin film is provided. Further, a miniaturized semiconductor device is provided. A method for processing a thin film includes the following steps: forming a film to be processed over a formation surface; forming an organic coating film over the film to be processed; forming a resist film over the organic coating film; exposing the resist film to light_or_an electron beam; removing part of the resist film by development to expose part of the organic coating film; depositing an organic material layer on the top surface and a side surface of the resist film by plasma treatment; etching part of the organic coating film using the resist film and the organic material layer as masks to expose part of the film to be processed; and etching part of the film to be processed using the resist film and the organic material layer as masks.

Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Abstract: A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.

Abstract: A semiconductor device includes a semiconductor construct including a semiconductor substrate and an external connection electrode provided to protrude on a surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including a side surface of the semiconductor substrate.

Abstract: Provided are methods of forming a bump and a semiconductor device with the same. The method may include providing a substrate with pads, forming a bump maker layer to cover the pads and include a resin and solder particles, thermally treating the bump maker layer to aggregate the solder particles onto the pads, removing the resin to expose the aggregated solder particles, forming a resin layer to cover the aggregated solder particles, and reflowing the aggregated solder particles to form bumps on the pads.

Abstract: In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti.

Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.

Abstract: A semiconductor device includes: an n?-type base layer; a p-type base layer formed in a part of a front surface portion of the n?-type base layer; an n+-type source layer formed in a part of a front surface portion of the p-type base layer; a gate insulating film formed on the front surface of the p-type base layer between the n+-type source layer and the n?-type base layer; a gate electrode that faces the p-type base layer through the gate insulating film; a p-type column layer formed continuously from the p-type base layer in the n?-type base layer; a p+-type collector layer formed in a part of a rear surface portion of the n?-type base layer; a source electrode electrically connected to the n+-type source layer; and a drain electrode electrically connected to the n?-type base layer and to the p+-type collector layer.

Abstract: An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.

Abstract: A method for fabricating a semiconductor device is disclosed in the present invention. The abovementioned method comprises the following steps. Firstly, a gate is formed on a substrate. A gate insulating layer is then formed on the gate, and further an active layer is disposed on the gate insulating layer, wherein the active layer is composed of a microwave absorbing material. Source/drain is defined on the active layer to form the semiconductor device, and a microwave annealing process is finally performed thereon.

Abstract: There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n?-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n?-type impurity regions overlap with a gate electrode, and the other n?-type impurity regions do not overlap with the gate electrode. Since the two kinds of n?-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

Abstract: An aspect of the present embodiment, there is provided a method of manufacturing a semiconductor device, including adsorbing a photolytic group on a hydrophilic surface of a substrate on which a concave portion is provided, irradiating a first area of the substrate with light to transform the photolytic group to a hydrophobic group to modify a surface of the first area, selectively coating a resist on a second area which is a portion of the substrate other than the first area modified by hydrophobic group.

Abstract: Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) providing a substrate (100); b) forming a dummy gate stack on the substrate (100), wherein the dummy gate stack consists of a gate dielectric layer (203) and a dummy gate (201) located on the gate dielectric layer (203), and the material of the dummy gate (201) is amorphous Si; c) performing ion implantation to regions exposed on both sides of the dummy gate (201) on the substrate (100), so as to form source/drain regions (110); d) forming an interlayer dielectric layer (400) that covers the source/drain regions (110) and the dummy gate stack; e) removing part of the interlayer dielectric layer (400) to expose the dummy gate (201) and removing the dummy gate (201); and f) annealing to activate dopants in source/drain regions.

Abstract: A semiconductor chip includes a first mark for identifying a position of the chip within an exposure field. The semiconductor chip includes a first matrix in a first layer of the chip and a second mark within the first matrix identifying a position of the exposure field on a wafer.

Abstract: According to one embodiment, a first adhesive layer is formed on one major surface of a first substrate. The first substrate and a second substrate are adhered using a second adhesive layer that has thermosetting properties and covers the first adhesive layer, wherein a bonding strength between the second substrate is greater than a bonding strength between the second substrate and the first adhesive layer. The other major surface of the first substrate is polished, and the first substrate is thinned. A physical force is then applied to peripheral parts of the second adhesive layer, and a circular notched part is formed along the outer perimeter of the second adhesive layer to separate the first substrate and the second substrate at the interface between the first adhesive layer and the second adhesive layer.

Abstract: A method for manufacturing a semiconductor device is disclosed in which the probability of occurrence of a crack is reduced and in which manufacturing cost is also reduced. An exposure mask used in the method is disclosed. Protrusion portions are formed in intersections of scribe lines in an outermost periphery of a scribe line pattern of a surface protection film of the exposure mask, to thereby stick out toward an outer circumference. In this manner, the probability of occurrence of a crack occurring in a device formation section can be reduced so that a reduction in the manufacturing cost can be achieved.

Abstract: According to one embodiment, a method includes forming a first SiGe layer having a first profile of a concentration of Ge on a semiconductor substrate, forming a second SiGe layer having a second profile of a concentration of Ge on the first SiGe layer, the second profile lower than a first peak of the first profile, forming a mask layer on the second SiGe layer, etching the first and second SiGe layers by anisotropic etching using the mask layer as a mask to form trenches, selectively removing the first SiGe layer exposed into the trenches to form a cavity under the second SiGe layer, and oxidizing side and lower surfaces of the second SiGe layer exposed in the trenches and the cavity to increase the concentration of Ge in the second SiGe layer.

Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial structure including a first III-nitride epitaxial layer coupled to the first side of the III-nitride substrate and a plurality of III-nitride regions of a second conductivity type. The plurality of III-nitride regions have at least one III-nitride epitaxial region of the first conductivity type between each of the plurality of III-nitride regions. The semiconductor structure further includes a first metallic structure electrically coupled to one or more of the plurality of III-nitride regions and the at least one III-nitride epitaxial region. A Schottky contact is created between the first metallic structure and the at least one III-nitride epitaxial region.

Abstract: A first amorphous silicon layer is formed over a substrate and a second amorphous silicon layer is formed over the first amorphous silicon layer. When a laser annealing process is performed, the second amorphous silicon layer absorbs more laser light than the first amorphous silicon layer does. The first amorphous silicon layer crystallizes into a microcrystalline silicon layer and the second amorphous silicon layer crystallizes into a polysilicon layer. During the laser annealing process, light interference between the first amorphous silicon layer and an underlying buffer layer is eliminated owing to that the second amorphous silicon layer absorbs more laser light. The laser fringe is eliminated. The microcrystalline silicon layer with better crystalline uniformity can serve as an active layer for TFTs in the display area of an OLED display to improve its illumination uniformity.

Abstract: A manufacturing method of MIS (Metal Insulator Semiconductor)-type semiconductor device includes the steps of; forming a zirconium oxynitride (ZrON) layer; forming an electrode layer containing titanium nitride (TiN) on the zirconium oxynitride (ZrON) layer; and heating the electrode layer.