Patents Issued in November 27, 2014
  • Publication number: 20140346578
    Abstract: A solid-state image sensor including a pixel unit arranged on a semiconductor substrate and including a plurality of photoelectric converters, and a peripheral circuit unit arranged on the semiconductor substrate and including MOS transistors and a capacitive element portion, wherein a gate insulating film of the MOS transistor in the peripheral circuit unit and an insulating film between facing electrodes of the capacitive element portion are nitrided, and a density of nitrogen atoms in the nitrided insulating film of the capacitive element portion is higher than the density of the nitrogen atoms in the nitrided insulating film of the MOS transistor in the peripheral circuit unit.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 27, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Katsunori Hirota
  • Publication number: 20140346579
    Abstract: A magnetic field sensor device having a semiconductor body, whereby the semiconductor body has a top side and a bottom side, and whereby the semiconductor body has a substrate layer and a passivation layer formed above the substrate on the top side of the semiconductor body, and one or more integrated electronic components are formed in the substrate layer of the semiconductor body, and a Hall plate is provided on the top side of the semiconductor body above the passivation layer, and the Hall plate is formed of a graphene compound.
    Type: Application
    Filed: May 27, 2014
    Publication date: November 27, 2014
    Applicant: Micronas GmbH
    Inventor: Joerg FRANKE
  • Publication number: 20140346580
    Abstract: A semiconductor device includes a plurality of first signal lines crossing a plurality of second signal lines. At least one of the first signal lines has a first end to receive a first voltage and a second end to receive a second voltage. The first and second voltages are applied simultaneously to respective ones of the first and second ends. A difference between the first and second voltages causes joule heating in the at least one first signal line. The joule heating may correct one or more defects in the semiconductor device.
    Type: Application
    Filed: March 5, 2014
    Publication date: November 27, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sungsam LEE
  • Publication number: 20140346581
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a first electrode and a dummy electrode formed apart from each other over a semiconductor substrate, a second electrode formed between the first electrode and the dummy electrode, at the circumferential side surface of the first electrode, and at the circumferential side surface of the dummy electrode, and a capacitive insulation film formed between the first electrode and the second electrode. The first electrode, the second electrode, and the capacitive insulation film form a capacitive element. Further, the semiconductor device has a first plug penetrating through the interlayer insulation film, and electrically coupled with the first electrode, and a second plug penetrating through the interlayer insulation film, and electrically coupled with the portion of the second electrode formed at the side surface of the dummy electrode opposite to the first electrode side.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yasushi Ishii, Hiraku Chakihara
  • Publication number: 20140346582
    Abstract: The disclosed technology generally relates to memory devices, and more particularly to memory devices having an intergate dielectric stack comprising multiple high k dielectric materials. In one aspect, a planar non-volatile memory device comprises a hybrid floating gate structure separated from an inter-gate dielectric structure by a first interfacial layer which is designed to be electrically transparent so as not to affect the program saturation of the device. The inter-gate structure comprises a stack of three layers having a high-k/low-k/high-k configuration and the interfacial layer has a higher k-value than its adjacent high-k layer in the inter-gate dielectric structure. A method of making such a non-volatile memory device is also described.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 27, 2014
    Inventors: Judit (Gloria) Lisoni REYES, Laurent BREUIL, Pieter BLOMME, Jan VAN HOUDT
  • Publication number: 20140346583
    Abstract: A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines.
    Type: Application
    Filed: November 5, 2013
    Publication date: November 27, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Vinod R. Purayath, James Kai, Donovan Lee, Yuan Zhang, Akira Matsudaira
  • Publication number: 20140346584
    Abstract: An embodiment relates to a memory device that includes a semiconductor channel, a tunnel dielectric located over the semiconductor channel, a charge storage region located over the tunnel dielectric, a blocking dielectric located over the charge storage region, and a control gate located over the blocking dielectric. An interface between the blocking dielectric and the control gate substantially prevents oxygen diffusion from the blocking dielectric into the control gate.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 27, 2014
    Inventors: Vinod R. Purayath, James Kai, Donovan Lee, Akira Matsudaira, Yuan Zhang
  • Publication number: 20140346585
    Abstract: According to one embodiment, a semiconductor memory device includes a lower gate layer, a stacked body including a plurality of electrode layers and a plurality of insulating layers, alternately stacked on the lower gate layer, a channel body extending within the stacked body from the topmost electrode layer to the lower gate layer, and a memory film provided between the electrode layer and the channel body. The memory film includes a charge storage film. The electrode layer includes a step portion in which a step is formed in a stacking direction of the stacked body. The channel body and the memory film pass through the step portion.
    Type: Application
    Filed: September 5, 2013
    Publication date: November 27, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobuhito KUGE, Tsukasa NAKAI
  • Publication number: 20140346586
    Abstract: A non-volatile memory structure, including a substrate, a plurality of stacked structures, a plurality of first conductive type doped regions, at least one second conductive type doped region, a conductive layer, and a first dielectric layer, is provided. The stacked structures are disposed on the substrate, and each of the stacked structures includes a charge storage structure. The first conductive type doped regions are disposed in the substrate under the corresponding charge storage structures respectively. The second conductive type doped region is disposed in the substrate between the adjacent charge storage structures and has an overlap region with each of the charge storage structures. The conductive layer covers the second conductive type doped region. The first dielectric layer is disposed between the conductive layer and the second conductive type doped region.
    Type: Application
    Filed: August 13, 2014
    Publication date: November 27, 2014
    Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Wen-Jer Tsai
  • Publication number: 20140346587
    Abstract: A method includes forming a recess into a crystalline semiconductor substrate, the recess being disposed beneath and surrounding a channel region of a transistor; depositing a layer of crystalline dielectric material onto a surface of the substrate that is exposed within the recess; and depositing stressor material into the recess such that the layer of dielectric material is disposed between the stressor material and the surface of the substrate. A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20140346588
    Abstract: A method for manufacturing a semiconductor power device, comprising the steps of: forming a trench in a semiconductor body having a first type of conductivity; partially filling the trench with semiconductor material via epitaxial growth so as to obtain a first column having a second type of conductivity and having an internal cavity. The epitaxial growth includes simultaneously supplying a gas containing dopant ions of the second type of conductivity, hydrochloric acid HCl in gaseous form and dichlorosilane DCS in gaseous form, so that the ratio between the amount of HCl and the amount of DCS has a value of from 3.5 to 5.5.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 27, 2014
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Giuseppe MORALE, Carlo MAGRO, Domenico MURABITO, Tiziana CUSCANI
  • Publication number: 20140346589
    Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.
    Type: Application
    Filed: August 13, 2014
    Publication date: November 27, 2014
    Inventors: Hans Weber, Stefan Gamerith, Franz Hirler
  • Publication number: 20140346590
    Abstract: A semiconductor device formed in a semiconductor substrate includes a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region. The gate electrode is disposed adjacent at least two sides of the body region, and the source region and the gate electrode are coupled to a source terminal. A width of the body region between the two sides of the body region is selected so that the body region is configured to be fully depleted.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Inventors: Andreas Meiser, Till Schloesser, Franz Hirler
  • Publication number: 20140346591
    Abstract: A method for manufacturing a semiconductor device includes forming a device isolation film defining an active region, forming a recess configured to expose a seam contained in the device isolation film by etching the active region and the device isolation film, forming a sacrificial film to fill the exposed seam, and forming a gate at a lower part of the recess.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 27, 2014
    Inventor: Seong Wan RYU
  • Publication number: 20140346592
    Abstract: A vertical MOSFET includes: a semiconductor substrate comprising a drain layer, a drift layer, a body layer, and a source layer; and a trench gate penetrating through the source layer and the body layer from an upper surface of the semiconductor substrate and reaching the drift layer. The trench gate includes a gate electrode; a first insulating film disposed on a bottom surface of a trench formed in the semiconductor substrate; a second insulating film disposed at least on a side surface of the trench, and in contact with the body layer; and a third insulating film disposed between the gate electrode and the second insulating film, and formed of a material of which dielectric constant is higher than a dielectric constant of the second insulating film.
    Type: Application
    Filed: December 6, 2012
    Publication date: November 27, 2014
    Applicants: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Toshimasa Yamamoto, Yukihiko Watanabe
  • Publication number: 20140346593
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: FU-YUAN HSIEH
  • Publication number: 20140346594
    Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.
    Type: Application
    Filed: August 27, 2013
    Publication date: November 27, 2014
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Francois HEBERT
  • Publication number: 20140346595
    Abstract: A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Inventor: Hiroaki TAKETANI
  • Publication number: 20140346596
    Abstract: High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an array of poly islands and a control gate structure by patterning a poly layer formed over a deep well region and a body of a substrate. The method further includes forming a metal shield in contact with the control gate structure and over the array of poly islands.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Inventors: John J. Ellis-Monaghan, Theodore J. Letavic, Santosh Sharma, Yun Shi, Michael J. Zierak
  • Publication number: 20140346597
    Abstract: High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an insulator layer of varying depth over a drift region and a body of a substrate. The method further includes forming a control gate and a split gate region by patterning a layer of material on the insulator layer. The split gate region is formed on a first portion of the insulator layer and the control gate is formed on a second portion of the insulator layer, which is thinner than the first portion.
    Type: Application
    Filed: June 7, 2013
    Publication date: November 27, 2014
    Inventors: Natalie B. Feilchenfeld, Theodore J. Letavic, Richard A. Phelps, Santosh Sharma, Yun Shi, Michael J. Zierak
  • Publication number: 20140346598
    Abstract: In one embodiment, method of making a high voltage PMOS (HVPMOS) transistor, can include: (i) providing a P-type substrate; (ii) implanting N-type dopants in the P-type substrate; (iii) dispersing the implanted N-type dopants in the P-type substrate to form a deep N-type well; (iv) implanting P-type dopants of different doping concentrations in the deep N-type well along a horizontal direction of the deep N-type well; and (v) dispersing the implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along the horizontal direction of the deep N-type well.
    Type: Application
    Filed: May 14, 2014
    Publication date: November 27, 2014
    Applicant: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Chenggong Han
  • Publication number: 20140346599
    Abstract: FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Xiuyu Cai, Ruilong Xie, Songkram Srivathanakul
  • Publication number: 20140346600
    Abstract: A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate.
    Type: Application
    Filed: August 15, 2013
    Publication date: November 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20140346601
    Abstract: A semiconductor device includes a gate electrode, source regions and drain regions, a body contact region, and a body bias control electrode. The gate electrode includes a plurality of first portions arranged in parallel with a first distance therebetween, and a second portion connecting the plurality of first portions. The source regions and the drain regions are provided between the plurality of first portions. The body contact region is disposed on the other side of the source regions and the drain regions relative to the second portion. The body bias control electrode is provided on the body contact region in parallel with the second portion at a second distance from the second portion that is greater than the first distance, and is electrically connected to the body contact region.
    Type: Application
    Filed: February 10, 2014
    Publication date: November 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masayuki SUGIURA
  • Publication number: 20140346602
    Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.
    Type: Application
    Filed: August 13, 2014
    Publication date: November 27, 2014
    Inventors: Shigenobu Maeda, Hee-Soo Kang, Sang-Pil Sim, Soo-Hun Hong
  • Publication number: 20140346603
    Abstract: Transistor devices having an anti-fuse configuration and methods of forming the transistor devices are provided. An exemplary transistor device includes a semiconductor substrate including a first fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than a height of the first fin. The first fin extends through and protrudes beyond the first insulator layer to provide a buried fin portion and an exposed fin portion. A gate electrode structure overlies the exposed fin portion. A gate insulating structure is disposed between the first fin and the gate electrode structure. The gate insulating structure includes a first dielectric layer overlying a first surface of the first fin. The gate insulating structure further includes a second dielectric layer overlying a second surface of the first fin. A potential breakdown path is defined between the first fin and the gate electrode structure through the first dielectric layer.
    Type: Application
    Filed: May 21, 2013
    Publication date: November 27, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Quek
  • Publication number: 20140346604
    Abstract: A thin film transistor includes: a substrate, a semiconductor layer disposed on the substrate, a first gate electrode and a second gate electrode disposed on the semiconductor layer, a gate insulating layer disposed between the semiconductor layer and the first and second gate electrodes and having a first through hole between the first and second gate electrodes and a capping layer covering the first gate electrode and contacting the semiconductor layer via the first through hole. The capping layer includes a conductive material.
    Type: Application
    Filed: October 10, 2013
    Publication date: November 27, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: YUL-KYU LEE, KYU-SIK CHO, SUN PARK
  • Publication number: 20140346605
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, an integrated circuit includes a semiconductor substrate with a fin structure overlying the semiconductor substrate and having a source region, a drain region, and a channel region between the source region and drain region. The source region and the drain region each have a recessed surface. A source contact is adjacent the recessed surface in the source region and a drain contact is adjacent the recessed surface in the drain region. Linear current paths are defined from the channel region to the source contact and from the channel region to the drain contact.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Inventors: Peter Zeitzoff, Abhijeet Paul
  • Publication number: 20140346606
    Abstract: Gate-rounding fabrication techniques can be implemented to increase an effective channel length of a transistor and to consequently reduce the leakage current and static power consumption associated with the transistor. The transistor comprises a substrate region that includes a source region and a drain region. The transistor can also comprise a gate region that includes a main gate portion, one or more gate tips, and one or more corresponding gate-rounded portions. Each of the one or more gate tips is formed at a suitable position along the side of the main gate portion. During fabrication, the junction between the main gate region and each of the gate tips takes on a rounded shape to form a corresponding gate-rounded region. The gate-rounded regions increase the average length of the gate region and the effective channel length of the transistor.
    Type: Application
    Filed: December 14, 2011
    Publication date: November 27, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Yanfei Cai, Ji Li
  • Publication number: 20140346607
    Abstract: A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Guan-Lin Chen, Ting-Hung Hsu, Jiun-Jia Huang
  • Publication number: 20140346608
    Abstract: A method of fabricating a semiconductor device is provided. A plurality of first gate electrode structure is formed on a substrate. A recess is formed in the substrate, wherein the recess is formed between two adjacent first gate electrode structures of the plurality of first gate electrode structure. A diffusion prevention layer includes a first material and is formed on the recess of the substrate. A first pre-silicide layer includes a second material different from the first material and is formed on the diffusion prevention layer. A metal layer is formed on the first pre-silicide layer. The first pre-silicide layer and the metal layer are changed to a first silicide layer by performing an annealing process to the substrate. The diffusion prevention layer prevents metal atoms of the metal layer from diffusing to the substrate, and the first silicide layer comprises a monocrystalline layer.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jin-Bum Kim
  • Publication number: 20140346609
    Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.
    Type: Application
    Filed: December 8, 2013
    Publication date: November 27, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Shaofeng Yu, Russell Carlton McMullan, Wah Kit Loh
  • Publication number: 20140346610
    Abstract: A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film which is formed on a first active region of a semiconductor substrate and has a first high dielectric constant film, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film which is formed on a second active region of the semiconductor substrate and has a second high dielectric constant film, and a second gate electrode formed on the second gate insulating film. The second high dielectric constant film contains first adjusting metal. The first high dielectric constant film has a higher nitrogen concentration than the second high dielectric constant film, and does not contain the first adjusting metal.
    Type: Application
    Filed: August 6, 2014
    Publication date: November 27, 2014
    Inventors: Yoshihiro SATO, Takayuki YAMADA
  • Publication number: 20140346611
    Abstract: A semiconductor device may include a voltage supply unit suitable for supplying a voltage, a first conductive line coupled to the voltage supply unit, a second conductive line formed over the first conductive line, a voltage contact plug formed over the second conductive line, a voltage transmission line formed over the voltage contact plug, and a switching element suitable for switching the voltage transferred from the voltage transmission line.
    Type: Application
    Filed: October 24, 2013
    Publication date: November 27, 2014
    Applicant: SK hynix Inc.
    Inventor: Sung Lae OH
  • Publication number: 20140346612
    Abstract: A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20140346613
    Abstract: There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.
    Type: Application
    Filed: May 30, 2014
    Publication date: November 27, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller
  • Publication number: 20140346614
    Abstract: A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Inventors: Wei-Yuan LU, Li-Ping HUANG, Han-Ting TSAI, Wei-Ching WANG, Ming-Shuan LI, Hsueh-Jen YANG, Kuan-Chung CHEN
  • Publication number: 20140346615
    Abstract: A field effect transistor that has a source, a drain, a gate, a semiconductor region, and a dielectric region. The dielectric region is located between the semiconductor region and the gate. Negatively charged ions are located within the dielectric layer underneath the gate.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Applicant: Massachusetts Institute of Technology
    Inventors: Yuhao Zhang, Tomas Apostol Palacios
  • Publication number: 20140346616
    Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
  • Publication number: 20140346617
    Abstract: A semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including first and second trenches, a gate insulating film in the first and second trenches, a first conductivity type work function control film on the gate insulating film in the first trench, a second conductivity type work function control film on the gate insulating film in the second trench, a first gate metal on the first conductivity type work function control film, the first gate metal filling the first trench, a second gate metal on the gate insulating film in the second trench, and a carrier mobility improving film on the second conductivity type work function control film, the carrier mobility improving film filling the second trench.
    Type: Application
    Filed: March 28, 2014
    Publication date: November 27, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Pil KIM, Yun-Young YEOH
  • Publication number: 20140346618
    Abstract: Provided are active materials for electrochemical cells. The active materials include silicon containing structures and treatment layers covering at least some surface of these structures. The treatment layers may include aminosilane, a poly(amine), or a poly(imine). These layers are used to increase adhesion of the structures to polymer binders within active material layers of the electrode. As such, when the silicon containing structures change their size during cycling, the bonds between the binder and the silicon containing structure structures or, more specifically, the bonds between the binder and the treatment layer are retained and cycling characteristics of the electrochemical cells are preserved. Also provided are electrochemical cells fabricated with such active materials and methods of fabricating these active materials and electrochemical cells.
    Type: Application
    Filed: December 2, 2013
    Publication date: November 27, 2014
    Inventors: John Lahlouh, Klaus Joachim Dahl, Sarah Lynn Goertzen, Marie Kerlau
  • Publication number: 20140346619
    Abstract: An approach for detecting sudden changes in acceleration in a semiconductor device or semiconductor package containing the semiconductor device is disclosed. In one embodiment, a piezoelectric sensor is embedded in a semiconductor die. The piezoelectric sensor is configured to sense a mechanical force applied to the semiconductor die. An excessive force indicator is coupled to the piezoelectric sensor. The excessive force indicator is configured to generate an excessive force indication in response to the piezoelectric sensor sensing that the mechanical force applied to the semiconductor die has exceeded a predetermined threshold indicative of an excessive mechanical force.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Stephen P. Ayotte, Benjamin J. Pierce, Timothy M. Sullivan, Heather M. Truax
  • Publication number: 20140346620
    Abstract: A MEMS microphone has reduced parasitic capacitance. The microphone includes a trench electrically separating an acoustically active section of the backplate from an acoustically inactive section of the backplate.
    Type: Application
    Filed: November 14, 2011
    Publication date: November 27, 2014
    Inventors: Leif Steen Johansen, Jan Tue Ravnkilde, Pirmin Hermann Otto Rombach, Kurt Rasmussen
  • Publication number: 20140346621
    Abstract: A MEMS backplate enables MEMS microphones with reduced parasitic capacitance. A MEMS backplate includes a central area and a perforation in the central area. A suspension area surrounds the central area at least partially. An aperture is disposed in the suspension area.
    Type: Application
    Filed: November 14, 2011
    Publication date: November 27, 2014
    Applicant: EPCOS AG
    Inventors: Leif Steen Johansen, Jan Tue Ravnkilde, Pirmin Hermann Otto Rombach, Kurt Rasmussen, Dennis Mortensen
  • Publication number: 20140346622
    Abstract: A semiconductor wafer is formed with a first device layer having active devices. A handle wafer having a trap rich layer is bonded to a top surface of the semiconductor wafer. A second device layer having a MEMS device or acoustic filter device is formed on a bottom surface of the semiconductor wafer. The second device layer is formed either by monolithic fabrication processes or layer-transfer processes.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Inventor: Michael A. Stuber
  • Publication number: 20140346623
    Abstract: Techniques for covering open-cavity integrated-circuit packages in a batch process are disclosed. In an example method, a plurality of open-cavity packages are molded on a single batch leadframe or substrate, each open-cavity package comprising a floor and a plurality of walls arranged around the floor to form a cavity, each of said the walls having a bottom end adjoining said floor and having a top side opposite the bottom end. At least one semiconductor device is attached to the floor and within the cavity of each of the open-cavity packages, and a single flexible membrane is affixed to the top sides of the walls of the plurality of open-cavity packages, so as to substantially cover all of the cavities. The flexible membrane is then severed, between the packages.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Inventors: Klaus Elian, Helmut Wietschorke
  • Publication number: 20140346624
    Abstract: A semiconductor device includes: a first member including a selection transistor on a front surface side of a first substrate; and a second member including a resistance change device and a connection layer that comes in contact with the resistance change device, the connection layer being bonded to a back surface of the first member.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 27, 2014
    Applicant: Sony Corporation
    Inventors: Mitsuharu Shoji, Ichiro Fujiwara
  • Publication number: 20140346625
    Abstract: A layered ferromagnetic structure is composed of a first ferromagnetic layer positioned over a substrate; a second ferromagnetic layer positioned over the first ferromagnetic layer; and a first non-magnetic layer placed between the first and second ferromagnetic layers. The top surface of the first ferromagnetic layer is in contact with the first non-magnetic layer. The first ferromagnetic layer includes a first orientation control buffer that exhibits an effect of enhancing crystalline orientation of a film formed thereon.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Applicant: NEC CORPORATION
    Inventors: Yoshiyuki FUKUMOTO, Chuuji IGARASHI
  • Publication number: 20140346626
    Abstract: According to some aspects, a layered structure includes a memory layer, a magnetization-fixed layer, and a tunnel insulating layer. The memory layer has magnetization perpendicular to a film face in which a direction of the magnetization is configured to be changed according to information by applying a current in a lamination direction of the layered structure. The magnetization-fixed layer has magnetization parallel or antiparallel to the magnetization direction of the memory layer and comprises a laminated ferripinned structure including a plurality of ferromagnetic layers and one or more non-magnetic layers, and includes a layer comprising an antiferromagnetic material formed on a first ferromagnetic layer of the plurality of ferromagnetic layers and situated between the first ferromagnetic layer and the non-magnetic layer. The tunnel insulating layer is located between the memory layer and the magnetization-fixed layer.
    Type: Application
    Filed: August 11, 2014
    Publication date: November 27, 2014
    Applicant: Sony Corporation
    Inventors: Kazutaka Yamane, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Tetsuya Asayama, Hiroyuki Uchida
  • Publication number: 20140346627
    Abstract: An imaging device accommodating package includes an insulating base body and an imaging device connecting pad. The insulating base body includes a lower surface, a through-hole and a bonding area on the bottom surface of the recess. The lower surface includes a recess. The through-hole is formed in a bottom surface of the recess in a perspective plan view. The bonding area is used for an imaging device. The imaging device connecting pad is formed on an upper surface of the insulating base body or on an inner surface of the through-hole.
    Type: Application
    Filed: November 30, 2012
    Publication date: November 27, 2014
    Applicant: KYOCERA CORPORATION
    Inventors: Hiroshi Yamada, Akihiko Funahashi, Yousuke Moriyama