Abstract: The invention provides droplet actuators and droplet actuator techniques. Among other things, the droplet actuators and methods are useful for manipulating beads on a droplet actuator, such as conducting droplet operations using bead-containing droplets on a droplet actuator. For example, beads may be manipulated on a droplet actuator in the context of executing a sample preparation protocol and/or an assay protocol. An output of the methods of the invention may be beads prepared for execution of an assay protocol. Another output of the methods of the invention may be results of an assay protocol executed using beads.

Abstract: The crystal structure of the ligand binding domain of ERR-? in complex with a ligand that forms a reversible thioether bond to Cys325 of ERR-?, methods to measure dissociation rates for ligands that form reversible covalent bonds, and methods to design ligands that form reversible covalent bonds for use as modulators of ERR-? activity are disclosed. The crystal structure and methods provide a novel molecular mechanism for modulation of the activity of ERR-? and provide the basis for rational drug design to obtain potent specific ligands for use as modulators of the activity of this new drug target.

Abstract: Management of the health status of an animal colony using a plurality of blood collection cards and the analysis of dried blood from members of the colony that has been collected on the cards. Members of the colony may be removed from the colony as a result of the analysis.

Abstract: There is disclosed apparatus and a system for effecting testing on a sample, such as for medical testing. The apparatus includes a sample chip (30) provided with at least two chambers (48, 50) within which analyte and a sample to be tested can be located, one chamber being a mixing chamber (48) and the other a detection chamber (50), the latter being provided with a sensor or means to enable sensing of one or more parameters pertaining to the sample. A detector unit (70, 170) includes a slot (76) for holding a sample carrier (30), drive means (94) for moving parts of a sample from the mixing chamber (48) to the detection chamber (50), such as by electromagnetic force, sensing means (60) for sensing the one or more parameters, a diagnostic unit (84) for analyzing the sensed parameters and a display unit (72) for displaying the results of the test to a user. The test unit (70, 170) is preferably handheld, which the sample carrier (30) is preferably in the form of a disposable chip.

Abstract: The invention provides methods and compositions for the rapid and sensitive detection of post-translationally modified proteins, and particularly of those with posttranslational glycosylations. The methods can be used to detect O-GlcNAc posttranslational modifications on proteins on which such modifications were undetectable using other techniques. In one embodiment, the method exploits the ability of an engine˜red mutant of ?-1,4-galactosyltransferase to selectively transfer an unnatural ketone functionality onto O-GlcNAc glycosylated proteins. Once transferred, the ketone moiety serves as a versatile handle for the attachment of biotin, thereby enabling detection of the modified protein. The approach permits the rapid visualization of proteins that are at the limits of detection using traditional methods. Further, the preferred embodiments can be used for detection of certain disease states, such as cancer, Alzheimer's disease, neurodegeneration, cardiovascular disease, and diabetes.

Abstract: A fabrication method includes forming a spin-polarizing layer, a spin transport layer on the spin polarizing layer on a substrate, a free layer magnet on the spin transport layer, a non-magnetic layer on the spin polarizing layer, a reference layer on the non-magnetic layer, and a hard mask layer on the reference layer, etching the hard mask layer and forming a read portion including the reference layer, the nonmagnetic layer and the free layer magnet, forming a nonlinear resistor layer on surfaces of the spin transport layer, the spacers, and the hard mask layer, etching the nonlinear resistor layer, the spin transport layer, and the spin polarizing layer and forming a write portion including the spin transport layer and the spin polarizing layer, forming an interlevel dielectric layer, forming a trench, exposing an upper surface of the reference layer of the read and write portions.

Abstract: Provided are a CVD apparatus and a method of manufacturing a light emitting device using the same. The CVD apparatus includes a chamber body including a susceptor having at least one pocket part having a wafer stably mounted therein; a chamber cover provided with the chamber body to open or close the chamber body and having a reaction space between the susceptor and the chamber cover; a reactive gas supplier supplying the reactive gas into the reaction space to allow the reactive gas to flow across a surface of the susceptor; and a non-reactive gas supplier supplying a non-reactive gas into the reaction space to allow the non-reactive gas to flow across a surface of the chamber cover between the susceptor and the chamber cover so as to prevent the reactive gas from contacting the surface of the chamber cover.

Abstract: The present invention relates to a light-emitting diode (LED) and a method for manufacturing the same. The LED comprises an LED die, one or more metal pads, and a fluorescent layer. The characteristics of the present invention include that the metals pads are left exposed for the convenience of subsequent wiring and packaging processes. In addition, the LED provided by the present invention is a single light-mixing chip, which can be packaged directly without the need of coating fluorescent powders on the packaging glue. Because the fluorescent layer and the packaging glue are not processed simultaneously and are of different materials, the stress problem in the packaged LED can be reduced effectively.

Abstract: The present invention relates to light emitting diode (LED) packages and methods of manufacturing the same, and more particularly, to an LED package and a method of manufacturing the same that can reduce a variation of color coordinates of mass-produced LED packages.

Abstract: There is provided a method of manufacturing a light emitting device, the method including: mounting a plurality of light emitting devices on an adhesive layer; arranging upper surfaces of the plurality of light emitting devices to be disposed horizontally using a pressing member; forming a wavelength conversion part covering the plurality of light emitting devices on the adhesive layer by applying a resin including at least one phosphor material; planarizing an upper surface of the wavelength conversion part using the pressing member; and separating the adhesive layer from the plurality of light emitting devices.

Abstract: An edge-emitting etched-facet optical semiconductor structure has a substrate, an active multiple quantum well (MQW) region formed on the substrate, and a ridge waveguide formed over the MQW region extending in substantially a longitudinal direction between a waveguide first etched end facet and a waveguide second etched end facet. A mask layer used to form windows in which the etched end facets are disposed consists of a single dielectric material disposed directly on the ridge waveguide. An optical coating consisting of no more than one layer of the same dielectric material of which the second mask is made is disposed directly on the second mask and disposed directly on the windows to coat the etched end facets.

Abstract: To improve light extraction efficiency of light emitting elements such as electroluminescent elements. A first electrode 101, a light emitting layer 102, and a second electrode 103 are formed over a substrate 100, which partially constitute a light emitting element. Light produced in the light emitting layer 102 is emitted out through the second electrode 103. A plurality of three-dimensional bodies 104 are provided in contact with a surface of the second electrode 103. With the provision of the bodies 104, light totally reflected between the second electrode 103 and the air enters the bodies 104 and can be emitted through faces of the bodies 104 that are not parallel to the interface between the bodies and the second electrode 103.

Abstract: Systems, and methods for the design and fabrication of OLEDs, including large-area OLEDs with metal bus lines, are provided. For a given panel area dimension, target luminous emittance, OLED device structure and efficiency (as given by the JVL characteristics of an equivalent small area pixel), and electrical resistivity and thickness of the bus line material and electrode onto which the bus lines are disposed, a bus line pattern may be designed such that Fill Factor (FF), Luminance Uniformity (U) and Power Loss (PL) may be optimized. One general design objective may be to maximize FF, maximize U and minimize PL. Another approach may be, for example, to define minimum criteria for U and a maximum criteria for PL, and then to optimize the bus line layout to maximize FF. OLED panels including bus lines with different resistances (R1) along a length of the bus line are also described.

Abstract: A method for producing an OLED illuminating device includes steps of: (a) forming metal lines and power transmission lines on a substrate; (b) forming a patterned insulating layer to cover the metal lines and the power transmission lines; (c) forming a patterned first electrode layer on the insulating layer; (d) forming an organic light-emitting membrane structure on the first electrode layer; (e) forming a second electrode layer on the organic light-emitting membrane structure so that a plurality of luminescent pixels are formed; and (f) when one of the luminescent pixels is defective, cutting one of the power transmission lines that is connected to the defective one of the luminescent pixels using an energy beam.

Abstract: A method of fabricating a patterned substrate, with which the optical performance of a photovoltaic cell including an organic solar cell and an organic light-emitting diode (OLED) can be improved. The method includes generating electrostatic force on a surface of a substrate by treating the substrate with electrolytes, causing nano-particles to be adsorbed on the surface of the substrate, etching the surface of the substrate using the nano-particles as an etching mask, and removing the nano-particles residing on the surface of the substrate.

Abstract: A MEMS device (40) includes a base structure (42) and a microstructure (44) suspended above the structure (42). The base structure (42) includes an oxide layer (50) formed on a substrate (48), a structural layer (54) formed on the oxide layer (50), and an insulating layer (56) formed over the structural layer (54). A sacrificial layer (112) is formed overlying the base structure (42), and the microstructure (44) is formed in another structural layer (116) over the sacrificial layer (112). Methodology (90) entails removing the sacrificial layer (112) and a portion of the oxide layer (50) to release the microstructure (44) and to expose a top surface (52) of the substrate (48). Following removal, a width (86) of a gap (80) produced between the microstructure (44) and the top surface (52) is greater than a width (88) of a gap (84) produced between the microstructure (44) and the structural layer (54).

Abstract: A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level.

Abstract: In a method for manufacturing a solar cell where the solar cell includes a dopant layer having a first portion of a first resistance and a second portion of a second resistance lower than the first resistance, the method includes ion-implanting a dopant into the semiconductor substrate to form the dopant layer; firstly activating by heating the second portion and activating the dopant at the second portion; and secondly activating by heating the first portion and the second portion and activating the dopant at the first portion and the second portion.

Abstract: A method of manufacturing a solar cell includes the steps of: providing a substrate having a front side, a back side and a doped region; forming a conductor layer on the front side; firing the conductor layer at a temperature such that the conductor layer is formed with a first portion embedded into the doped region and a second portion other than the first portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the conductor layer so that the second portion of the conductor layer is disposed in the ARC layer; and removing the ARC layer on the conductor layer so that the conductor layer has an exposed surface exposed out of the ARC layer, wherein the exposed surface of the conductor layer is substantially flush with a first exposed surface of the ARC layer.

Abstract: Methods and devices are provided for high-efficiency solar cells. In one embodiment, an assembly is provided comprising of a plurality of solar cells each having at least one transparent conductor, a photovoltaic layer, at least one bottom electrode, a plurality of emitter wrap through (EWT) vias containing a conductive material, and a plurality of series interconnect vias containing a conductive material. The assembly may also include a backside support coupled to the solar cells, wherein the backside support is patterned to have electrically conductive areas and electrically nonconductive areas that create a series interconnect between solar cells electrically coupled by the support and prevents parallel connections between the solar cells. The cells may have a via insulating layer in each via separating the conductive material in each via from any side walls of the bottom electrode.

Abstract: A camera module includes an image sensor chip including a substrate having first and second opposite surfaces and a ground pad on the first surface, a housing surrounding the sides of the image sensor chip but which leaves the second surface of the image sensor chip exposed, an electromagnetic wave-shielding film united with the housing, and an electrical conductor electrically connected to the ground pad. The camera module also has an optical unit disposed on the first surface of the image sensor chip in the housing to guide light from an object to the image sensor chip. The electrical conductor extends through a side of the housing. The conductor also contacts the electromagnetic wave-shielding film to electrically connect the ground pad and the electromagnetic wave-shielding film.

Abstract: A method for producing a selective doping structure in a semiconductor substrate in order produce a photovoltaic solar cell. The method includes the following steps: A) applying a doping layer (2) to the emitter side of the semiconductor substrate, B) locally heating a melting region of the doping layer (2) and a melting region of the semiconductor substrate lying under the doping layer (2) in such a way that dopant diffuses from the doping layer (2) into the melted semiconductor substrate via liquid-liquid diffusion, so that a high doping region (3) is produced after the melt mixture solidifies, C) producing the planar low doping region by globally heating the semiconductor substrate, D) removing the doping layer (2) and E) removing or converting a layer of the semiconductor substrate on the doping side in such a way that part of the low doping region and of the high doping region close to the surface is removed or is converted into an electrically non-conducting layer.

Abstract: A method cleaving a semiconductor material that includes providing a germanium substrate having a germanium and tin alloy layer is present therein. A stressor layer is deposited on a surface of the germanium substrate. A stress from the stressor layer is applied to the germanium substrate, in which the stress cleaves the germanium substrate to provide a cleaved surface. The cleaved surface of the germanium substrate is then selective to the germanium and tin alloy layer of the germanium substrate. In another embodiment, the germanium and tin alloy layer may function as a fracture plane during a spalling method.

Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.

Abstract: A method of bonding by molecular bonding between at least one lower wafer and an upper wafer comprises positioning the upper wafer on the lower wafer. In accordance with the invention, a contact force is applied to a peripheral side of at least one of the two wafers in order to initiate a bonding wave between the two wafers.

Abstract: The solid-state imaging device in which pixel electrodes, a photoelectric conversion portion having an organic film generating electric charge in response to incident light, a transparent counter electrode, and a sealing layer are formed on a substrate is produced by the method including causing a metal mask to come into close contact with a substrate surface, on which the pixel electrodes are disposed, by magnetic force; forming the organic film by vapor-depositing an organic substance to the substrate surface on which the pixel electrodes are disposed; removing the metal mask after the organic film is formed; forming the counter electrode on the organic film; and forming the sealing layer covering the counter electrode, wherein the metal mask has undergone half etching to have a half etching portion and comes into close contact with the substrate surface such that a lower surface of the half etching portion faces the pixel electrodes.

Abstract: The present disclosure is directed to methods of forming different types of Cu2ZnSnS4 (CZTS) solar cells and Copper Indium Gallium DiSelenide (CIGS) solar cells that can be combinatorially varied and evaluated. These methodologies all incorporate the formation of site-isolated regions using a combinatorial processing tool and the use of these site-isolated regions to form the solar cell area. Therefore, multiple solar cells may be rapidly formed on a single substrate for use in combinatorial methodologies. Any of the individual processes of the methods described may be varied combinatorially to test varied process conditions or materials.

Abstract: A photovoltaic device includes a crystalline substrate having a first dopant conductivity, an interdigitated back contact and a front surface field structure. The front surface field structure includes a crystalline layer formed on the substrate and a noncrystalline layer formed on the crystalline layer. The crystalline layer and the noncrystalline layer are doped with dopants having a same dopant conductivity as the substrate. Methods are also disclosed.

Abstract: A method for the production of a wafer-based, back-contacted heterojunction solar cell includes providing at least one absorber wafer. Metallic contacts are deposited as at least one of point contacts and strip contacts in a predetermined distribution on a back side of the at least one absorber wafer. The contacts have steep flanks that are higher than a cumulative layer thickness of an emitter layer and an emitter contact layer and are sheathed with an insulating sheath. The emitter layer is deposited over an entire surface of the back side of the at least one absorber wafer. The emitter contact layer is deposited over an entire surface of the emitter layer so as to form an emitter contact system. At least one of the emitter layer and the emitter contact layer is selectively removed so as to expose the steep flanks of the contacts that are covered with the insulating sheath.

Abstract: A method for producing an organic radiation-emitting component is specified, which comprises, in particular, the following method steps: A) providing a first electrode layer (2) on a substrate (1), B) applying a structured electrically conductive layer (3) on the first electrode layer (2), wherein the electrically conductive layer (3) comprises a metal, C) producing an electrically insulating layer (4) comprising an oxide of the metal of the electrically conductive layer (3) on surfaces (31) of the electrically conductive layer (3) which are remote from the first electrode layer (2) by oxidation of the metal, D) applying at least one organic functional layer (5) on the first electrode layer (2) and the electrically insulating layer (4), and E) applying a second electrode layer (9) on the at least one organic functional layer (5). An organic radiation-emitting component is furthermore specified.

Abstract: The present invention relates to a method for producing an organic electroluminescence element, comprising an organic layer between an anode and a cathode of the organic electroluminescence element by a wet film-forming method by using a composition containing an organic electroluminescence element material and a solvent in any one environment of the following film formation environments 1 to 3, and drying the formed film: film formation environment 1: a carbon dioxide concentration of 0.7 g/m3 or less and an oxygen concentration of 18 to 22 vol %, film formation environment 2: a sulfur oxide concentration of 2.2 ?g/m3 or less and an oxygen concentration of 18 to 22 vol %, and film formation environment 3: a nitrogen oxide concentration of 3.1 ?g/m3 or less and an oxygen concentration of 18 to 22 vol %.

Abstract: There is provided an organic light emitting display device including a first substrate; an organic light emitting unit formed on the first substrate; a second substrate disposed on the organic light emitting unit; and an adhesive unit for adhering the first substrate and the second substrate to each other, wherein the adhesive unit includes a sealant, and particles that are arranged in the sealant so as to block penetration of external impurities. There is further provided a method of manufacturing the organic light emitting display device.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.

Abstract: The amount of water and hydrogen contained in an oxide semiconductor film is reduced, and oxygen is supplied sufficiently from a base film to the oxide semiconductor film in order to reduce oxygen deficiencies. A stacked base film is formed, a first heat treatment is performed, an oxide semiconductor film is formed over and in contact with the stacked base film, and a second heat treatment is performed. In the stacked base film, a first base film and a second base film are stacked in this order. The first base film is an insulating oxide film from which oxygen is released by heating. The second base film is an insulating metal oxide film. An oxygen diffusion coefficient of the second base film is smaller than that of the first base film.

Abstract: Disclosed herein is a method for manufacturing a metal-oxide thin film transistor. The method includes the steps of: (a1) forming a gate electrode on a substrate; (a2) forming a gate insulating layer over the gate electrode; (a3) forming a metal-oxide semiconductor layer having a channel region on the gate insulating layer; (a4) forming a source electrode and a drain electrode on the metal-oxide semiconductor layer, wherein the source electrode is spaced apart from the drain electrode by a gap exposing the channel region; (a5) forming a mobility-enhancing layer on the channel region, wherein the mobility-enhancing layer is not in contact with the source electrode and the drain electrode; and (a6) annealing the metal-oxide semiconductor layer and the mobility-enhancing layer in an environment at a temperature of about 200° C. to 350° C.

Abstract: A method of manufacturing a nonvolatile memory device includes: forming a tantalum oxide material layer including an oxygen-deficient transition metal oxide; forming a tantalum oxide material layer including a transition metal oxide and having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the tantalum oxide material layer; and exposing, after the forming of a tantalum oxide material layer, the tantalum oxide material layer to plasma generated from a noble gas.

Abstract: Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and electrically coupling a first end of laterally extending conductive elements to conductive terminals on or in a surface of the substrate. Second ends of the laterally extending conductive elements are structurally and electrically coupled to bond pads on or in an active surface of the first semiconductor die. Conductive structures are structurally and electrically coupled to bond pads of a second semiconductor die. At least some of the conductive structures are aligned with at least some of the bond pads of the first semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. At least some of the conductive structures are structurally and electrically coupled to at least some of the bond pads of the first semiconductor die.

Abstract: A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.

Abstract: Structures and methods for forming good electrical connections between an integrated circuit (IC) chip and a chip carrier of a flip chip package include forming one of: a tensile layer on a front side of the IC chip, which faces a tops surface of the chip carrier, and a compressive layer on the backside of the IC chip. Addition of one of: a tensile layer to the front side of the IC chip and a compressive layer the backside of the IC chip, may reduce or modulate warpage of the IC chip and enhance wetting of opposing solder surfaces of solder bumps on the IC chip and solder formed on flip chip (FC) attaches of a chip carrier during making of the flip chip package.

Abstract: Method for bonding of a plurality of chips onto a base wafer which contains chips on the front, the chips being stacked in at least one layer on the back of the base wafer and electrically conductive connections are established between the vertically adjacent chips, with the following steps: a) fixing of the front of the base wafer on a carrier, b) placing at least one layer of chips in defined positions on the back of the base wafer, and c) heat treatment of the chips on the base wafer fixed on the carrier, characterized in that prior to step c) at least partial separation of the chips of the base wafer into separated chip stack sections of the base after takes place.

Abstract: A method of assembling a packaging structure is provided and includes directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically interconnecting at least one of the respective sidewalls of the first and second chips to a common chip and orienting the respective active surfaces of the first and second chips transversely with respect to the common chip.

Abstract: A plurality of microelectronic assemblies (60) are made by severing an in-process unit including an upper substrate (40) and lower substrate (20) with microelectronic elements (36) disposed between the substrates. In a further embodiment, a lead frame (452) is joined to a substrate (440) so that the leads project from this substrate. Lead frame (452) is joined to a further substrate (470) with one or more microelectronic elements (436, 404, 406) disposed between the substrates.

Abstract: Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

Abstract: A method of making a semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive and a build-up circuitry is disclosed. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry includes a dielectric layer and conductive traces on the semiconductor device and the flange. The conductive traces provide signal routing for the semiconductor device.

Abstract: Provided are a double-sided adhesive tape, semiconductor packages, and methods of fabricating the packages. A method of fabricating semiconductor packages includes providing a double-sided adhesive tape on a top surface of a carrier, the double-sided adhesive tape including a first adhesive layer and a second adhesive layer stacked on the first adhesive layer, the first adhesive layer of the double-sided adhesive tape being in contact with the top surface of the carrier, adhering active surfaces of a plurality of semiconductor chips onto the second adhesive layer of the double-sided adhesive tape, separating the first adhesive layer from the second adhesive layer such that the second adhesive layer remains on the active surfaces of the semiconductor chips, patterning the second adhesive layer to form first openings that selectively expose the active surfaces of the semiconductor chips, and forming first conductive components on the second adhesive layer to fill the first openings.

Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.

Abstract: The present invention specifies a leadframe for electronic components and a corresponding manufacturing process, in which the bonding islands are formed by welding individual, prefabricated segments of a bonding-capable material onto a stamped leadframe.

Abstract: A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided.

Abstract: Various semiconductor chip package substrates with reinforcement and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is formed on the first side of the package substrate outside of the central area to resist bending of the package substrate.

Abstract: A method comprises fabricating an interconnect structure comprising a plurality of conductive interconnects encased in a dielectric structure and coupling each of the conductive interconnects to a corresponding bond pad of a package substrate and bond pad of a die. A device package comprises a substrate having a first plurality of bond pads disposed at a first surface of the substrate and a die having a first surface facing the first surface of the substrate and a second surface opposite the first surface, the die comprising a second plurality of bond pads disposed at the second surface. The device package further comprises an interconnect structure comprising a plurality of conductive interconnects encased in a dielectric structure, each of the conductive interconnects coupled to a corresponding bond pad of the first plurality of bond pads and to a corresponding bond pad of the second plurality of bond pads.