Abstract: An electrically, thermally, or electrically and thermally actuated device is disclosed herein. The device includes a substrate, a first electrode established on the substrate, an active region established on the electrode, and a second electrode established on the active region. A pattern is defined in at least one of the substrate, the first electrode, the second electrode, or the active region. At least one of grain boundaries are formed within, or surface asperities are formed on, at least one of the electrodes or the active region. The pattern controls the at least one of the grain boundaries or surface asperities.

Abstract: A semiconductor device includes: an n?-type base layer; a p-type base layer formed in a part of a front surface portion of the n?-type base layer; an n+-type source layer formed in a part of a front surface portion of the p-type base layer; a gate insulating film formed on the front surface of the p-type base layer between the n+-type source layer and the n?-type base layer; a gate electrode that faces the p-type base layer through the gate insulating film; a p-type column layer formed continuously from the p-type base layer in the n?-type base layer; a p+-type collector layer formed in a part of a rear surface portion of the n?-type base layer; a source electrode electrically connected to the n+-type source layer; and a drain electrode electrically connected to the n?-type base layer and to the p+-type collector layer.

Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.

Abstract: A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

Abstract: An integration flow for LDD and spacer fabrication on a sacrificial amorphous carbon gate structure, form first spacer by way of depositing on the si substrate which have gate structure first. Gate is provided above the N-well and P-well on substrate. Spin coating a layer of photoresist in the first spacer, patterning the photoresist, and the gate structure above the N-well or P-well is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the first spacer layer, form the second spacer layer by depositing on the surface of the si substrate and gate, and spin coating another photoresist layer on the second spacer layer. Pattern the another photoresist layer, and another side of the gate structure is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the second spacer layer, form the third spacer layer and SiN layer by depositing on the gate and the Si substrate in turn.

Abstract: It is an object to drive a semiconductor device at high speed or to improve the reliability of the semiconductor device. In a method for manufacturing the semiconductor device, in which a gate electrode is formed over a substrate with an insulating property, a gate insulating film is formed over the gate electrode, and an oxide semiconductor film is formed over the gate insulating film, the gate insulating film is formed by deposition treatment using high-density plasma. Accordingly, dangling bonds in the gate insulating film are reduced and the quality of the interface between the gate insulating film and the oxide semiconductor is improved.

Abstract: A Fin-FET fabrication approach and structure are provided using channel epitaxial regrowth flow (CRF). The method includes forming a Fin-FET structure including a Si line on a substrate, shallow trench isolation (STI) oxide on both sides of the Si line on the substrate, and a poly wall on top of and across the STI oxide and the Si line, wherein the Si line is higher than the STI oxide from the substrate. The method further includes thinning the STI oxide and the Si line while maintaining about the same height ratio of the Si line and the STI oxide, and forming a spacer wall adjacent to both sides of the poly wall and further adjacent to Si and STI oxide side walls under the poly wall uncovered due thinning the STI oxide and the Si line.

Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.

Abstract: An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and tungsten formed on the upper barrier layer.

Abstract: A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics.

Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.

Abstract: Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.

Abstract: A metal-oxide-semiconductor (MOS) device having a selectable threshold voltage determined by the composition of an etching solution contacting a metal layer. The MOS device can be either a p-type or n-type MOS and the threshold voltage is selectable for both types of MOS devices. The etching solution is either an oxygen-containing solution or a fluoride-containing solution. The threshold voltage is selected by adjusting the flow rate of inert gases into an etching chamber to control the concentration of oxygen gas or nitrogen trifluoride.

Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a multi-composition ILD layer by forming a first portion of an inter-layer dielectric (ILD) layer on a semiconductor substrate; and forming a second portion of an ILD layer on the first portion of the ILD layer. The second portion may have a greater silicon content than the first portion. For example, the second portion may be a silicon rich oxide.

Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.

Abstract: A structure including nFET and pFET devices is fabricated by depositing a germanium-containing layer on a crystalline silicon layer. The crystalline silicon layer is converted to silicon germanium in the pFET region to provide a thin silicon germanium channel for the pFET device fabricated thereon. Silicon trench isolation is provided subsequent to deposition of the germanium-containing layer. There is substantially no thickness variation in the silicon germanium layer across the pFET device width. Electrical degradation near the shallow trench isolation region bounding the pFET device is accordingly avoided. Shallow trench isolation may be provided prior to or after conversion of the silicon layer to silicon germanium in the pFET region. The germanium-containing layer is removed from the nFET region so that an nFET device can be formed on the crystalline silicon layer.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET.

Abstract: The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors.

Abstract: A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.

Abstract: A method of fabricating a semiconductor device may include patterning a substrate to form trenches, forming a sacrificial layer to cover inner surfaces of the trenches, the sacrificial layer having a single-layered structure, forming sacrificial patterns by isotropically etching the sacrificial layer such that the sacrificial layer remains on bottom surfaces of the trenches, forming lightly doped regions in sidewalls of the trenches using the sacrificial patterns as an ion mask, removing the sacrificial patterns, and sequentially forming a gate insulating layer and a gate electrode layer in the trenches.

Abstract: A trench having a side wall and a bottom portion is formed in a silicon carbide substrate. A trench insulating film is formed to cover the bottom portion and the side wall. A silicon film is formed to fill the trench with the trench insulating film being interposed therebetween. The silicon film is etched so as to leave a portion of the silicon film that is disposed on the bottom portion with the trench insulating film being interposed therebetween. The trench insulating film is removed from the side wall. By oxidizing the silicon film, a bottom insulating film is formed. A side wall insulating film is formed on the side wall.

Abstract: A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench.

Abstract: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.

Abstract: A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.

Abstract: A semiconductor device may include a first insulating layer disposed on a substrate, a gate electrode disposed on the first insulating layer, and a second insulating layer disposed on the gate electrode and the first insulating layer. The second insulating layer includes a first discharge site.

Abstract: Methods of fabricating non-planar transistors including current enhancing structures are provided. The methods may include forming first and second fin structures directly adjacent each other overlying a substrate including an isolation layer. The methods may further include forming a spacer on the isolation layer including first and second recesses exposing upper surfaces of the first and second fin structures respectively. The spacer may cover an upper surface of the isolation layer between the first and second recesses. The methods may also include forming first and second current enhancing structures contacting the first and second fin structures, respectively, in the first and second recesses.

Abstract: A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity.

Abstract: Embodiment of the present invention provides a method of forming a semiconductor device. The method includes providing a semiconductor substrate; epitaxially growing a silicon-carbon layer on top of the semiconductor substrate; amorphizing the silicon-carbon layer; covering the amorphized silicon-carbon layer with a stress liner; and subjecting the amorphized silicon-carbon layer to a solid phase epitaxy (SPE) process to form a highly substitutional silicon-carbon film. In one embodiment, the highly substitutional silicon-carbon film is formed to be embedded stressors in the source/drain regions of an nFET transistor, and provides tensile stress to a channel region of the nFET transistor for performance enhancement.

Abstract: A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate. Preferably, the semiconductor substrate includes at least a recess, the undoped first epitaxial layer has a lattice constant, a bottom thickness, and a side thickness, in which the lattice constant is different from a lattice constant of the semiconductor substrate and the bottom thickness is substantially larger than or equal to the side thickness.

Abstract: A method includes forming a gate stack to cover a middle portion of a semiconductor fin, and doping an exposed portion of the semiconductor fin with an n-type impurity to form an n-type doped region. At least a portion of the middle portion is protected by the gate stack from receiving the n-type impurity. The method further includes etching the n-type doped region using chlorine radicals to form a recess, and performing an epitaxy to re-grow a semiconductor region in the recess.

Abstract: An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer. An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

Abstract: A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening.

Abstract: A circuit configuration and methods for controlling parameters of a bipolar junction transistor (BJT) fabricated on a substrate. A bias voltage is electrically coupled to the substrate and can be adjusted to alter the working parameters of a target BJT.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials.

Abstract: A method of manufacturing a photo-semiconductor device that has a photoconductive semiconductor film provided with electrodes and formed on a second substrate, the semiconductor film being formed by epitaxial growth on a first semiconductor substrate different from the second substrate, the second substrate being also provided with electrodes, and the electrodes of the second substrate and the electrodes of the photoconductive semiconductor film being held in contact with each other.

Abstract: This invention relates to a supported polymer heterostructure and methods of manufacture. The heterostructure is suitable for use in a range of applications which require semiconductor devices, including photovoltaic devices and light-emitting diodes.

Abstract: A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed.

Abstract: An integrated circuit having a replacement gate MOS transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a MOS hard mask segment over a MOS sacrificial gate and a resistor hard mask segment over a resistor body. The resistor body is thinner than the MOS sacrificial gate. During the gate replacement process sequence, the MOS hard mask segment is removed, exposing the MOS sacrificial gate while at least a portion of the resistor hard mask segment remains over the resistor body. The MOS sacrificial gate is replaced by a replacement gate while the resistor body is not replaced.

Abstract: The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.

Abstract: A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region, forming a first trench having a first width in the first region and a second trench having a second width in the second region, and the second width is greater than the first width. The method also includes forming a first insulation layer in the first and second trenches, removing the first insulation layer in the second trench to form a first insulation pattern that includes the first insulation layer remaining in the first trench, forming on the substrate a second insulation layer that fills the second trench, and the second insulation layer includes a different material from the first insulation layer.

Abstract: A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1.

Abstract: A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film.

Abstract: Methods for forming semiconductor devices include providing a textured template, forming a buffer layer over the textured template, forming a substrate layer over the buffer layer, removing the textured template, thereby exposing a surface of the buffer layer, and forming a semiconductor layer over the exposed surface of the buffer layer.

Abstract: Methods and systems for dicing a semiconductor wafer including a plurality of integrated circuits (ICs) are described. In one embodiment, a method involves adhering an adhesive tape to a thin water soluble dry film. The method involves applying the thin water soluble dry film adhered to the adhesive tape over a surface of the semiconductor wafer. The method involves removing the adhesive tape from the thin water soluble dry film. The thin water soluble dry film is patterned with a laser scribing process, exposing regions of the semiconductor wafer between the ICs. The method involves etching the semiconductor wafer through gaps in the patterned thin water soluble dry film, and removing the thin water soluble dry film.

Abstract: An active device substrate includes a flexible substrate, an inorganic de-bonding layer, and at least one active device. The flexible substrate has a first surface and a second surface opposite to the first surface, wherein the first surface is a flat surface. The inorganic de-bonding layer covers the first surface of the flexible substrate, and the material of the inorganic de-bonding layer is metal, metal oxide or combination thereof. The active device is disposed on or above the second surface of the flexible substrate.

Abstract: In a wafer processing method, a modified layer is formed inside a wafer along planned dividing lines by irradiating the wafer with a laser beam with such a wavelength as to be transmitted through the wafer from the back surface side of the wafer along the dividing lines. A first modified layer is formed near the back surface of the wafer by irradiating the wafer with the light focal point of the laser beam positioned near the back surface of the wafer. The wafer is then irradiated with the light focal point of the laser beam positioned on the front surface side. Then plural second modified layers are formed in a multi-layering manner with sequential movement of the light focal point toward an area leading to the first modified layer. The wafer is divided into individual devices along the dividing lines by applying an external force to the wafer.

Abstract: An object of the present invention is to provide a production process of an epitaxial silicon carbide single crystal substrate having a high-quality silicon carbide single crystal thin film reduced in the surface defect and the like on a silicon carbide single crystal substrate with a small off-angle. According to the present invention, in the production process of an epitaxial silicon carbide single crystal substrate having a high-quality silicon carbide single crystal thin film reduced in the surface defect and the like on a silicon carbide single crystal substrate with an off-angle of 4° or less, pretreatment etching to a depth of 0.1 to 1 ?m is performed at a temperature of 1,550 to 1,650° C. by flowing a gas containing silicon and chlorine together with a hydrogen gas such that the silicon atom concentration becomes from 0.0001 to 0.01% based on hydrogen atoms in the hydrogen gas, and thereafter, an epitaxial layer is formed.