Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.

Abstract: Embodiments of methods for forming features in a silicon containing layer of a substrate disposed on a substrate support are provided herein. In some embodiments, a method for forming features in a silicon containing layer of a substrate disposed on a substrate support in a processing volume of a process chamber includes: exposing the substrate to a first plasma formed from a first process gas while providing a bias power to the substrate support, wherein the first process gas comprises one or more of a chlorine-containing gas or a bromine containing gas; and exposing the substrate to a second plasma formed from a second process gas while no bias power is provided to the substrate support, wherein the second process gas comprises one or more of an oxygen-containing gas or nitrogen gas, and wherein a source power provided to form the first plasma and the second plasma is continuously provided.

Abstract: In a wafer processing method, the back side of the wafer is ground to reduce the thickness of the wafer to a predetermined thickness. A modified layer is formed by applying a laser beam to the wafer from the back side of the wafer along each division line with the focal point of the laser beam set inside the wafer. The wafer is mounted on a reinforcing sheet having an insulating function on the back side of the wafer and a dicing tape is attached to the reinforcing sheet. The peripheral portion of the dicing tape is supported by an annular frame. The wafer is heated, which also heats the reinforcing sheet, thereby hardening the reinforcing sheet. An external force is applied to the wafer to divide the wafer into individual devices along each division line and to also break the reinforcing sheet along the individual devices.

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract: A method of growing a nitride semiconductor layer includes forming a plurality of nano-structures on a substrate, forming a first buffer layer on the substrate such that upper portions of each of the nano-structures are exposed, removing the nano-structures to form voids in the first buffer layer, and growing a nitride semiconductor layer on the first buffer layer including the voids.

Abstract: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1?xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1?yGey and a covering region comprising SiO2 and enclosing the center region.

Abstract: Embodiments of the present disclosure generally relate to doping and annealing substrates. The substrates may be doped during a hot implantation process, and subsequently annealed using a nanosecond annealing process. The combination of hot implantation and nanosecond annealing reduces lattice damage of the substrates and facilitates a higher dopant concentration near the surface of the substrate to facilitate increased electrical contact with the substrate. An optional capping layer may be placed over the substrate to reduce outgassing of dopants or to control dopant implant depth.

Abstract: A method for fabricating a semiconductor device is provided. An ion implantation mask exposing a portion of a semiconductor substrate is formed on the semiconductor substrate. The implantation mask includes a second hardmask layer having a first thickness and a second hardmask layer having a second thickness. The first hardmask layer is disposed between the second hardmask layer and the semiconductor substrate. An ion implantation process is performed on the exposed portion of the semiconductor substrate using the implantation mask. The implantation mask is removed without forming an etch mask layer on the exposed portion of the semiconductor substrate.

Abstract: A composition for forming an n-type diffusion layer includes a glass powder containing P2O5, SiO2 and CaO and a dispersion medium. An n-type diffusion layer and a photovoltaic cell element having an n-type diffusion layer are produced by applying the composition for forming an n-type diffusion layer on a semiconductor substrate and by subjecting the substrate to a thermal diffusion treatment.

Abstract: A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.

Abstract: A semiconductor device includes vertical channel layers, control gates and interlayer insulating layers stacked alternately with each other on the substrate and surrounding the vertical channel layers, floating gates interposed between the vertical channel layers and the control gates and separated from each other by the interlayer insulating layers, and charge blocking layers interposed between the floating gates and the control gates.

Abstract: A plating apparatus 20 includes a substrate holding device 110 configured to hold and rotate the substrate 2; a first discharge device 30 configured to discharge a plating liquid toward the substrate 2 held on the substrate holding device 110; and a top plate 21 that is provided above the substrate 2 and has an opening 22. The first discharge device 30 includes a first discharge unit 33 configured to discharge the plating liquid toward the substrate 2, and the first discharge unit 33 is configured to be moved between a discharge position where the plating liquid is discharged and a standby position where the plating liquid is not discharged. Further, the first discharge unit 33 is configured to be overlapped with the opening 22 of the top plate 21 at the discharge position.

Abstract: Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts.

Abstract: A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.

Abstract: A method for forming a through wafer via hole in a semiconductor device, wherein the semiconductor device comprises a wafer having a SiC substrate with a front side and a backside, a GaN-based layer formed on the front side of the SiC substrate, and a mask structure formed on the backside of the SiC substrate defining an etching area. The etching area is first descummed A through substrate via hole is formed by etching the etching area through the SiC substrate. The mask structure is removed and the inner surface of the through substrate via hole is cleaned. The inner surface of the through substrate via hole is then descummed A through wafer via hole is formed by etching through the GaN layer in the through substrate via hole. And lastly the inner surface of the through wafer via hole is cleaned.

Abstract: Systems, methods and apparatus for processing a substrate are disclosed. A reactor for processing a substrate includes a reaction chamber, a substrate support, a nozzle, and an outlet. The chamber is configured to process a single substrate on the substrate support. The nozzle extends along an axis of elongation along a side of the chamber. The nozzle includes a nozzle body forming an inner volume, an inlet providing fluid communication between a reactant source and the inner volume, and a plurality of holes spaced along the axis of elongation. The holes provide fluid communication between the inner volume of the nozzle body and the reaction chamber. The nozzle is configured such that fluid conductance through the holes increases with increasing distance from the inlet. The outlet is configured to allow flow from the nozzle through the reaction chamber to the outlet. The flow is parallel to a major surface of the substrate.

Abstract: Embodiments described herein generally relate to methods for forming gate structures. Various processes may be performed on a gate dielectric material to reduce the K value of the dielectric material. The gate dielectric having a reduced K value may provide for reduced parasitic capacitance and an overall reduced capacitance. The gate dielectric may be modified without thermodynamic constraint.

Abstract: A process for the manufacture of semiconductor devices is provided. The process comprises the chemical-mechanical polishing of a substrate or layer containing at least one III-V material in the presence of a chemical-mechanical polishing composition (Q1) comprising (A) inorganic particles, organic particles, or a mixture or composite thereof, (B) a polymer comprising at least one N-heterocycle, and (M) an aqueous medium and whereas Q1 has a pH of from 1.5 to 4.5.

Abstract: A method including forming a line pattern in a substrate includes using a plurality of longitudinally spaced projecting features formed along respective guide lines as a template in forming a plurality of directed self-assembled (DSA) lines that individually comprise at least one of (a): the spaced projecting features and DSA material longitudinally there-between, and (b): are laterally between and laterally spaced from immediately adjacent of the guide lines. Substrate material elevationally inward of and laterally between the DSA lines may be processed using the DSA lines as a mask.

Abstract: A semiconductor is fabricated on a silicon (Si) substrate. The semiconductor is III-nitride based. The Si substrate is partially isolated. Etching is directly processed from top on a chip for solving wire-width problem. The Si substrate does not need to be made thin. The chip can be large scaled and be prevented from bowing. Thus, the present invention simplifies producing procedure and reduces production cost. Besides, for a large-scaled chip, the breakdown voltage is enhanced; and, without making the Si substrate thin, the on-state current is remained the same and the heat problem is weakened.

Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.

Abstract: A bevel etcher for cleaning a bevel edge of a semiconductor substrate with plasma includes a lower electrode assembly having a lower support having a cylindrical top portion. An upper dielectric component is disposed above the lower electrode assembly having a cylindrical bottom portion opposing the top portion of the lower support. A tunable upper plasma exclusion zone (PEZ) ring surrounds the bottom portion of the dielectric component, wherein a lower surface of the tunable upper PEZ ring includes an upwardly tapered outer portion extending outwardly from the bottom portion of the upper dielectric component, wherein a vertical height of an adjustable gap between the lower surface of the upper PEZ ring and an upper surface of a substrate supported on the lower support can be increased or decreased such that the extent of the bevel edge of the substrate to be cleaned by the plasma can respectively be adjusted radially inward or radially outward.

Abstract: Provided is a plasma etching method capable of favorably forming masks used when etching a multilayer film. This plasma etching method for etching boron-doped amorphous carbon involves using a plasma of a gas mixture comprising a chlorine gas and an oxygen gas, and setting the temperature of a mounting stage (3) to 100° C. or greater.

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to the process of plasma etching an amorphous carbon layer. In one implementation, a method of etching a feature in an amorphous carbon layer is provided. The method comprises transferring a substrate including a patterned photoresist layer disposed above the amorphous carbon layer into an etching chamber, exposing the amorphous carbon layer to a fluorine-free etchant gas mixture including a fluorine-free halogen source gas and a passivation source gas and etching the amorphous carbon layer with a plasma of the fluorine-free etchant gas mixture. It has been found that plasma etching with a fluorine-free halogen based gas mixture reduces the formation of top critical dimension clogging oxides.

Abstract: In a dry etching method for isotropically etching each of SiGe layers selectively relative to each of Si layers in a laminated film composed of the Si layers and SiGe layers alternately and repeatedly laminated, the each of the SiGe layers is plasma-etched with pulse-modulated plasma using NF3 gas.

Abstract: An apparatus configured to remove metal etch byproducts from the surface of substrates and from the interior of a substrate processing chamber. A plasma is used in combination with a solid state light source, such as an LED, to desorb metal etch byproducts. The desorbed byproducts may then be removed from the chamber.

Abstract: A method includes passing a chemical solution through a metal-ion absorber, wherein metal ions in the metal-ion absorber are trapped by the metal-ion absorber. The chemical solution exiting out of the metal-ion absorber is then used to etch a metal-containing region, wherein the metal-containing region includes a metal that is of a same element type as the metal ions.

Abstract: Systems, methods and apparatus for processing a substrate are described. A reactor includes a reaction chamber, a composite nozzle, and a reaction chamber outlet. The composite nozzle extends along a side of the chamber and includes a first nozzle and a second nozzle separate from and parallel the first nozzle. Each nozzle includes a body extending along an axis of elongation, an inlet providing communication between at least one source of a common species and an inner volume of the body, and holes spaced along the axis. The holes provide fluid communication between the inner volume and the chamber. The outlet is configured to allow flow from the composite nozzle through the chamber to the outlet. The first nozzle inlet is positioned at a first end of the first body, and the second nozzle inlet is positioned at a second end of the second body. The second end is opposite the first end of the first body.

Abstract: Disclosed herein are methods of depositing layers of material on multiple semiconductor substrates at multiple processing stations within one or more reaction chambers. The methods may include dosing a first substrate with film precursor at a first processing station and dosing a second substrate with film precursor at a second processing station with precursor flowing from a common source, wherein the timing of said dosing is staggered such that the first substrate is dosed during a first dosing phase during which the second substrate is not substantially dosed, and the second substrate is dosed during a second dosing phase during which the first substrate is not substantially dosed. Also disclosed herein are apparatuses having a plurality of processing stations contained within one or more reaction chambers and a controller with machine-readable instructions for staggering the dosing of first and second substrates at first and second processing stations.

Abstract: In order to extend the cycle of gas cleaning for a film-forming device, a method for manufacturing a semiconductor device includes: a substrate carry-in process for carrying a substrate into a processing chamber; a film forming process for laminating at least two types of films on the substrate in the processing chamber; a substrate carry-out process for carrying the film laminated substrate out from the processing chamber; an etching process for supplying an etching gas into the processing chamber while the substrate is not in the processing chamber after the substrate carry-out process. The etching process includes a first cleaning process for supplying a fluorine-containing gas activated by plasma excitation into the processing chamber as an etching gas; and a second cleaning process for supplying a fluorine-containing gas activated by heat into the processing chamber as an etching gas.

Abstract: Provided is a method of forming a silicon nitride film on a surface to be processed of a target object, which includes: repeating a first process a first predetermined number of times, the process including supplying a silicon source gas containing silicon toward the surface to be processed and supplying a decomposition accelerating gas containing a material for accelerating decomposition of the silicon source gas toward the surface to be processed; performing a second process of supplying a nitriding gas containing nitrogen toward the surface to be processed a second predetermine number of times; and performing one cycle a third predetermined number of times, the one cycle being a sequence including the repetition of the first process and the performance of the second process to form the silicon nitride film on the surface to be processed.

Abstract: Described herein are methods for forming silicon nitride films. In one aspect, there is provided a method of forming a silicon nitride film comprising the steps of: providing a substrate in a reactor; introducing into the reactor an at least one organoaminosilane having a least one SiH3 group described herein wherein the at least one organoaminosilane reacts on at least a portion of the surface of the substrate to provide a chemisorbed layer; purging the reactor with a purge gas; introducing a plasma comprising nitrogen and an inert gas into the reactor to react with at least a portion of the chemisorbed layer and provide at least one reactive site wherein the plasma is generated at a power density ranging from about 0.01 to about 1.5 W/cm2.

Abstract: A connector reduced in height without reducing contact reliability. A contact of the connector includes a first spring portion that supports a contact portion, a second spring portion that supports a connection portion, and an integral connection portion that integrally connects the first spring portion and the second spring portion. The first spring portion and the second spring portion are arranged on an imaginary straight line that extends through the contact portion and is parallel to a connection direction, and the integral connection portion is made away from the imaginary straight line in a direction orthogonal to the connection direction.

Abstract: Apparatus for electrically connecting and grounding at least two mechanically interconnectable, planar mats in a reusable load-supporting surface includes at least one removable, electrically-conductive cover configured to be engaged with each mat and extend at least partially across the top and/or bottom face thereof. Each cover includes at least one conductive interface configured to electrically connect its associated mat with at least one other mat in the load-supporting surface.

Abstract: A system for connecting a shared DC bus between multiple power converters is disclosed. The DC bus includes a positive and a negative rail across which the DC voltage is present. A pair of DC bus stabs is mounted to a PCB within the power converter. Each DC bus stab is electrically connected to either the positive or negative rail. A connector assembly is mounted to the housing of the power converter such that a first receptacle engages a plug portion of the DC bus stab. The connector assembly also includes a second receptacle extending to the exterior of the power converter. The connector assembly is positioned on each power converter such that a known distance, or one of a number of known distances, is established between adjacent connector assemblies. A DC bus assembly extends between and is plugged into the second receptacle of the two adjacent connector assemblies.

Abstract: A safety device prevents the terminal of an electrical plug from being disengaged from or engaged with an electrical receptacle. When the terminal is engaged with the receptacle, a tubular lock-in member slides over the plug to obstruct the release of a plug securing means that secures the plug to the receptacle. A retainer member attaches to the lock-in member and engages the receptacle or a part attached to the receptacle to limit the movement of the lock-in member. When the terminal is disengaged from the receptacle, a lock-out member obstructs contact between the terminal and the receptacle and engages the plug securing means. The lock-in member obscures the plug securing means and is secured to the lock-in member by the retainer member and the keyed lockable means.

Abstract: A socket has a plug board with first plug-in openings for appropriate pins of a plug of a first standard and with second plug-in openings for appropriate pins of a plug of a second standard. Provided in a spacing to the plug board are a first type of contact mounts for receiving plug pins of the first standard, and a second type of contact mounts for receiving plug pins of the second standard. Provided between the contact mounts and the plug board are protection elements which are movable out of a closed position in which the first and second plug-in openings are blocked, into an open position in which the plug-in openings are open. The protection elements are pretensioned into their respective closed positions by spring elements. The first and second protection elements are pretensioned into their respective end positions in different directions of movement by the spring elements.

Abstract: A plug structure for connecting sockets comprises at least one jack formed at a side of a first socket; and a plug rod disposed on a second socket corresponding to the at least one jack and configured to plug in the at least one jack. The plug rod is electrically contacted with a spring piece in the jack so as to electrify the second socket. A slidable baffle plate is disposed on an inner side of the at least one jack and is configured to cover the jack. A through hole corresponding to the jack is formed in the baffle plate. A slope configured to push the baffle plate is disposed at a position on the baffle plate corresponding to the jack, and is disposed at an edge of the through hole and fitted with the plug rod to push the baffle plate to be inserted into the through hole. The plug structure for connecting sockets according to the present disclosure provides an improvement for a security protection of combined interfaces of the sockets, thus ensuring a security of the combined sockets.

Abstract: A multiple-in-one interface connector includes a shielding casing, an insulation body received in the shielding casing, a micro card receiving zone formed on a surface of the insulation body and a micro USB connection zone, a card ejection bar movably arranged at one side of the insulation body, and a card ejector rotatably mounted to the insulation body and operatively coupled to the card ejection bar. The insulation body includes a micro card receiving port and a micro USB connection port respectively in the micro card receiving zone and the micro USB connection zone. A micro card and a micro USB male connector can be respectively inserted to the micro card receiving zone and the micro USB connection port. To eject the micro card, the card ejection bar is pushed to move the card ejector so as to eject the micro card out of the micro card receiving zone.

Abstract: A connector includes a housing for insertion and ejection of a device, and an ejection mechanism. The ejection mechanism includes a rod member able to slide in the directions of device insertion and ejection. The rod member includes a main body portion extending in the directions of insertion and ejection, an operating piece connected to a protruding end of the main body portion protruding from the housing and extending in a direction intersecting the insert and ejection directions, and a reinforcing portion connected to the main body portion in front of the protruding end in the insertion direction and able to support the operating piece from the front in the insertion direction. The reinforcing portion includes a supporting end able to support the operating piece from the front in the insertion direction. The supporting end extends in a direction intersecting the length direction of the operating piece.

Abstract: An electrical connector assembly is provided. The assembly includes a terminal, a housing, and a seal. The seal is configured to create a moisture barrier between the housing and a mating connector. The seal defines a retainer portion that cooperates with the housing to retain the terminal to the housing.

Abstract: A connector joining structure includes an outer housing mounted on a casing, an inner housing having a terminal to be connected to a terminal of a mating connector mounted in the casing, and a first packing interposed between the outer housing and the inner housing. The first packing is configured to ensure sealing property between the outer housing and the inner housing even upon a position of the inner housing with respect to the outer housing being displaced in at least one of three directions in a three-dimensional space by a predetermined amount with respect to a target value.

Abstract: An electrical connector configured to retain an electrical terminal including a terminal lock nib that projects inward into a terminal cavity from a first cavity wall for retaining the electrical terminal in the connector body and a flexible cantilever beam that projects axially into the terminal cavity from a fixed end of the cantilever beam. The cantilever beam is located opposite the terminal lock nib and is configured to push the terminal against a second cavity wall and into retaining engagement with the terminal lock nib. The connector also includes a support ridge that projects into the terminal cavity and is configured to contact and restrict movement of a free end of the cantilever beam during insertion of the terminal into the terminal cavity. The terminal has a laterally spaced lock surface engageable with the lock nib and is configured to prevent withdrawal of the terminal from the cavity.

Abstract: A circuit board connecting device comprising a first connector which having a first fixing metallic member attached to a first housing, a second connector having a second fixing metallic member attached to a second housing, and holding means operative to prevent the second housing from being undesirably separated from the first housing under a condition in which the first and second housings are coupled with each other, wherein end portions of a resilient movable holding member provided on the first connector to be movable in a predetermined direction are supported respectively by the first fixing metallic member to engage respectively with portions of the second fixing metallic member for holding the second housing when the second housing is coupled with the first housing, so that the end portions of the resilient movable holding member and the portions of the second fixing metallic member constitute the holding means.

Abstract: A connection structure connects a plate-like terminal main body (11) on the ground terminal fitting (10) in surface contact with a grounding member (20) that has female screw holes (41, 42) and a receiving portion (23). A wire connecting portion (12) on the ground terminal fitting (10) is connected to a wire (60). A lock (13) on the terminal main body (11) engages the receiving portion (23) and is on an axis line extension (70) of the wire (60). Mounting holes (151, 152) formed on the terminal main body (11) and aligned with the female screw holes (41, 42) by locking the lock (13) to the receiving portion (23). The ground terminal fitting (10) is connected to the grounding member (20) by screwing bolts (51, 52) inserted through the mounting holes (151, 152) into the female screw holes (41, 42).

Abstract: A grounding member (20) is formed with a receiving hole (23), and a ground terminal fitting (10) is formed with a cantilevered lock (13) including a step (13B). The lock (13) is locked to the receiving hole (23) with the step (13B) contact with a stopper (24) of the receiving hole (23). In tightening a first bolt (51) at a first mounting hole (151) and a first female screw hole (51), a rotational force in a direction to bring the step (13B) into contact with the stopper (24) is applied to a terminal main body (11). Butting portions (14) protrude from side edges (13D) of the lock (13) and prevent following rotation of the terminal main body (11) by contacting receiving surfaces (25) when the first bolt (51) is tightened.

Abstract: A contact terminal having a main body case and a plunger pin received in an elongate hole formed in the main body case is provided. The plunger pin is a round bar provided with a step and includes a small diameter portion including the protrusion end portion and a large diameter portion that slides on a surface of the hole to freely move in a longitudinal direction thereof. A cut space is formed to extend from an end of the large diameter portion so as to leave at least a part of a side surface portion of the large diameter portion and the cut space receives an insulation ball including at least an insulation surface. A coil spring is arranged between the hole and the insulation ball to press the protrusion end portion of the plunger pin such that the protrusion end portion protrudes from the main body case.

Abstract: An electric connector includes a first housing including a guide shaft and a second housing including a guide hole into which the guide shaft is inserted, the guide shaft including a main body, and a projection radially projecting from the main body, the guide hole being formed at an inner surface thereof with a groove into which the projection is fit, the projection and the groove being formed such that a first imaginary line intersects with a second imaginary line, the first imaginary line being defined by extending a contact plane at which the projection and the groove make contact with each other when the first housing rotates relative to the second housing, towards a center of the main body, the second imaginary line being defined as a line bisecting a top surface of the projection and extending towards a center of the main body.

Abstract: A connector includes a cable tray configured to receive and retain a cable in a stable position and couple with a top cap configured to create an electrical connection with the cable as the top cap is manipulated in a predetermined manner while coupled with the cable tray. An upper surface of the cable tray is configured to receive the cable. The cable tray also includes a finger extending beyond the first end for some distance longitudinally. The finger includes a protrusion that protrudes to some extent in a transverse direction so that a cable-accommodating gap is defined between the protrusion and the first end. The protrusion is configured to bear against the cable and retain the cable in the stable position when the cable is inserted between the protrusion and the first end (before, during and/or after an electrical connection is established).

Abstract: A connector includes a cable tray configured to receive and retain a cable in a stable position and couple with a top cap configured to create an electrical connection with the cable as the top cap is manipulated in a predetermined manner while coupled with the cable tray. An upper surface of the cable tray is configured to receive the cable. The cable tray also includes a finger extending beyond the first end for some distance longitudinally. The finger includes a protrusion that protrudes to some extent in a transverse direction so that a cable-accommodating gap is defined between the protrusion and the first end. The protrusion is configured to bear against the cable and retain the cable in the stable position when the cable is inserted between the protrusion and the first end (before, during and/or after an electrical connection is established).