Abstract: An electronic device includes a number of n Hall effect regions with n>1, wherein the n Hall effect regions are isolated from each other. The electronic device also includes at least eight contacts in or on surfaces of the n Hall effect regions, wherein the contacts include: a first and a second contact of each Hall effect region. A first contact of the (k+1)-th Hall effect region is connected to the second contact of the k-th Hall effect region for k=1 to n?1, and the first contact of the first Hall effect region is connected to the second contact of the n-th Hall effect region. The at least eight contacts include at least two supply contacts and at least two sense contacts. Each Hall effect region includes at most one of the at least two supply contacts and at most one of the at least two sense contacts.

Abstract: Featured are methods for magnetic resonance imaging of a volume, such a volume having susceptibility-generating objects or interfaces having susceptibility mismatches therein. Such a method includes selectively visualizing one of susceptibility-generating objects or interfaces having susceptibility mismatches as hyperintense signals, where such visualizing includes controlling variable imaging parameters so as to control a geometric extent of a signal enhancing effect, m more particular aspects of the present invention, such selectively visualizing includes attenuating or essentially suppressing signals from fat and/or water, namely on-resonant water protons, so as to thereby enhance a signal(s) associated with magnetic susceptibility gradient(s). Also featured are MRI systems, apparatuses and/or applications programs for execution on a computer system controlling the MRI data acquisition process embodying such methods.

Abstract: The present embodiments relate to a standing wave trap for a magnetic resonance tomography device. The standing wave trap includes a conductor region extending in one plane and at least one capacitor that is conductively connected to two sections of the conductor region.

Abstract: The present invention is directed to an electrical wiring device that includes a test circuit that is configured to generate a recurring simulated fault signal. A detection circuit is configured to generate a test detection signal in response to the recurring simulated fault signal. An end-of-life monitor circuit is configured to generate an end-of-life detection signal if the test detection signal is not generated within a first predetermined period of time. At least one indicator is configured to emit an indication signal in response to the end-of-life detection signal. A response mechanism is configured to decouple the plurality of line terminals from the plurality of load terminals after a second predetermined period of time has elapsed following the end-of-life detection signal.

Abstract: In one embodiment, a method of evaluating electric joints includes: partially separating a terminal portion from a busbar portion of a joint formed between a battery cell terminal and an interconnector busbar; and measuring electric resistance between the terminal portion and the busbar portion. In another embodiment, the step of measuring includes connecting the terminal portion of the joint to a first clip of a first polarity and connecting the busbar portion of the joint to a second clip of an opposing polarity.

Abstract: A battery monitoring apparatus for monitoring a battery condition of an assembled battery. In the apparatus, a control unit transmits, to a monitoring unit that is powered by the assembled battery and monitors its battery condition, a first mode-switching instruction signal for instructing the monitoring unit to transition from a normal mode to a dark-current mode. Subsequently, the control unit transmits to the monitoring unit a second mode-switching signal for instructing the monitoring unit to transition from the dark-current mode to the normal mode, and acquires an increased count value of a timer circuit in the monitoring unit for a time period from transmission of the first mode-switching instruction signal to transmission of the second mode-switching instruction signal. When it is determined that the increased count value is greater than an abnormality diagnosis criterion value, then the control unit determines that the dark-current mode of the monitoring unit is malfunctioning.

Abstract: A system for making high voltage measurements to measure a voltage of a battery pack and detect of an isolation fault. The system includes a first resistive divider comprising at least a first resistive element and a second resistive element. The system also includes a second resistive divider comprising the second resistive element and a third resistive element. The system also includes a plurality of switches comprising a first switch and a second switch coupled between the second resistive element and the battery pack. The system further includes a controller configured to control the plurality of switches to operate in first mode to measure the voltage of the battery pack based on a voltage produced by the first resistive divider, and to control the plurality of switches to operate in at least a second mode to detect an isolation fault based on a voltage produced by the second resistive divider.

Abstract: A battery condition estimating apparatus for a battery pack having a plurality of battery cells connected in series includes an analog channel switching circuit and a battery gas gauge circuit. The analog channel switching circuit has a plurality of input ports and an output port, wherein the input ports are coupled to the battery cells via a plurality of analog channels, respectively, and the analog channel switching circuit is arranged to couple the output port to a selected input port of the input ports for allowing the output port N5 to be coupled to a selected battery via a selected analog channel. The battery gas gauge circuit is coupled to the output port of the analog channel switching circuit, and used for estimating a battery condition of the battery pack by monitoring the selected battery cell via the selected analog channel.

Abstract: A method is provided for current-based detection of an electrical fault in an electrical network of a motor vehicle, the network having at least: one battery, one pulse-controlled inverter, one d.c. voltage converter, and an intermediate circuit associated with the pulse-controlled inverter. The method includes: detecting magnitudes of each a battery current, a d.c. voltage converter current, and an intermediate circuit current; comparing current magnitudes according to provided equations; and checking based on the comparison of whether a specifiable deviation has been exceeded. An alternative method for voltage-based detection of an electrical fault in an electrical network of a motor vehicle includes: detecting magnitudes of each a battery voltage, a d.c. voltage converter voltage, and an intermediate circuit voltage; comparing voltage magnitudes according to provided equations; and checking based on the comparison of whether a specifiable deviation has been exceeded.

Abstract: A method of testing a short circuit protection system applied to a spur of an electric circuit. The short circuit protection system has a current limiting means which applies a current limit to the spur if the current thereon exceeds a trip level. The electric circuit has a power supply and an isolation means adapted to fully or partially isolate the power supply from the electric circuit if the current thereon exceeds a power supply trip level for longer than a deadband period. The method includes applying a test current demand to the short circuit protection system which has a current and duration sufficient for the spur current trip level but a current insufficient to exceed the power supply trip level and/or a duration insufficient to exceed the deadband period, and detecting if the current limiting means applies the current limit or not during the test current demand.

Abstract: A microwave apparatus comprises a microwave source for providing a microwave signal, connectable to a load; control means configured in operation to vary over a frequency range a frequency of the microwave signal provided by the source; a microwave detector for performing microwave measurements, arranged to receive reflections from and/or transmissions to the load in operation and to perform a plurality of measurements, each measurement corresponding to a respective one of a plurality of different frequencies of the frequency range; and means for determining from the plurality of measurements a measure of reflection and/or a measure of transmission.

Abstract: Present techniques provide an inductive proximity sensor having a multi-receiver coil assembly and an evaluator circuit configured to receive a differential signal from the multi-receiver coil assembly to determine the presence of a target. The multi-receiver coil assembly includes two receiver coils in a differential coil arrangement and a transmitter coil configured to emit an electromagnetic field and induce a voltage on each of the receiver coils. The voltage difference between the two receiver coils is transmitted as a differential signal to the evaluator circuit. Targets which approach the inductive proximity sensor disrupt the electromagnetic field and change the induced voltages on each of the receiver coils, thereby changing the differential signal. The evaluator circuit processes the differential signal to determine whether the changes indicate that a target is present.

Abstract: There is provided a capacitor sensor capable of controlling sensitivity, wherein the capacitor sensor measures the magnitude and direction of a shear force applied to the sensor, as well as the magnitude of a normal force applied on the surface of the sensor, and consists of a single cell including a pattern electrode capable of varying its shape to control the sensitivity of the sensor.

Abstract: Provided are a method of measuring a degree of degradation of a lubricating oil and a measuring device therefor, in which (a) acidity is measured through use of an ISFET of hydrogen ion sensitive type and (b) dielectric constants or electrostatic capacitances at two or more different frequencies are obtained, to thereby determine a degradation state of the lubricating oil based on the acidity and a plurality of values of the dielectric constants or the electrostatic capacitances. Accordingly, the degree of degradation of the lubricating oil can be measured easily and precisely and a degradation mechanism of the lubricating oil can be predicted.

Abstract: A circuit and a method for sensing differential capacitance involve using plural storing capacitors to repeatedly sample charges of the differential capacitance in an over-sampling manner, and storing the charges sampled in different transfer rounds into different storing capacitors instead of repeatedly transferring charges for a single storing capacitor, so as to collect charge averages about both inputs and noises and in turn effectively reduce RF interference and source noises.

Abstract: The contactless conductivity detector in one embodiment includes a microfluidic chip having a channel (102) thereon and four detection electrodes: first and second emitting electrodes (100a, 101a), and first and second receiving electrodes (100b, 101b). The channel (102) is defined by channel walls. The first emitting electrode (100a) and the first receiving electrode (100b) are adjacent a first channel wall, and the second emitting electrode (101a) and the second receiving electrode (101b) are adjacent a second channel wall, the second channel wall being opposite the first channel wall.

Abstract: The invention relates to a method for measuring the electrical resistance of a glow plug, wherein a test current is set by closed-loop control to a constant value using a constant-current source, and is directed through the plug. A value of the electrical resistance of the glow plug is determined by evaluating a feedback signal of the constant-current source.

Abstract: A flexible current and voltage sensor provides ease of installation of a current sensor, and optionally a voltage sensor in application such as AC branch circuit wire measurements, which may require installation in dense wiring conditions and/or in live panels where insulating gloves must be worn. The sensor includes at least one flexible ferromagnetic strip that is affixed to a current sensing device at a first end. The second end is secured to the other side of the current sensing device or to another flexible ferromagnetic strip extending from the other side of the current sensing device to form a loop providing a closed pathway for magnetic flux. A voltage sensor may be provided by metal foil affixed to the inside of the flexible ferromagnetic strip. A clamp body, which can be a spring loaded handle operated clamp or a locking fastener, can secure the ferromagnetic strip around the wire.

Abstract: A pixel array module with a self-test function including a test circuit unit, a plurality of test lines, and a pixel array is provided. The test circuit unit provides the self-test function. The test lines are connected between the test circuit unit and the pixel array. The pixel array is connected to the test circuit unit through the test lines and includes a plurality of pixels. Each pixel includes a transistor. Each transistor has a first terminal and a second terminal. Regarding each of the pixels, a driving signal of the transistor is transmitted from the first terminal to the second terminal thereof under a normal mode, and a test signal of the transistor is transmitted from the second terminal to the first terminal thereof under a test mode. Furthermore, a self-test method of the foregoing pixel array module is also provided.

Abstract: An IDDQ test system and method that, in one embodiment, includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQm) at a measured temperature (Tm) for a specific semiconductor device embodying the given semiconductor device design, the measured temperature (Tm) obtained within 5 seconds of obtaining the measured IDDQ value (IDDQm), and 3) a scaling subsystem operable to scale the measured IDDQ value (IDDQm) at the measured temperature (Tm) to a compensated IDDQ value (IDDQc) at a desired temperature (Td) using the IDDQ versus temperature model.

Abstract: An integrated circuit (IC) device tester maintains a set point temperature on an IC device under test (DUT) having a die attached to a substrate. The tester includes a thermal control unit and a fluid management system configured to supply the thermal control unit with fluids for pneumatic actuation, cooling, and condensation abating. The tester can includes a box enclosing the thermal control unit thereby providing a substantially isolated dry environment during low humidity testing of the DUT. The heat exchange plate may include an inner structure for thermal conductivity enhancement.

Abstract: A jig for use in a semiconductor test of the present invention includes; a base on which a probe pin and an insulating material are provided such that the probe pin is surrounded by the insulating material in plan view; and a stage arranged to face a surface of the base on which the probe pin and the insulating material are provided. The stage is capable of receiving a test object placed on a surface facing the base. When the test object is placed on the stage and the base and the stage move in a direction in which they get closer to each other, the probe pin comes into contact with an electrode formed on the test object, and the insulating material comes into contact with both the test object and the stage.

Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board including a rocker base protrusion, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.

Abstract: A planar body is configured such that its edges engage the sidewall of a via of a device under test to create point electrical contacts and the planar body resists removal of the planar body from the via after insertion. The edges of the planar body may include barbs that create point electrical contacts and resist removal of the planar body from the via after insertion. The end of the body that is inserted into the via may form a tapered tip to facilitate insertion. The end of the planar body that is inserted into the via may include barbs that resist removal of the planar body from the via after insertion. The edges of the planar body may include stops that prevent further insertion of the planar body into the via beyond the stops.

Abstract: A support structure for installation of a component assembly housed in a rotating, translating carriage chassis, the support structure including: a stationary rail that includes a shaft extruding perpendicular to the stationary rail; a rotating rail adapted to receive a carriage chassis rail, the rotating rail parallel to the stationary rail when the rotating rail is in a non-rotated position, the rotating rail including a shaft receptacle that receives the shaft, the rotating rail configured to rotate about the shaft and relative to the stationary rail; and a translation mechanism attached to the rotating rail, the translation mechanism enabling the carriage chassis rail to translate parallel to and along the rotating rail.

Abstract: A semiconductor package testing apparatus and testing a semiconductor package, the apparatus including a test circuit substrate that electrically tests a semiconductor package having connection terminals; a socket electrically connecting the test circuit substrate with the semiconductor package; a socket guide having an open region delimiting the socket; an insert that fixes the semiconductor package and positions the semiconductor package in the open region of the socket guide; a pusher that presses the semiconductor package to make contact between the socket and the semiconductor package; and an alignment part that aligns the semiconductor package with the open region, wherein the alignment part is configured to selectively apply a magnetic force to align keys of the semiconductor package, the align keys being formed of a magnetic material.

Abstract: The present invention discloses a voltage applying device for an LCD substrate, and the voltage applying device includes a base, a probe bar, and probe pins. The base includes a first slide rail. The probe bar is movably disposed on the first slide rail of the base, and the probe bar includes a second slide rail. The probe pins are movably disposed on the second slide rail of the probe bar, and the probe pins are utilized to contact a plurality of contact pads of the LCD substrate, so as to apply voltage on the LCD substrate. The voltage applying device of the present invention can overcome a problem of increased costs for a conventional voltage applying device can not be shared.

Abstract: A fault detection circuit is utilized to automatically detect faults in hold-up power storage devices. The fault detection circuit includes a hold-up monitoring circuit and a memory device. The hold-up monitoring circuit is connected to monitor output of the hold-up power storage device, wherein the hold-up monitoring circuit measures a duration of time that the hold-up power storage device provides sufficient power following a loss of normal power and detects faults based on the measured duration of time. The memory device is connected to store the duration of time measured by the hold-up power storage device following a loss of normal power.

Abstract: Preservation of quantum entanglement in a two-qubit system is achieved by use of the disclosed systems. Three different example two-qubit systems are shown: (1) a system employing a weak measurement, (2) a system in which a generalized amplitude dampening occurs without use of a weak measurement, and (3) an extended system in which the system is prepared in a more robust state less susceptible to decoherence prior to a generalized amplitude dampening.

Abstract: An integrated circuit design protecting device includes a switch device and a non-volatile memory. The switch device includes M input ports, N output ports, N multiplexers, and S selection nodes. Each multiplexer of the N multiplexers includes I input nodes, an output node, and at least one selection node. The I input nodes are coupled to I input ports of the M input ports. The output node is coupled to an output port of the N output ports. The non-volatile memory is coupled to the S selection nodes of the switch device for providing selection codes to the switch device.

Abstract: A programming element including a first transistor, a second transistor, and a capacitor between a logic circuit using a semiconductor element and a power supply is provided. In the programming element, a node where a drain electrode of the first transistor, a gate electrode of the second transistor, and one of electrodes of the capacitor are electrically connected to each other is formed. A potential can be supplied to each of a source electrode of the first transistor and the other of the electrodes of the capacitor. The power supply and the logic circuit are electrically connected to each other through a source electrode and a drain electrode of the second transistor. A connection state between the power supply and the logic circuit is controlled in accordance with the state of the second transistor.

Abstract: In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract: To provide a charge pump circuit to manufacture a low-power-consumption PLD. A semiconductor device includes a first circuit and a second circuit electrically connected to the first circuit. A charge pump circuit formed of a transistor including an oxide semiconductor and a boosting control circuit controlling the charge pump circuit are provided between the first circuit and the second circuit. The first circuit and the charge pump circuit operate at first power supply voltage, and the boosting control circuit and the second circuit operate at second power supply voltage. The first power supply voltage is lower than the second power supply voltage.

Abstract: A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.

Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.

Abstract: An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library.

Abstract: An apparatus relating generally to voltage conversion includes an amplifier coupled to receive an input voltage and a reference voltage. First and second converters are coupled to the amplifier to receive a bias voltage. The first converter includes a first transconductor coupled to receive the bias voltage to adjust a first tail current, and a first differential input. A first inverter of the first converter has a first feedback device coupled input-to-output to provide a first transimpedance amplifier load. The first inverter is coupled to the first transconductor. The second converter includes a second transconductor coupled to receive the bias voltage to adjust a second tail current, and a second differential input. A second inverter of the second converter has a second feedback device coupled input-to-output to provide a second transimpedance amplifier load. The second inverter is coupled to the second transconductor.

Abstract: A key press detecting circuit and method detect the status of multiple keys through a single pin. In an embodiment, a constant current is provided to apply to a key module through a single pin, to generate a voltage at the single pin that is related to the equivalent resistance of the key module observed from the single pin, and the voltage of the single pin is compared with a set of reference values to identify the status of the plurality of keys. In another embodiment, a variable current is provided to apply to a key module through a single pin in such a way that the variable current is adjusted to maintain a constant voltage at the single pin, and the variable current is compared with a set of reference values to identify the status of the plurality of keys.

Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.

Abstract: A semiconductor device with a current sampler and a start-up structure, comprises first, second and third high-voltage transistors, and a resistor, wherein: a drain terminal of the first transistor is respectively connected to a drain terminal of the second transistor, a drain terminal of the third transistor and one end of the resistor; a source terminal of the first transistor is grounded, and a gate terminal of the first transistor is connected to a gate terminal of the second transistor; the other end of the resistor is connected to a gate terminal of the third transistor; wherein the resistor is wound and formed in a common voltage withstand region of the first transistor, the second transistor and the third transistor, or in a voltage withstand region of the first transistor only, or in the voltage withstand region of the third transistor only.

Abstract: A high-side semiconductor-switch driving method includes generating power for controlling a high side semiconductor switch. The high side semiconductor switch has a control terminal and the power allows a current to flow into the control terminal of the high side semiconductor switch to switch the high side semiconductor switch. The voltage at the control terminal of the high side semiconductor switch is quantified. The power dependent on the voltage at the control terminal of the high side semiconductor switch is controlled so that the current provided is increased when the voltage at the control terminal indicates that the current is not sufficient to switch the high side semiconductor switch.

Abstract: A driver circuit for driving a power transistor includes a converter having a first transistor and a second transistor coupled in series between a supply node and a reference node. The converter is configured to receive a first signal and in response thereto generate a second signal for selectively controlling status of the power transistor. The ratio of a first leakage current of the first transistor to a second leakage current of the second transistor is used in the generation of the second signal which is applied to the control terminal of a transistor switch that is selectively actuated to turn off the power transistor.

Abstract: An exemplary gate drive circuit and method are disclosed for controlling a gate-controlled component, the gate drive circuit having a PI controller adapted to receive an input reference signal and to control a gate voltage of the gate-controlled component. The gate drive circuit can include a first feedback loop for the PI controller, the first feedback loop having a first gain (kv), a second feedback loop for the PI controller, the second feedback loop having a second gain (ki), and a clipping circuit adapted to modify a feedback signal in the second feedback loop during turn-on of the gate-controlled component when the time derivative of the collector current is negative. The first feedback loop can include a first blanking circuit adapted to cut the feedback loop when the gate-controlled component is in a blocking state.

Abstract: In various embodiments, a switch circuit arrangement may include a switch circuit, a driver circuit and a supply circuit. The driver circuit may be configured to control the switch circuit. The supply circuit may be configured to power the driver circuit. The supply circuit may include a first circuit configured to modify an output impedance of the supply circuit to have a first impedance when the driver circuit controls the switch circuit to be in a conducting state and to have a second impedance when the driver circuit controls the switch circuit to change from a non-conducting state to the conducting state.

Abstract: There is provided an apparatus for output buffering having a half-swing rail-to-rail structure. The apparatus provides output buffering by using a switch structure in order to attain a high slew rate and low power characteristics, thereby reducing current consumption. The provided apparatus for output buffering having a half-swing rail-to-rail structure includes a first output buffer, driven between a first voltage rail and a second voltage rail and outputting a first output signal in response to a first input signal and a second input signal, and a second output buffer, driven between the first and the second voltage rails and a third voltage rail and outputting a second output signal in response to a third input signal and a fourth input signal.

Abstract: A PLL includes an oscillator, multiple time-to-digital converters (TDCs) and a system for the remaining functionality. The TDCs measure the oscillator's phase against respective multiple reference clocks. The system compares the respective measured phases with respective desired phases to obtain phase error signals. One is selected to close the loop. The others are monitored and adjusted when not equal to zero. When a new reference clock must be used, the loop is changed from including the old phase error signal to the new. The old phase error was zero because the loop was in lock, the new phase error is zero because it was monitored and adjusted. Therefore, upon switching the loop from the old to the new phase error signal, the loop remains locked and switching is hitless.

Abstract: In one embodiment, a delay-locked loop (DLL) for synchronizing a phase of a periodic digital output signal with a phase of a periodic digital input signal includes a deskew element responsive to the periodic digital input signal to the DLL and the periodic digital output signal from the DLL for suppressing jitter in the periodic digital output signal by synchronizing transitions in the periodic digital output signal with transitions in the periodic digital input signal and generating a final jitter-suppressed periodic digital output signal.

Abstract: A signal generating circuit comprises a signal synchronizing module and a control circuit. The signal synchronizing module includes: a first delay path for delaying a target signal to generate a first delayed target signal by utilizing a first delay amount; a second delay path for delaying the target signal to generate a second delayed target signal by utilizing a second delay amount larger than the first delay amount; and a logic module, for gating the target signal to generate a first output signal according to the first delayed target signal, or gating the target signal to generate a second output signal according to the second delayed target signal. The control circuit controls the signal synchronizing module to output one of the first output signal and the second output signal according to phase difference between the target signal and a reference signal.

Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

Abstract: A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain multiplier memory and a perturbation unit configured to generate a calibration offset signal to initiate a calibration. Additionally, the phase-locked loop digital bandwidth calibrator also includes a digital bandwidth calibration unit configured to provide a corrected nominal gain for storage in the gain multiplier memory, wherein a digital gain correction for the corrected nominal gain is determined by a digital integration stage and a correction database. A phase-locked loop digital bandwidth calibration method is also provided.