Abstract: Exemplary embodiments or implementations are disclosed of methods, apparatus, and systems for operating motors in variable speed situations. In an exemplary implementation, a method of controlling a variable-speed motor includes defining a control duration as a predetermined number of cycles of a multiple-phase power supply. Each speed in a range of speeds is defined by a corresponding number of the cycles of the control duration. Power is provided to the motor from the power supply at a selected one of the speeds, by enabling input from the power supply for the number of the cycles of the control duration corresponding to the selected speed.

Abstract: A clamp assembly for solar panels comprising a base and a clamp. The base has a baseplate and first and second spaced-apart struts connected to the baseplate to form a channel. Surfaces of the struts define slots adjacent to the channel. Beams are connected to the struts, and spacers are attached to the beams. Each spacer has an angled surface adjacent to the channel and a curved surface. The clamp includes a plate with fingers extending from the plate into the channel. The clamp further includes angled surfaces in contact with the spacer angled surfaces. Bolts extend through the plate so that most of the threaded portions are positioned between fingers. Corresponding nuts are positioned in the slots and inhibited from rotation during threading with the bolt by the slot surfaces. The clamp assembly is preferably made from a nonconductive material to inhibit arcing and the risk of electrical fire from incorrect or failed wiring.

Abstract: A solar array including a solar array assembly, hub assembly, and wing assembly.

Abstract: A string monitor comprises a modular base unit and one or more sensor modules which may include sensor modules for measuring DC voltage and current.

Abstract: A diagnosis device (17) for a solar power generation system, which diagnosis device (17) diagnoses a whole or a part of an output in the solar power generation system includes: a measurement data acquiring section (21) for acquiring an electric current value and a voltage value from an ammeter (12a) and a voltmeter (12b), respectively; and an diagnosing section (25) diagnoses the output on the basis of a motion of a power point indicated by the electric current value and the voltage value thus acquired.

Abstract: One aspect of this disclosure is an apparatus including an oscillator that includes a secondary LC circuit to increase a tuning range of the oscillator and/or to reduce a phase noise of the oscillator. Another aspect of this disclosure is an apparatus that includes oscillator with a primary LC circuit and a secondary LC circuit. This oscillator can operate in a primary oscillation mode or a secondary oscillation mode, depending on whether oscillation is set by the primary LC circuit or the secondary LC circuit.

Abstract: The invention relates to a frequency generator assembly, including at least one oscillator and an electronic signal processing device, which is designed in such a way that the electronic signal processing device provides an electric clock signal (f) having a defined frequency as an output signal of the frequency generator assembly, wherein the defined frequency depends on the vibration frequency of the oscillator, wherein the oscillator includes at least one micromechanical seismic mass which is vibrationally excited by at least one driving device, whereupon the electronic signal processing device generates and provides the electric clock signal (f) according to the vibration frequency of the at least one seismic mass.

Abstract: An oscillation circuit includes a temperature compensating section to which electric power is supplied from a main power supply and a backup power supply, an oscillating section, a function of which is compensated by a signal from the temperature compensating section, and a switch and a power-supply monitoring circuit configured to select, when the temperature compensating section is not operating, at least one of the main power supply and the backup power supply and control connection to the temperature compensating section.

Abstract: A triple cascode power amplifier is provided. The triple cascode power amplifier includes a first-stage transistor pair, a second-stage transistor pair and a third-stage transistor pair. The first-stage transistor pair comprises two first-stage transistors that respectively receive two dynamic bias voltages with opposite polarities. The second-stage transistor pair is coupled with the first-stage transistor pair to form a first node and comprise two second-stage transistors coupled with each other to form a second node. The third-stage transistor pair is coupled with the second-stage transistor pair and comprises two third-stage transistors for outputting a differential signal. The first-stage transistor pair and the second-stage transistor pair are low voltage components while the third-stage transistor pair is a high voltage component. The power amplifier transforms the differential signal into a single-ended signal for output.

Abstract: It is presented a power amplifier assembly comprising; a radio frequency multi-order power amplifier comprising a circuit board; a grounding structure connected to the radio frequency multi-order power amplifier and comprising a recess; a combining network connected to a plurality of outputs of the radio frequency multi-order power amplifier. The combining network comprises: a plurality of input connection points, wherein each of the plurality of input connection points is connected to a respective output of the plurality of outputs of the radio frequency multi-order power amplifier; an output connection point; and a conductor arrangement comprising a plurality of conductive paths arranged between the plurality of input connection points and the output connection point; wherein at least one of the plurality of conductive paths is at least partly formed by a suspended conductor positioned in the recess of the grounding structure.

Abstract: Radio frequency (RF) power amplifier (PA) circuitry and a PA envelope power supply are disclosed. The RF PA circuitry receives and amplifies an RF input signal to provide an RF output signal using an envelope power supply signal, which is provided by the PA envelope power supply. The RF PA circuitry operates in either a normal RF spectral emissions mode or a reduced RF spectral emissions mode. When reduced RF spectral emissions are required, the RF PA circuitry operates in the reduced RF spectral emissions mode. As such, at a given RF output power, during the reduced RF spectral emissions mode, RF spectral emissions of the RF output signal are less than during the normal RF spectral emissions mode. As a result, the reduced RF spectral emissions mode may be used to reduce interference between RF communications bands.

Abstract: A radio frequency system includes a first power splitter, a first push-pull power amplifier and a second push-pull power amplifier. The first power splitter is configured to receive a first radio frequency signal and generate a first output signal and a second output signal. The first push-pull power amplifier is configured to amplify the first output signal. The first push-pull power amplifier comprises a first set of transistors including at least two radio frequency power transistors and a first output transformer. The second push-pull power amplifier is configured to amplify the second output signal. The second push-pull power amplifier includes a second set of transistors including at least two radio frequency power transistors and a second output transformer. An output of the first transformer is galvanically and directly connected to an output of the second output transformer.

Abstract: Various embodiments provide a bias circuit for a radio frequency (RF) power amplifier (PA) to provide a direct current (DC) bias voltage, with bias boosting, to the RF PA. The bias circuit may include a bias transistor that forms a current mirror with an amplifier transistor of the RF PA. The bias circuit may further include a first resistor coupled between the gate terminal and the drain terminal of the bias transistor to block RF signals from the gate terminal of the bias transistor. The bias circuit may further include a second resistor coupled between the drain terminal of the bias transistor and the RF PA (e.g., the gate terminal of the amplifier transistor). An amount of bias boosting of the DC bias voltage provided by the bias circuit may be based on an impedance value of the second resistor.

Abstract: An amplifier includes a transistor chip, a matching chip with a capacitor group having multiple MIM capacitors, each of the MIM capacitors including a lower electrode, a dielectric, and an upper electrode, a bonding wire that electrically connects the transistor chip to the upper electrode of any one of the MIM capacitors of the capacitor group and transmits a high-frequency signal, and a case that accommodates the transistor chip and the matching chip. The lower electrodes of the MIM capacitors are grounded, and capacitance values of each of the MIM capacitors of the capacitor group are different from each other.

Abstract: Disclosed is a differential power amplifier using mode injection, which includes: a first transistor of which the gate receives a first signal and the source is connected to the ground; a second transistor of which the gate receives a second signal and the source is connected to the ground; a third transistor of which the source is connected to the source of the first transistor; a fourth transistor of which the source is connected to the source of the second transistor; a fifth transistor of which the source is connected with the drain of the first transistor and the drain is connected with a first output port and the drain of the third transistor; and a sixth transistor of which the source is connected with the drain of the second transistor and the drain is connected with a second output port and the drain of the fourth transistor.

Abstract: A high-output electric power amplifier using a depression-type FET includes a drain voltage supply portion adapted to create a positive voltage to be applied to a drain terminal in the depression-type FET, and a gate bias voltage supply portion adapted to create a negative voltage to be applied to a gate terminal in the depression-type FET, wherein the drain voltage supply portion uses an external commercial power supply as an electric power source, and the gate bias voltage supply portion uses a battery as an electric power source, in order to certainly prevent breakdowns of the FET due to excessive electric currents.

Abstract: Disclosed are circuits, devices, systems and methods related to an enable circuit for a radio-frequency (RF) amplifier. In some embodiments, the enable circuit can be configured to control a low-noise amplifier (LNA). The enable circuit includes a plurality of input ports, with each input ports being configured to receive a control signal. The enable circuit further includes a logical section connected to the input ports and configured to be capable of generating a plurality of output signals based on different combinations of the plurality of control signals. The output signals include either or both of enable and power shut-off signals for the LNA.

Abstract: A power amplifying circuit includes: a signal input terminal, a common-mode voltage input terminal, a power tube control unit, a feedback loop, a driving unit, a first switching element, a second switching element, a low-pass filter, a speaker, a source voltage terminal, and a ground terminal, wherein the power tube control unit includes: an operational amplifier, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a eighth switch, a ninth switch, a third switching element connected with the third switch and the fourth switch, a fourth switching element connected with the fifth switch and the sixth switch, and a comparator connected with the third switching element and the fourth switching element. The present invention is able to realize functions of CLASS AB amplifier and CLASS D amplifier.

Abstract: An amplification circuit (100) comprising a first filter (102) and an LNA (110). The first filter (102) comprising an input (104) for receiving an input signal; a first differential output (106); and a second differential output (108). The first filter (102) has a differential mode of operation for frequencies in its pass-band (706, 806) and a common mode of operation for frequencies outside its pass-band (706, 806), and may be an acoustic wave filter. The LNA (110) comprising a first differential input (112) connected to the first differential output (106) of the first filter (102); a second differential input (114) connected to the second differential output (108) of the first filter (102); and an output (116) for providing an amplified output signal.

Abstract: A scalable radio frequency (RF) generator system including at least one power supply, at least one power amplifier receiving input from the power supply, and a power supply control module, and a system controller. Output from the at least one power supply can be combined and applied to each of the power amplifiers. Output form each of the at least one power amplifiers can be combined to generate a single RF signal. A compensator module controls operation of the at least one power supply. The compensator module, system control module, and power supply controller communicate in a daisy chain configuration.

Abstract: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.

Abstract: In accordance with an embodiment, a system for amplifying a signal provided by a capacitive signal source includes an impedance converter having an input node configured to be coupled to a first terminal of the capacitive signal source, and an adjustable capacitive network having a first node configured to be coupled to a second terminal of the capacitive signal source and a second node coupled to an output node of the impedance converter.

Abstract: Switched capacitor circuits and charge transfer methods include a sampling phase and a transfer phase. Circuits and methods are implemented via a plurality of switches, a set of at least two capacitors, at least one buffer amplifier, and an operational amplifier. In one example, during the sampling phase at least one input voltage is sampled, and during the transfer phase at least a first reference voltage provided by the at least one buffer amplifier is subtracted from the at least one input voltage using the operational amplifier. The same set of at least two capacitors may be used in both the sampling phase and the transfer phase.

Abstract: A communication device (1) comprising a speaker (2), a microphone (3), a noise detection module (7) adopted to determine an ambient noise level (NL) from a microphone signal received from the microphone (3) and an automatic volume control module (4), which in dependence of a change in noise level adjusts the speaker volume level (SL) to an adjusted level during an adaption time interval (TA). The communication device (1) comprises a motion sensor (5), and the length of the adaption time interval (TA) depends on a motion signal received from the motion sensor (5).

Abstract: Provided is a control program of an audio device which performs automatic control on the audio device so as not to interfere with a telephone call. A control unit of a mobile telephone equipped with a telephone communication unit is caused to function as an operation detector that detects a user operation, an incoming call detector that detects an incoming telephone call to the telephone communication unit, and a command transmitter that communicates with an audio device that outputs a reproduced sound, and the command transmitter transmits a command message containing control contents corresponding to the user operation to the audio device when the operation detector detects the user operation, and transmits a command message for controlling the reproduced sound to the audio device when the incoming call detector detects the incoming telephone call.

Abstract: The estimated gain profile of an amplifier can be modified during operation of the amplifier utilizing detected values of the amplification level of signals produced by the amplifier. The amplification levels can be detected at a location that is remote from the amplifier. New expected amplification levels can be determined for corresponding control signal values in the estimated gain profile. Digital filtering such as Kalman filtering can be used to determine the new expected amplification levels. The estimated gain profile can be modified with the new expected amplification levels.

Abstract: There is provided an acoustic processing device capable of applying acoustic processing matching listener's sense to reproduce an audio signal with satisfactory sound quality in terms of auditory sense irrespective of the characteristics of a sound source. The acoustic processing device (1) includes a gain calculation section (5) that calculates a gain correction amount corresponding to predetermined auditory sense characteristics, an offset gain calculation section (6) that calculates a gain offset based on a frequency characteristics of an audio signal analyzed by a frequency analysis section (3), an acoustic signal generation section (7) that generates an acoustic signal based on the gain correction amount and the gain offset, and an acoustic addition section (8) that adds the generated acoustic signal to the audio signal.

Abstract: A stack type common mode filter (CMF) for high frequency may improve high frequency characteristics, like removing an impedance difference between terminals by not overlapping terminal portions of multiple stack structures with upper and lower magnetic substances, and removing noise in a common mode and removing a signal distortion in a differential mode by removing an unnecessary parasitic impedance from terminal portions, and thus the stack type CMF for high frequency may be applicable at a high frequency compared to a conventional CMF.

Abstract: A power distributing duplexer system is provided. In some aspects, the system includes a duplexer configured to couple an antenna to a transmitter and a receiver. The system also includes a balancing network coupled to the duplexer. The balancing network includes a network impedance. The balancing network is configured to adjust the network impedance to match an antenna impedance of the antenna. The balancing network includes a plurality of balancing network modules coupled to the duplexer. Each of the plurality of balancing network modules is configured to receive a portion of an output voltage from the duplexer.

Abstract: A resonator includes a resonator element including a base section, vibrating arms extending from the base section, and a support arm disposed between the vibrating arms, a package adapted to support the resonator element, and electrically-conductive adhesives adapted to fix the support arm to the package, the support arm includes a tip portion and a width-decreasing portion having a width smaller than the width of the tip portion, and the electrically-conductive adhesive has contact with at least a part of the width-decreasing portion in a planar view.

Abstract: An antenna matching circuit includes at least two signal paths are connected to one antenna connection. The signal paths are designed to transmit and/or receive RF signals. A matching circuit includes a discrete line for phase shifting integrated at the antenna end in at least one of the signal paths. In this case, at least one of the capacitances contained in the discrete line is in the form of a micro-acoustic resonator, whose resonance is shifted sufficiently far that it is outside the pass band of the respective signal paths.

Abstract: A position coordinate difference calculation section 5 calculates a position coordinate difference between a position coordinate of an output digital signal and a position coordinate of an input digital signal close to it. AN FIR coefficient memory 9 stores FIR coefficients of an FIR-LPF having such a characteristic as to cut off frequency components equal to or higher than ½ of an output sampling rate. When the position coordinate difference is input, the FIR coefficient memory outputs FIR coefficients corresponding to position coordinate differences between position coordinates of a certain number of input digital signals existing in the vicinity of the position coordinate of the output digital signal and the position coordinate of the output digital signal. AN FIR computation unit 3 performs FIR-LPF interpolation computation by using a certain number of the input digital signals and the FIR coefficients and obtains the output digital signal.

Abstract: A tunable series resonant circuit includes a voltage source, a source impedance, a variable capacitor, a series inductor, and a load impedance. The variable capacitor includes a sPAC (series programmable array of capacitors) having desirable characteristics for a tunable series resonant circuit. The sPAC may be a binary weighted sPAC, a thermometer coded sPAC, or some other sPAC.

Abstract: A wireless communications system includes a clock module, a global positioning system (GPS) module, an integrated circuit for a cellular transceiver, and a baseband module. The clock module is configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). The GPS module is configured to operate in response to the first clock reference. The integrated circuit includes a system phase lock loop (PLL) configured to (i) operate in response to the first clock reference, and (ii) generate a corrected clock reference by performing AFC on the first clock reference in response to an AFC signal. The baseband module is configured to (i) operate in response to the first clock reference from the clock module, and (ii) generate the AFC signal.

Abstract: An integrated circuit is provided that includes a plurality of modules comprising at least one clock-gated module and a controller unit, which is arranged to enable and disable provision of a clock signal to the at least one clock-gated module. The at least one clock-gated module includes one or more electronic circuits arranged to be in a first state of an electrical stress condition during a first portion of a period of time and in a second state of less electrical stress than in the first state during a second portion of the period of time. The at least one clock-gated module is further arranged to switch the one or more electronic circuits between the first state and the second state such that a change of a characteristic of at least one of the one or more electronic circuits caused by the electrical stress condition is at least partially reduced.

Abstract: A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.

Abstract: A three dimensional integrated circuit includes a master circuit, a slave circuit, and a through-silicon via (TSV). The master circuit is configured to receive and process an input data, a data strobe signal (DQS) and an input command to output a writing data signal to a master die. The through-silicon via (TSV) is electrically coupled between the master circuit and the slave circuit. The master circuit is configured to transfer the writing data signal to a slave die through the TSV. Furthermore, a method for controlling a three dimensional integrated circuit is disclosed herein.

Abstract: A relaxation oscillator shares charging current and comparator biasing current between just two current sources, thereby relaxing requirements on total supply current. The resulting reduction in power consumption has no adverse effect on the speed and accuracy of the oscillator. A switching arrangement directs charging and biasing currents between the two current sources and two charging capacitors and their associated comparators.

Abstract: A clock doubler circuit includes a filtering circuit. The filtering circuit includes a first input to receive a first clock signal, a first output to provide a second clock signal, and a second output to provide a third clock signal. The third clock signal is a complementary signal to the second clock signal. The first clock signal, the second clock signal, and the third clock signal are at a first clock frequency. The second clock signal is a low pass filtered version of the first clock signal. The clock doubler circuit includes a frequency doubling circuit. The frequency doubling circuit includes a first input to receive the second clock signal and a second input to receive the third clock signal. The frequency doubling circuit includes an output node. The output node provides a fourth clock signal at a second clock frequency that is twice the first clock frequency.

Abstract: An AC-inverting amplifier for a waveform conversion circuit includes a first MOS transistor of a first conductivity type having a gate that receives an input signal, a drain that provides an inverted amplified output signal, and a source coupled to a first power supply voltage. A current source provides a first bias current and a second bias current in proportion to the first bias current. The second bias current is coupled to the drain of the first MOS transistor to bias the first MOS transistor. The first bias current has a magnitude that is determined by a DC voltage applied at the gate of the first MOS transistor.

Abstract: The power supply voltage transition comparison circuit includes a comparator evaluation voltage setting circuit, a comparator, a voltage evaluation circuit, and an evaluation voltage setting value output circuit. The comparator evaluation voltage setting circuit generates a divided voltage of one of a power supply voltage and a reference voltage. The comparator compares the other of the power supply voltage and the reference voltage with the divided voltage. The voltage evaluation circuit evaluates the power supply voltage based on a result of a comparison between the other voltage and the divided voltage. The evaluation voltage setting value output circuit changes a ratio between the one voltage and the divided voltage based on a result of an evaluation of the power supply voltage.

Abstract: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.

Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs). In embodiments, a body-bias circuit may derive a bias voltage based on a radio frequency signal applied to a switch field-effect transistor and apply the bias voltage to the body terminal of the switch field-effect transistor.

Abstract: A circuit includes a first power node configured to carry a voltage K·VDD, a second power node configured to carry a zero reference level, an output node, K P-type transistors serially coupled between the first power node and the output node, and K N-type transistors serially coupled between the second power node and the output node. Gates of the K P-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of source-gate voltages or absolute values of drain-gate voltages are equal to or less than VDD. Gates of the K N-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of gate-source voltages or gate-drain voltages are equal to or less than VDD.

Abstract: A desaturation detection circuit for use between the desaturation detection input of an optocoupler and the output of a power switching device, the desaturation detection circuit comprising: a threshold setting element having an input and an output, the input for connection to the output of a power switching device via one or more diode(s), the threshold setting element being arranged to set a threshold voltage at the input at which the threshold setting element will provide an output at the output of the threshold setting element when the input voltage is exceeded, and a detector having an input connected to the output of the threshold setting element and an output connectable to a desaturation detection input of an optocoupler, the detector being arranged to detect an output at the output of the threshold setting element and in response to provide a control signal at the output of the detector for the desaturation detection input to trigger a desaturation routine in the optocoupler.

Abstract: An I/O circuit for use with an industrial controller provides a photovoltaic optical isolator communicating between a controller and a field-side of the I/O circuit, the photovoltaic optical isolator eliminating the need for high wattage power dropping circuits for powering the field-side of the I/O circuit from high-voltage field signals. The field effect transistor type transistors permit use of the low-power photovoltaic optical isolator while allowing flexible connections to various field circuit types.

Abstract: A non-contact sensing module includes a coil printed circuit board in which a reference pattern coil may be formed at an upper surface and in which a sensing pattern coil may be formed at a lower surface and that has a mounting hole at the center, and a main printed circuit board that may be coupled to the mounting hole and that may be vertically disposed at an upper surface of the coil printed circuit board and that may be electrically connected to the reference pattern coil and the sensing pattern coil.

Abstract: An inductive proximity sensor and a method comprising a transmitter coil, a receiver coil, an excitation device which is connected to the transmitter coil and an evaluation device, wherein the evaluation device is designed to generate an output signal which depends on a voltage ratio between a transmission voltage of the transmitter coil and/or of the excitation device and a reception voltage of the receiver coil, wherein the excitation device is designed to generate a sinusoidal radio frequency transmission voltage. An inductive proximity sensor and a method comprising a transmitter coil, a receiver coil, an excitation device which is connected to the transmitter coil and an evaluation device, wherein the evaluation device is designed to generate an output signal which is dependent on a reception voltage of the receiver coil, wherein the excitation device is designed to generate a sinusoidal radio frequency transmission voltage with a constant amplitude.

Abstract: Electronic interface and method for reading a capacitive sensor that includes one input capacitor (30) or several input capacitors, in which the capacitive sensor is excited with a two-level voltage (Vlow, Vhigh) and read by a charge-sense amplifier whose output is sampled in four successive instants. An evaluation unit (333) is arranged to compute two difference values (V12, V34) between two pairs of samples corresponding to different voltage levels and to combine said difference values into an output value (V_out_raw) proportional to the charge transferred to the input of the charge-sense amplifier and an error value (error_bit) sensitive to a time derivative of a noise current din/dt.

Abstract: Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor is arranged in series between a termination switch and a common voltage node at the termination end of each bus conductor. Information regarding the current or anticipated bus state is received from an external device such as a bus controller or may be derived by sensing activity on the bus. For example, clock frequency detection logic coupled to clock lines of the bus senses the current operational speed of the bus. A highest-value termination resistance predetermined to be consistent with reliable bus operation under conditions of the current or anticipated bus state is selected for each bus conductor. A bus conductor termination may be taken to a high impedance state by opening the associated termination switch. Decreased average bus power consumption may result.