Abstract: Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one small core. Specifically, embodiments include receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message.

Abstract: The present invention relates to the transcription of audio, and, more particularly, to an engine, system and method of providing audio transcriptions for use in content resources.

Abstract: API associations among a plurality of service application programming interfaces may be identified by analyzing service API call logs, which contain data associated with invocation of the plurality of application programming interfaces by a plurality of applications, wherein sets of APIs that are determined to be called together are identified. For a set of service APIs, a plurality of applications that invoke the APIs in the set is identified. A sequence of API calls by an application in the plurality of applications is identified, wherein multiples sequences of APIs are identified, one sequence of API calls identified respectively for one application in the plurality of applications. An application pattern is determined based on the multiple sequences of service APIs.

Abstract: An approach for implementing a live application control platform for providing live application control triggers via a multicast/broadcast transmission session. The approach includes receiving an input for specifying an application event trigger. The approach also includes delivering the application event trigger over a multicast data channel, wherein the application event trigger is received by a device within a coverage area of the multicast data channel to trigger an event to be performed by one or more applications of the device.

Abstract: An electronic device may maintain separate OS domains associated with security permissions. The OS domain may implement separate corresponding clipboard services. A clipboard agent or clipboard mediator service may receive a clipboard data request from a first application. The clipboard agent may determine which OS domain has most recently processed a store command associated with storing data in a corresponding clipboard service of the OS domain. The clipboard agent associated with the OS domain that most recently stored content may determine whether to send the data from the corresponding clipboard service based at least in part on permissions associated with the OS domain. Security of the clipboard access may be enforced on a per domain basis. Access to clipboard content may be mediated at the time of the request without a need to share data prior to the request.

Abstract: There is provided a computer embedded apparatus comprising: a process control unit configured with a plurality of software layers wherein each of the layers provides a service to an upper layer and each of the layers includes, a message processing unit configured to control a sequence of messages input to or output from the layer.

Abstract: An information handling system includes a processor and a configuration detection and error handling module operable to read a first tag data file from a first storage volume, read a second tag data file from a second storage volume, and determine that the first storage volume and the second storage volume are configured as mirrored storage volumes based upon the first tag data file and the second tag data file.

Abstract: A technique for failure monitoring and recovery of a first application executing on a first virtual machine includes storing machine state information during execution of the first virtual machine at predetermined checkpoints. An error message that includes an application error state at a failure point of the first application is received, by a hypervisor, from the first application. The first virtual machine is stopped in response to the error message. The hypervisor creates a second virtual machine and a second application from the stored machine state information that are copies of the first virtual machine and the first application. The second virtual machine and the second application are configured to execute from a checkpoint preceding the failure point. In response to receipt of a failure interrupt by the second application, one or more recovery processes are initiated in an attempt to avert the failure point.

Abstract: Alert conditions datasets are created from historic data taken from actual incidents for which the alert condition datasets are to indicate during future operations. A networked computers system including various devices is monitored for alert conditions associated with one, or more, of the devices. The severity of an alert is based on the number of alert conditions met for a given alert conditions dataset.

Abstract: A notification of a problem associated with an application may be received. A difference may be determined between a problem version of the application and an operational version of the application to identify a change associated with the problem. A modification may be performed to the problem version of the application to resolve the problem associated with the change based on determining of the difference. Performing the modification may comprise associating a priority for resolution of the problem. The problem version of the application may be rolled back or rolled forward to the operational version of the application based on the priority for resolution.

Abstract: One embodiment provides a system that facilitates processing of error-condition information associated with a content-centric network (CCN) message transmitted over a network. During operation, the system receives, by a first node, a packet that corresponds to a CCN message, where a name for the CCN message is a hierarchically structured variable length identifier (HSVLI) which comprises contiguous name components ordered from a most general level to a most specific level. Responsive to determining that the CCN message triggers an error condition, the system generates an interest return message by pre-pending a data structure to the CCN message, where the data structure indicates the error condition. The system transmits the interest return message to a second node.

Abstract: Systems and methods for partial bad block reuse may be provided. Data may be copied from a block of a first memory to a block of a second memory. A post write read error may be detected in a first portion the data copied to the block of the second memory without detection of a post write read error in a second portion of the data copied to the block of the second memory. The block of the second memory may be determined to be a partial bad block usable for storage in response to detection of the post write read error in the first portion of the data but not in the second portion of the data.

Abstract: A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance.

Abstract: A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.

Abstract: Described herein are techniques for storing data in a redundant manner on a plurality of storage units of a storage system. While all of the storage units are operating without failure, only error-correction blocks are stored on a first one of the storage units, while a combination of data blocks and error-correction blocks are stored on a second one of the storage units. Upon failure of the second storage unit, one or more data blocks and one or more error-correction blocks formerly stored on the second storage unit are reconstructed, and the one or more reconstructed data blocks and the one or more reconstructed error-correction blocks are stored on the first storage unit.

Abstract: Methods and systems for managing and locating available storage space in a system comprising data files stored in a plurality of storage devices and configured in accordance with various data storage schemes (mirroring, striping and parity-striping). A mapping table associated with each of the plurality of storage devices is used to determine the available locations and amount of available space in the storage devices. The data storage schemes for one or more of the stored data files are changed to a basic storage mode when the size of a new data file configured in accordance with an assigned data storage scheme exceeds the amount of available space. The configured new data file is stored in accordance with the assigned data storage scheme in one or more of the available locations and the locations of the new data file are recorded.

Abstract: A method recovers an information handling system (IHS) from a non-operational state. The method includes determining if the non-operational state of the IHS has occurred. In response to determining that the non-operational state of the IHS has occurred, a basic input-output (BIOS) recovery device is identified as being coupled to an embedded controller. In response to identifying that the BIOS recovery device is coupled to the embedded controller, an IHS type is transmitted to the BIOS recovery device. The BIOS recovery device is signaled to determine if the BIOS recovery device contains a BIOS payload corresponding to the IHS type. In response to determining that the BIOS recovery device contains the BIOS payload corresponding to the IHS type, the BIOS recovery device is triggered to transmit the BIOS payload to the embedded controller. The IHS is triggered to restart using the new BIOS payload.

Abstract: According to certain aspects, a method of creating customized bootable images for client computing devices in an information management system can include: creating a backup copy of each of a plurality of client computing devices, including a first client computing device; subsequent to receiving a request to restore the first client computing device to the state at a first time, creating a customized bootable image that is configured to directly restore the first client computing device to the state at the first time, wherein the customized bootable image includes system state specific to the first client computing device at the first time and one or more drivers associated with hardware existing at time of restore on a computing device to be rebooted; and rebooting the computing device to the state of the first client computing device at the first time from the customized bootable image.

Abstract: What is disclosed is a method of operating a volume access system. The method includes processing at least a first file to generate a file system view of the first file comprising a plurality of items within the first file, and providing the file system view of the first file over a network interface as a hierarchical data volume. The method also includes receiving an access request for a requested item of the hierarchical data volume over the network interface, and in response, providing access to a first item of the plurality of items within the first file corresponding to the requested item.

Abstract: Approaches for prioritizing backup of files are described. In one example, a backup prioritizing parameter for a file shortlisted for backup is identified. Once the backup prioritizing parameter is identified, a position of the file for placing within a backup queue for backup, is subsequently determined based on the backup prioritizing parameter.

Abstract: A source remote copy configuration in a source storage system is migrated to a destination storage system as a destination remote copy configuration. The destination primary storage apparatus of the destination storage system defines a virtual volume mapped to the primary volume provided by the source primary storage apparatus which is a storage area of the virtual volume; takes over a first identifier of the primary volume to the virtual volume; transfers, when the virtual volume receives an access request, the access request to the source primary storage apparatus to write data in the primary volume; and takes over the first identifier from the virtual volume to another primary volume provided by the destination primary storage apparatus, after completion of copy of data from primary volume of the source primary storage apparatus into primary volume of the destination primary storage apparatus and secondary volume of the destination secondary storage apparatus.

Abstract: Techniques for processing changes in a cluster database system are provided. A first instance in the cluster transfers a data block to a second instance in the cluster before a redo record that stores one or more changes that the first instance made to the data block is durably stored. The first instance also transfers, to the second instance, a block change timestamp that indicates when a redo record for the one or more changes was generated by the first instance. The first instance also separately sends, to the second instance, a last store timestamp that indicates when the last redo record that was durably stored was generated by the first instance. The block change timestamp and the last store timestamp are used by the second instance when creating redo records for changes (made by the second instance) that depend on the redo record generated by the first instance.

Abstract: The System Integrity Guardian can protect any type of object and repairs and restores the system back to its original state of integrity. The Client component is the user interface for administering the System Integrity Guardian environment. An administrator can determine which servers to protect, which objects to protect, and what actions will be taken when an event that breaches integrity occurs. The Monitor Agent component is the watchdog of the System Integrity Guardian that captures and addresses any event that occurs on any object being protected. The Server component includes the server and the Protected Object Central Repository. The authoritative copies are maintained, digital signatures are created and stored, objects are validated, and communication between the three units is performed.

Abstract: A method for enabling a distributed computing system to tolerate system faults during the execution of a client process. The method includes instantiating an execution environment relating to the client process; executing instructions within the execution environment, the instructions causing the execution environment to issue further instructions to the distributing computing system, the further instructions relating to actions to be performed with respect to data stored on the distributed computing system. An object interface proxy receives the further instructions and monitors the received to determine if the execution environment is in a desired save-state condition; and, if so, save a current state of the execution environment in a data store.

Abstract: Technology is disclosed for recovering I/O modules in a storage system using in-band alternate control path (ACP) architecture (“the technology”). The technology enables a storage server to transmit control commands, e.g., for recovering an I/O module, to the I/O module over a data path that is typically used to transmit data commands. The control commands are typically transmitted using ACP that is separate from the data path. By enabling transmission of control commands over the data path, the technology eliminates the need for separate medium for ACP, at least in part, to transmit the control commands. The technology can be implemented in a pure in-band ACP mode, which supports recovering an I/O module of a storage shelf in which at least one I/O module is responsive, and/or in a mixed in-band ACP mode, which supports recovery of I/O modules of a storage shelf in which all I/O modules are non-responsive.

Abstract: Systems, methods, and computer program products for managing a consensus group in a distributed computing cluster, by determining that an instance of an authority module executing on a first node, of a consensus group of nodes in the distributed computing cluster, has failed; and adding, by an instance of the authority module on a second node of the consensus group, a new node to the consensus group to replace the first node. The new node is a node in the computing cluster that was not a member of the consensus group at the time the instance of the authority module executing on the first node is determined to have failed.

Abstract: Exemplary embodiments of the present invention relate to a failure recovery apparatus of digital logic circuit and method thereof when a fault occurs in the digital logic circuit. A failure recovery apparatus according to an embodiment of the present invention comprises: a fault detection block configured to determine fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having a first cycle; and a failure recovery block configured to perform a failure recovery operation of the plurality of digital logic circuit by using a clock having a second cycle which is longer than the first cycle when it is determined as that a fault occurs. According to exemplary embodiments of the present invention, when a fault occurs in digital logic circuits due to external factors, it provides high reliability in failure recovery of the digital logic circuits.

Abstract: The disclosed method includes, at a storage controller of a storage system, receiving host instructions to modify configuration settings corresponding to a first memory portion of a plurality of memory portions. The method includes, in response to receiving the host instructions to modify the configuration settings, identifying the first memory portion from the host instructions and modifying the configuration settings corresponding to the first memory portion, in accordance with the host instructions. The method includes, after modifying the configuration settings corresponding to the first memory portion, sending one or more commands to perform memory operations having one or more physical addresses corresponding to the first memory portion and receiving a failure notification indicating failed performance of at least a first memory operation of the one or more memory operations. The method includes, in response to receiving the failure notification, executing one or more error recovery mechanisms.

Abstract: Systems and methods which provide mount catalogs to facilitate rapid volume mount are shown. A mount catalog of embodiments may be provided for each aggregate containing volumes to be mounted by a takeover node of a storage system. The mount catalog may comprise a direct storage level, such as a DBN level, based mount catalog. Such mount catalogs may be maintained in a reserved portion of the storage devices containing a corresponding aggregate and volumes, wherein the storage device reserved portion is known to a takeover node. In operation according to embodiments, a HA pair takeover node uses a mount catalog to access the blocks used to mount volumes of a HA pair partner node prior to a final determination that the partner node is in fact a failed node and prior to onlining the aggregate containing the volumes.

Abstract: A computer device may include logic configured to provide a centralized library for descriptive programming and other types of object descriptions to a testing script engine. The descriptive programming library may store test object descriptions for test objects associated with an application under testing. The logic may be further configured to provide a unification layer over all the object description types and to provide inheritance among the objects at the unification layer. The logic may be further configured to store a test object description, associated with a test object, in the descriptive programming library; identify a reference to the test object in a descriptive programming statement associated with the testing script engine; access the stored test object description in the descriptive programming library based on the identified reference to the test object; and identify an application object, associated with the application under testing, based on the stored test object description.

Abstract: Techniques described herein generally relate to a task management system for a chip multiprocessor having multiple processor cores. The task management system tracks the changing instruction set capabilities of each processor core and selects processor cores for use based on the tracked capabilities. In this way, a processor core with one or more failed processing elements can still be used effectively, since the processor core may be selected to process instruction sets that do not use the failed processing elements.

Abstract: Methods and arrangements to collect data related to the state or conditions of a system are described herein. Embodiments may comprise a data identifier to identify data to collect in response to an event and a data collector to collect the identified data. The data collector may comprise firmware, code in ROM, a state machine, and/or other logic, and the data identifier may also comprise firmware, code in ROM, a state machine, and/or other logic that may access information and/or code in a file or other data storage to identify the data to collect. The data storage may comprise information and/or code to identify the location of data to collect and, in some embodiments, the sequence with which to collect the data. For example, such a file may comprise an address or address range within memory of a specific component of the system such as a memory controller.

Abstract: An approach for validating code for an extract, transform and load (ETL) tool is provided. Naming, coding, and performance standards for the code is received. The code is exported to a job definition file and parsed. Violations of the standards are determined by determining the parsed code does not match the standards. A report identifying the violations is generated. Based on a review of the report and a rework of the code to comply with the standards, the reworked code is exported to another job definition file and parsed, the parsed reworked code is determined to not include the violations of the standards, and a second report is generated that indicates that the reworked code does not include the violations. An approval of the reworked code is received based on the second report.

Abstract: A system and method for determining execution trace differences in a computer-implemented software application is provided herein. A software application under analysis is executed at least twice, thereby generating first and second execution trace and associated first and second sets of execution data describing all the necessary data gained by program instrumentation at each program statement of source or bytecode level. These data are stored for at least two executions of the software application. This data is then compared to determine a set of differences between the first and second executions of the program. The set of differences may contain statement coverage data, execution trace data, variable values or influences among program instructions. The differences can be arranged according into historical order. The differences then can be analyzed to identify the location of the fault in the program or to map the related code to a feature in unknown code.

Abstract: Embodiments of the invention are directed to a system, method, and computer program product for assessing error notifications associated with one or more application functions. An exemplary embodiment includes receiving an indication of an error associated with at least one function in an application; extracting information associated with the application from one or more sources; and initiating a presentation of a second user-interface to enable a user to resolve the error, wherein the second user-interface comprises at least one of an aggregation of the information extracted from the one or more sources.

Abstract: A novel approach to test-suite reduction based on network maximum flows. Given a test suite T and a set of test requirements R, the method identifies a minimal set of test cases which maintains the coverage of test requirements. The approach encodes the problem with a bipartite directed graph and computes a minimum cardinality subset of T that covers R as a search among maximum flows, using the classical Ford-Fulkerson algorithm in combination with efficient constraint programming techniques. Test results have shown that the method outperforms the Integer Linear Programming (ILP) approach by 15-3000 times, in terms of the time needed to find the solution. At the same time, the method obtains the same reduction rate as ILP, because both approaches compute optimal solutions. When compared to the simple greedy approach, the method takes on average 30% more time and produces from 5% to 15% smaller test suites.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a memory controller. An apparatus includes a volatile memory medium located on a memory module. An apparatus includes a non-volatile memory medium located on a memory module. A memory controller is located on a memory module. A memory controller may be configured to provide access to at least a non-volatile memory medium over a direct wire interface with a processor.

Abstract: The embodiments described herein are used to allocate memory in a storage system. The method includes, at a memory controller in the storage system, determining a current memory allocation for a set of memory devices, wherein the set of memory devices is formatted with a ratio of first storage density designated portions to second storage density designated portions in accordance with the current memory allocation. The method further includes detecting satisfaction of one or more memory reallocation trigger conditions. The method further includes, in response to detecting satisfaction of one or more memory reallocation trigger conditions, modifying the ratio of the first storage density designated portions to the second storage density designated portions in the set of memory devices to generate a second memory allocation for the set of memory devices.

Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller reads first data from the non-volatile memory subsystem in response to a Flash access request received via the memory channel, and causes at least a portion of the first data to be written into the volatile memory subsystem in response to a dummy write memory command received via the C/A bus. The module control device includes status registers accessible by the computer system via the memory bus.

Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: A storage drive including a first and second memories and a controller. The second memory has a write cycle lifetime that is less than a write cycle lifetime of the first memory. Each of the first and second memories includes solid-state memory. The controller: determines a write frequency for a first logical address; and based on the write frequency, determines a write frequency ranking for the first logical address. The write frequency ranking is based on a weighted time-decay average of write counts or an average of elapsed times of write cycles. The controller also: determines whether the write frequency ranking is greater than a lowest write frequency ranking of logical addresses of the first memory; and if the write frequency ranking of the first logical address is greater, maps the logical address with the lowest write frequency ranking in the first memory to the second memory.

Abstract: A method of collecting garbage blocks in a solid state drive includes collecting a garbage block of a multiple level cell flash memory, selecting a spare block as a target block, copying effective data of the garbage block to a physical cell of the target block, searching for unprogrammed physical pages of the physical cell of the target block, using dummy data to complete programming of the unprogrammed physical pages of the physical cell, deleting the effective data in the garbage block, and recycling the garbage block to be a new spare block.

Abstract: In a GC processing in which a memory area is managed by being divided, collection efficiency of an area is further optimized. In order to realize the technology, a calculator including an arithmetic unit and a memory includes a storage unit which stores reference source information of data which is stored in a plurality of storage areas which are allocated to the memory in each of the storage areas; and a control unit which determines a storage area in which updated reference source information is different from reference source information which is recorded in the storage unit to be an area as a release target.

Abstract: Certain example embodiments relate to memory management techniques that enable users to “pin” elements to particular storage tiers (e.g., RAM, SSD, HDD, tape, or the like). Once pinned, elements are not moved from tier-to-tier during application execution. A memory manager, working with at least one processor, receives requests to store and retrieve data during application execution. Each request is handled using a non-transitory computer readable storage medium (rather than a transitory computer readable storage medium), if the associated data is part of a data cache that is pinned to the non-transitory computer readable storage medium, or if the associated data itself is pinned to the non-transitory computer readable storage medium. If neither condition applies, the memory manager determines which one of the non-transitory and the transitory computer readable storage mediums should be used in handling the respective received request, and handles the request accordingly.

Abstract: A receiving controller which receives a read request out of first and second storage controllers transfers the read request to an associated controller which is associated with a read source storage area out of the first and second storage controllers when the receiving controller is not the associated controller. It is however the receiving controller that reads the read-target data from a read source storage device, writes the read-target data to a cache memory of the receiving controller, and transmits the read-target data written in the cache memory of the receiving controller to a host apparatus.

Abstract: A coordinating node acts as a write back cache, isolating local cache storage endpoints from latencies associated with accessing geographically remote cloud cache and storage resources.

Abstract: A coordinating node creates virtual storage from a hierarchy of local and remote cache storage resources by maintaining global logical block address (LBA) metadata maps. A size of the metadata maps at each level of the hierarchy is independent of an amount of data allocated to a respective cache store at each level.

Abstract: A coordinating node maintains globally consistent logical block address (LBA) metadata for a hierarchy of caches, which may be implemented in local and cloud based storage resources. Associated storage endpoints initially determine a hash associated with each access request, but forward the access request to the coordinating node to determine a unique discriminator for each hash.

Abstract: A cache memory that selectively enables and disables speculative reads from system memory is disclosed. The cache memory may include a plurality of partitions, and a plurality of registers. Each register may be configured to stored data indicative of a source of returned data for previous requests directed to a corresponding partition. Circuitry may be configured to receive a request for data to a given partition. The circuitry may be further configured to read contents of a register corresponding to the given partition, and initiate a speculative read dependent upon the contents of the register.