Abstract: A monitoring target apparatus connected to a plurality of monitoring manager apparatuses is characterized in that the monitoring target apparatus includes, in a memory, a monitoring agent for collecting monitoring information from monitoring target resources among resources constituting the monitoring target apparatus; and monitoring condition management information that defines an event issuance condition for each type of the monitoring target resources; wherein the monitoring agent judges whether to issue an event or not, based on the monitoring information and the monitoring condition management information; and if the monitoring agent issues the event, it transmits the issued event to all the plurality of monitoring manager apparatuses.

Abstract: A race condition in a workflow representation is detected and corrected. First and second contracts are retrieved for respective first and second analytics of the workflow representation, wherein the contracts specify input types and output types of their analytics. Both contracts include information required to execute their respective analytics by a workflow executor. It is determined that the output type of the first analytic matches the input type of the second analytic based on a comparison of the first contract and the second contract, and that the workflow representation does not include a directed edge connecting the first analytic to the second analytic. The inclusion of a directed edge in the workflow representation connecting the first analytic to the second analytic will correct the race condition in the workflow representation.

Abstract: A unit test coverage report system and method may generate a coverage report to indicate the success or failure of current unit tests and the amount of further testing that is required to fully test an application undergoing development. The system or method may receive a source code file including a plurality of source code units, wherein each source code unit corresponds to one of a plurality of comments sections. The system or method may then parse the plurality of comments sections and extract an identification of each source code unit from the plurality of comments sections. The identification may then be compared to a list of tested source code units and the comparison added to a unit test coverage report.

Abstract: Described herein is a technology for a dashboard used for visualizing data. In some implementations, a dashboard with one or more dashboard item is provided. Performance of the dashboard is evaluated to determine a load time of the dashboard. Possible suggestions for improving performance of the dashboard are provided if performance issues are determined from evaluating performance of the dashboard.

Abstract: A system and computer-implemented method for determining a runtime of a thread of an application. Synchronization events for a first thread of an application executing on the computer system are received, the synchronization events including at least a first synchronization event and a second synchronization event for the first thread. A first difference between a synchronization event timestamp of the first synchronization event and the synchronization event timestamp of the second synchronization event is calculated. A second difference between an accumulated timestamp of the first synchronization event and the accumulated timestamp of the second synchronization event is calculated. A runtime of the first thread of the application is calculated as a difference between the first difference and the second difference.

Abstract: A method for diagnosing an error associated with a software is provided. The method may include receiving a stack trace associated with the error. The method may also include fetching a source code associated with the received stack trace. The method may further include parsing the fetched source code associated with the received stack trace. The method may also include generating an abstract syntax tree (AST) based on the parsed fetched source code. Additionally, the method may include inserting at least one logging call into the generated abstract tree. The method may include recompiling the captured code based on the generated abstract tree with the at least one inserted logging call. The method may also include uploading the recompiled code onto at least one deployment server.

Abstract: Disclosed are methods for finding all valid paths in a COBOL program. These methods are performed in polynomial time, allowing them to be scaled to accommodate large COBOL programs. As the methods find all valid paths in COBOL program code, by traversing and marking the nodes of the program upon being traversed. Accordingly, all usable and reachable code is indicated and marked. This increases safety when working with the code, as removal or alteration of such valid code is indicated, and thus, made unlikely.

Abstract: Embodiments of the invention relate to modifying run-time-instrumentation controls (MRIC) from a lesser-privileged state. The MRIC instruction is fetched. The MRIC instruction includes the address of a run-time-instrumentation control block (RICCB). The RICCB is fetched based on the address included in the MRIC instruction. The RICCB includes values for modifying a subset of the processor's run-time-instrumentation controls. The subset of run-time-instrumentation controls includes a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location. The RIB holds run-time-instrumentation information of the events recognized by the processor during program execution. The values of the RICCB are loaded into the run-time-instrumentation controls. Event information is provided to the RIB based on the values that were loaded in the run-time-instrumentation control.

Abstract: Aspects relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor.

Abstract: Various embodiments for hit testing of visual objects are described herein. Data of visual objects is generated in a two-dimensional clip space. The data of visual objects includes two-dimensional projections of the visual objects. Cursor coordinates are transformed into the clip space and bounding box calculations are performed using the transformed cursor coordinates and the generated data. Hit testing is performed when there is a hit on a bounding box of at least one of the visual objects in the clip space. The hit testing is performed in a three-dimensional space. A result is then presented on a user interface based on the hit testing.

Abstract: A method for producing regulatory-compliant software includes validating a software application and freezing the validated software application in a validation portal, proving-in an infrastructure on which the software application operates, and providing evidence of operational change management for a regulatory agency, which evidence comprises documentation that satisfies the agency's compliance rules. A regulatory-compliant software package is also described.

Abstract: A testing device for evaluating operations of software installed in a mobile terminal includes a scenario selecting unit configured to select a scenario that includes information for causing the mobile terminal to execute a function that should be operated by the mobile terminal, a scenario execution determining unit configured to determine whether the scenario selected by the scenario selecting unit is executable, a scenario execution unit configured to execute the scenario determined to be executable by the scenario execution determining unit, and a scenario execution result determining unit configured to determine whether an execution result of the scenario executed by the scenario execution unit is the same as a result expected beforehand. The scenario execution determining unit determines whether the scenario selected by the scenario selecting unit is executable based on the execution result of the scenario executed by the scenario execution unit in the past.

Abstract: This disclosure relates to systems and methods for generating test cases. In one embodiment, a method is provided that may include identifying, by a computer including one or more processors, a first test event associated with a first user interaction with a first test device. The first user interaction may include interaction with a first display displaying a plurality of applications on the first test device. The method may also include determining, by the computer, at least one first view in which the first test event occurs. Furthermore, the method may include determining, based at least in part on the first test event, a first state of the first test device. Additionally, the method may include storing information about the first test event, the at least one first view, and the first state of the first test device in a first test case.

Abstract: A method and system for test automation framework for backup and recovery applications is described. Initial data states are prepared for corresponding system components for a test host. A backup and recovery application is executed to store backup copies corresponding to the system components to a storage device. The initial data states are modified to modified data states corresponding to the system components. The backup and recovery application is executed to recover the backup copies from the storage device. The test host is rebooted based on recovering the backup copies. A comparison is output, via an output device, of the system components in the test host to the initial data states.

Abstract: A method and system for re-ordering bits in a memory system is disclosed. The memory system includes a system on a chip (SoC) coupled to a plurality of memory chips. Each of the memory chips including a memory array, multipurpose registers (MPRs) coupled to the memory array; and a data bus coupled between the SoC and the memory array. The method and system comprise utilizing the MPRs within each of the plurality of memory chips to determine bit ordering within each byte lane of memory array of the associated memory chip. The method and system further includes providing the determined bit ordering to the SoC.

Abstract: Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.

Abstract: The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes mapping a data pattern to a number of program state combinations L corresponding to a group of memory cells configured to store a fractional number of data units per cell. The mapping can be based, at least partially, on a recursive expression performed in a number of operations, the number of operations based on a number of memory cells N within the group of memory cells and the number of program state combinations L.

Abstract: The present invention provides a system and method for virtual block numbers (VBNs) to disk block number (DBN) mapping that may be utilized for both single and/or multiple parity based redundancy systems. Following parity redistribution, new VBNs are assigned to disk blocks in the newly added disk and disk blocks previously occupied by parity may be moved to the new disk.

Abstract: A technique reclaims memory pages in a virtualization platform. The technique involves receiving, by a virtual machine of the virtualization platform, an inflate command which directs a balloon driver of the virtual machine to inflate. The technique further involves issuing, by the virtual machine and in response to the inflate command, a sweep request to a hypervisor. The sweep request directs the hypervisor to (i) perform a scan of memory pages allocated to the virtual machine for a predetermined pattern of characters, (ii) de-allocate memory pages having the predetermined pattern of characters from the virtual machine (e.g., zeroed pages), the de-allocated memory pages including super pages and regular pages, and (iii) update a list of memory page mappings to reflect the de-allocated memory pages. The technique further involves completing balloon driver inflation after the list of memory page mappings is updated.

Abstract: A block grouping method includes the following steps. Firstly, a link list is established. In the link list, plural blocks are classified into plural groups according to valid data counts of respective blocks. If a host refreshes a stored data of a flash memory of the solid state drive or adds a new data into the flash memory, the valid data count of the block corresponding to the refreshed data or the new data is changed, and the link list is updated according to the changed valid data count of the block. After the garbage collection is started by the solid state drive, the block to be subject to the garbage collection is selected according to the link list, and the garbage collection is performed.

Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units, and a memory control circuit unit and the memory storage apparatus are provided. The method includes grouping the physical erasing units into at least a data area, a backup area and a spare area; and setting a value obtained by summing a minimum threshold and a predetermined number as a garbage collecting threshold. The data writing method also includes getting at least one physical erasing unit from the spare area, writing data into the gotten physical erasing unit, associating the gotten physical erasing unit with the backup area and re-adjusting the garbage collecting threshold according to the number of physical erasing units associated with the backup area and the minimum threshold.

Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.

Abstract: A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area.

Abstract: For semiconductor memory garbage collection, an identification module identifies a garbage collection time window for at least one block of a flash memory array. A garbage collection module garbage collects a first block of the flash memory array with a highest garbage collection level and an open garbage collection time window.

Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. This allows the memory system to both store and read data in the same cycle with no conflicts.

Abstract: A technique of operating a data processing system, includes logging addresses for cache lines modified by a producer core in a data array of a producer cache to create a high-availability (HA) log for the producer core. The technique also includes moving the HA log directly from the producer cache to a consumer cache of a consumer core and moving HA data associated with the addresses of the HA log directly from the producer cache to the consumer cache. The HA log corresponds to a cache line that includes multiple of the addresses. Finally, the technique includes processing, by the consumer core, the HA log and the HA data for the data processing system.

Abstract: A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

Abstract: A method and a system to dynamically determine how much of the total IO bandwidth may be used for flushing dirty metadata from the cache to the main memory without increasing the host memory access latency time, includes increasing the number of IO processes by adding a number of IO processes at short intervals and measuring host latency. If the host latency is acceptable, then increasing the number of IO processes again by the same number, and repeating until the host latency period reaches a limit. When the limit has been reached, reducing the number of IO processes by a multiplicative factor, and repeating the additive process from the reduced number of IO processes. The number of IO processes used for flushing dirty metadata may resemble a series of saw teeth, rising gradually and declining rapidly in response to the number of host IO processes needed.

Abstract: A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.

Abstract: A technique manages data within a data storage apparatus having a cache of volatile memory and non-volatile storage. The technique involves receiving a set of write commands to write data to the non-volatile storage. The technique further involves acknowledging, in a write-back caching manner, completion of the set of write commands after the data reaches the cache of volatile memory and prior to the data reaching the non-volatile storage. The data includes host data as well as critical metadata. The technique further involves saving, after acknowledging completion of the set of write commands, the data from the cache of volatile memory to the non-volatile storage, the critical metadata being saved from the cache of volatile memory to the non-volatile storage at a quicker rate than that of the host data (i.e., accelerated synchronization of the critical metadata).

Abstract: An information processing system and computer program storage product for managing objects stored in a shared memory cache. The system includes at least a plurality of cache readers accessing data from the shared memory cache. The system updates data in the shared memory cache using a cache writer. The system maintains a cache replacement process collocated with a cache writer. The cache replacement process makes a plurality of decisions on objects to store in the shared memory cache. Each of the plurality of cache readers maintains information on frequencies with which it accesses cached objects. Each of the plurality of cache readers communicates the maintained information to the cache replacement process. The cache replacement process uses the communicated information on frequencies to make at least one decision on replacing at least one object currently stored in the shared memory cache.

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract: A combination of a host system and a storage system is disclosed that facilitates improved responsiveness of the host system to user requests. In one embodiment, the host system includes a cache management module, a partitioning module, and a driver. The cache management module determines write data to cache to a dedicated zone of a hard disk media of the storage system. The partitioning module partitions the hard disk media into one partition including the dedicated zone and another partition not including the dedicated zone. The driver transmits storage access commands to the storage system to cache data in and retrieve cached data from the one partition. Thereby, the host system can access the write data from the hard disk media more quickly than if the write data were cached in and accessed from another zone of the hard disk media.

Abstract: A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.

Abstract: A system and method for adaptive data prefetching in a processor enables adaptive modification of parameters associated with a prefetch operation. A stride pattern in successive addresses of a memory operation may be detected, including determining a stride length (L). Prefetching of memory operations may be based on a prefetch address determined from a base memory address, the stride length L, and a prefetch distance (D). A number of prefetch misses may be counted at a miss prefetch count (C). Based on the value of the miss prefetch count C, the prefetch distance D may be modified. As a result of adaptive modification of the prefetch distance D, an improved rate of cache hits may be realized.

Abstract: A procedure, which is performed by a processor of a variable updating device, includes: (a) judging whether or not the cache set is a cache set selected in advance; (b) in a case in which the corresponding cache set is judged to be the cache set selected in advance, judging which of (1) a hit and (2) a miss has occurred; and (c) carrying out a first processing that, in a case in which it is judged that the miss has occurred, updates a miss variable that expresses a number of times that misses have occurred and stores the address information in the storage portion, and a second processing that, in a case in which it is judged that the hit has occurred, updates a hit variable that expresses a number of times that hits have occurred.

Abstract: An apparatus may include a first memory, a control circuit, a first address comparator and a second address comparator. The first memory may store a table, which may include an expected address of a next memory access and an offset to increment a value of the expected address. The control circuit may read data at a predicted address in a second memory and store the read data in a cache. The first and second address comparators may determine if a value of a received address is between the value of the expected address and the value of the expected address minus a value of the offset. The control circuit may also modify the value of the offset responsive to determining the value of the received address is between the value of the expected address and the value of the expected address minus the value of the offset.

Abstract: The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.

Abstract: Methods and structure are provided for rebuilding cache data from a failed cache device based on tracking data for the failed cache device. The system includes a memory and a cache manager. The memory stores tracking data that correlates entries at a cache with logical block addresses of a logical volume. The cache manager is able to determine that a device implementing the cache has failed and to analyze the tracking data to identify logical block addresses correlated with cache entries from the failed cache device. The cache manager is further able to generate new cache entries at a new cache device, and to populate the new cache entries with data from the identified logical block addresses.

Abstract: A memory system having increased throughput is disclosed. Specifically, the memory system includes a first level write combining queue that reduces the number of data transfers between a level one cache and a level two cache. In addition, a second level write merging buffer can further reduce the number of data transfers within the memory system. The first level write combining queue receives data from the level one cache. The second level write merging buffer receives data from the first level write combining queue. The level two cache receives data from both the first level write combining queue and the second level write merging buffer. Specifically, the first level write combining queue combines multiple store transactions from the load store units to associated addresses. In addition, the second level write merging buffer merges data from the first level write combining queue.

Abstract: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.

Abstract: In order to optimize efficiency of deserialization, a serialization cache is maintained at an object server. The serialization cache is maintained in conjunction with an object cache and stores serialized forms of objects cached within the object cache. When an inbound request is received, a serialized object received in the request is compared to the serialization cache. If the serialized byte stream is present in the serialization cache, then the equivalent object is retrieved from the object cache, thereby avoiding deserialization of the received serialized object. If the serialized byte stream is not present in the serialization cache, then the serialized byte stream is deserialized, the deserialized object is cached in the object cache, and the serialized object is cached in the serialization cache.

Abstract: The present invention relates to a method of optimizing the provisioning of a bootable image onto a storage device. In some embodiments, a host device executes a provisioning application to image a storage drive as a bootable drive. During the provisioning process, the storage device is configured to disguise its use of write caching during the provisioning process. In one embodiment, the storage device is configured to suppress forced unit access commands and cache flush commands for the provisioning application. In another embodiment, the storage device is configured to reject forced unit access commands. The storage device may disguise its use of write caching based on various criteria, such as a length of time, a counter, and the like.

Abstract: A portable electronic device may be rebranded, this rebranding may cause a plurality of data files in a user memory partition on the portable electronic device to be deleted when the device is returned to factory settings or otherwise wiped during the rebranding. Rebranding may be desirable in order for the user to receive better and/or more cost-effective services from a telecommunications service provider. Therefore, a user may want to rebrand their device without losing the data in the user memory partition. The user may specify or configure the device to copy or move the plurality of data to a carrier memory partition or a system memory partition on the device, or to a remote server, or to a removable memory such as an SD card.

Abstract: A storage system comprises a cache for caching data blocks and storage devices for storing blocks. A storage operating system may deduplicate sets of redundant blocks on the storage devices based on a deduplication requirement. Blocks in cache are typically deduplicated based on the deduplication on the storage devices. Sets of redundant blocks that have not met the deduplication requirement for storage devices and have not been deduplicated on the storage devices and cache are targeted for further deduplication processing. Sets of redundant blocks may be further deduplicated based on their popularity (number of accesses) in cache. If a set of redundant blocks in cache is determined to have a combined number of accesses being greater than a predetermined threshold number of accesses, the set of redundant blocks is determined to be “popular.” Popular sets of redundant blocks are selected for deduplication in cache and the storage devices.

Abstract: A processor, operable in a computing storage environment, allocates portions of a Scatter Index Table (SIT) disproportionately between a larger portion dedicated for meta data tracks, and a smaller portion dedicated for user data tracks, and processes a storage operation through the disproportionately allocated portions of the SIT using an allocated number of Task Control Blocks (TCB).

Abstract: A host selects a memory page that has been allocated to a guest for eviction. The host may be a host machine that hosts a plurality of virtual machines. The host accesses a bitmap maintained by the guest to determine a state of a bit in the bitmap associated with the memory page. The host determines whether content of the memory page is to be preserved based on the state of the bit. In response to determining that the content of the memory page is not to be preserved, the host discards the content of the memory page.

Abstract: Data processing methods and apparatus for efficiently storing and retrieving data, e.g., blocks of data, to and from memory. The data processing includes, e.g., techniques such as using linked lists and/or tables for tracking duplicate data blocks received for storage, the use of lossless data compression, and de-duplication based on comparing hash values, compressed data block sizes, and/or bit by bit comparisons of the block of data to be stored and previously stored blocks of data.

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated.

Abstract: A system and method for managing a data cache in a central processing unit (CPU) of a database system. A method executed by a system includes the processing steps of adding an ID of a page p into a page holder queue of the data cache, executing a memory barrier store-load operation on the CPU, and looking-up page p in the data cache based on the ID of the page p in the page holder queue. The method further includes the steps of, if page p is found, accessing the page p from the data cache, and adding the ID of the page p into a least-recently-used queue.