Abstract: A device comprises at the input a first component (PA) having a first output impedance (Z1), at the output a second component (ANT) having a second input impedance (Z2), and an impedance-matching network between said first and second components. Because the first and/or the second impedance vary/varies, said impedance-matching network comprises a filter (Fadp), with an impedance that is matchable to the first and second impedances, located between said first and second components and comprising at least two acoustic wave coupled resonators. At least one of the resonators comprises a perovskite type material and means for applying a voltage to said resonator, which enable the permittivity and the impedance thereof to be varied.

Abstract: A method and system for providing a surface acoustic wave band reject filter are disclosed. According to one aspect, a surface acoustic wave band reject filter includes a substrate having electrode bars and bonding pads formed on the substrate. The filter further includes at least one die having a side facing the substrate. A plurality of surface acoustic wave resonators are formed on the at least one die formed on the substrate. Solder balls formed on a side of the at least one die facing the substrate are positioned to engage bonding pads on the substrate. The plurality of surface acoustic wave resonators collectively exhibit a band reject filter response.

Abstract: A filter device for filtering signals via a pass-band includes series resonators connected in series between an input terminal and an output terminal, each of the series resonators having a corresponding parallel resonance frequency Fp and series resonance frequency Fs, and shunt resonators respectively connected between at least one of the series resonators and a ground voltage, each of the shunt resonators having a corresponding parallel resonance frequency Fp and series resonance frequency Fs. At least one series resonator has a corresponding series resonance frequency Fs outside the pass-band of the filter device, and at least one other series resonator has a corresponding series resonance frequency Fs inside the pass-band, and/or at least one shunt resonator has a corresponding parallel resonance frequency Fp outside the pass-band of the filter device, and at least one other shunt resonator has a corresponding parallel resonance frequency Fp inside the pass-band.

Abstract: A digital filter circuit and a digital filter control method are capable of reducing circuit scale and power consumption for filter processing in a frequency domain such as an overlap FDE method.

Abstract: In accordance with an embodiment, a switchable capacitance circuit includes a plurality of capacitance-switch cells that each has a first semiconductor switching circuit and a capacitance circuit having a first terminal coupled to the first semiconductor switching circuit. A resistance of the first semiconductor switching circuit of a first switch-capacitance cell of the plurality of capacitance-switch cells is within a first tolerance of a resistance of the first semiconductor switching circuit of a second capacitance-switch cell of the plurality of capacitance-switch cells, and a capacitance of the capacitance circuit of the first capacitance-switch cell is within a second tolerance of a capacitance of the capacitance circuit of the second capacitance-switch cell.

Abstract: A method and a circuit system for actuating a number of modules. The method is carried out using the circuit system, which implements a flexible trigger mechanism.

Abstract: The present invention is directed to solve a problem that, in a semiconductor device capable of generating a clock signal by coupling a quartz oscillator to an external terminal to which an I/O port is coupled, leak current of the I/O port which is in the inactive state disturbs activation of a clock. The semiconductor device has a first terminal, an amplification circuit coupled to the first terminal, and an output buffer whose output terminal is coupled to the first terminal. The output buffer has first and second transistors of a first conduction type coupled in series via a first node between a first power supply line and an output terminal, and the conduction states of the first and second transistors of the first conduction state are controlled in response to a first control signal which is applied commonly to the gate of each of the first and second transistors.

Abstract: A clock control circuit includes: a first buffer that receives a first pair of input clocks of multi-phase clocks, buffers and outputs the first pair of input clocks; a second buffer that receives a second pair of input clocks of the multi-phase clocks, and is controllable to buffer and output the second pair of input clocks or to output a fixed level; and a frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clocks, the first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the multi-phase clocks.

Abstract: The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.

Abstract: A master-slave flip-flop implemented in an integrated circuit comprises a master latch coupled to receive data at an input; and a slave latch coupled to an output of the master latch, wherein the slave latch comprises an SEU-enhanced latch, and the master latch is not enhanced for SEU protection. A method of implementing a master-slave flip-flop in an integrated circuit is also described.

Abstract: An integrated circuit including a processor configured to operate off a supply voltage being applied at one of a plurality of external pins; and internal input/output circuitry configured to select between the supply voltage and at least one other supply voltage being applied at another of the plurality of external pins.

Abstract: A dielectric-based nonlinear transmission line (NLTL) coupled to an adjacent waveguide. Energy in an input pulse to the nonlinear transmission line is concentrated into an electromagnetic shock or a series of soliton-like oscillations by the nonlinear properties of the NLTL. Energy from the electromagnetic shock or the soliton-like oscillations are transferred into the waveguide. A plate of the NLTL coupled to the waveguide can include an aperture or a series of apertures. Energy from the electromagnetic shock or the soliton-like oscillations can then be transferred into waveguide via an aperture or apertures in such a way that forward and/or backward guided electromagnetic waves are generated in the waveguide. The waveguide can contain at a nonlinear magnetic material, a dielectric material, a slow wave structure, or a metamaterial. The NLTL can include nonlinear dielectric elements such as a periodic array interspersed with linear dielectric elements.

Abstract: A device comprising a clock circuit, a control circuit, and a current mode logic (CML) circuit is disclosed. The clock circuit provides a first differential clock signal and the control circuit generates a control signal based at least in part on the frequency of the first differential clock signal. The CML circuit generates a second differential clock signal based at least in part on the first differential clock signal. The CML circuit operates in one of a plurality of different frequency modes based at least in part on the control signal and includes a number of variable resistors that are responsive to the control signal.

Abstract: A circuit for generating a oscillating with a selectable frequency, comprises a delay generator configured to identify a first time instant, the first time instant being delayed with respect to a signal edge of a clock signal oscillating with a predetermined clock frequency. A delay element is configured to provide a signal edge, the signal edge being delayed with respect to the first time instant such that the signal edge is provided at a second time instant corresponding to a signal edge of the synthesized signal.

Abstract: Provided is a metal-insulator transition (MIT) transistor system including an MIT critical current supply device allowing MIT to occur between a control terminal and an outlet terminal of an MIT transistor for easily and conveniently driving the MIT transistor. A current supplier according to the present invention provides a critical current for allowing an MIT phenomenon to occur between the control terminal and the output terminal of the MIT transistor.

Abstract: A circuit includes a transformer having a first winding and a second winding, an input connected to a first terminal of the first winding, a first power transistor and a second power transistor. The first power transistor has a source, a gate, and a drain connected to a second terminal of the first winding. The second power transistor has a source connected to ground, a gate connected to a pulsed voltage drive source and a drain connected to the source of the first power transistor. The gate of the first power transistor is connected to a DC source or the same pulsed voltage drive source as the gate of the second power transistor. The first power transistor actively turns off independent of load current. Other circuit embodiments and corresponding load switching methods are also provided.

Abstract: Disclosed herein are an apparatus and a method for guiding a multi-function switch guide. The apparatus for guiding a multi-function switch includes: a sensor unit that is disposed on an operating lever of a multi-function switch of a vehicle to sense an approach of a user or an operation of the operating lever; a switch state determining unit that determines a current operation state of the multi-function switch, when the approach of the user or the operation of the operating lever is sensed by the sensor unit; an information detection unit that detects a lever operation method corresponding to the current operation state of the multi-function switch; and an output control unit that performs a control to display the detected lever operation method.

Abstract: An electrode unit on a touch-sensing element includes a first electrode and a second electrode. The first electrode includes a first conductive element; and a plurality of second conductive elements extending from the first conductive element in directions in parallel with a first direction within a specific range. The second electrode includes a third conductive element and a plurality of fourth conductive elements extending from the third conductive element in directions in parallel with a second direction within a specific range.

Abstract: Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest.

Abstract: A multiplexer tree operable to control an output a sequence of data stored in a plurality of storage units in accordance with a non-linear address sequence that has less bit transition counts than a linear address sequence. The non-linear address sequence is provided to the selection inputs of the multiplexer tree and causes the levels having greater numbers of multiplexers to toggle less frequently than the levels having smaller numbers of multiplexers. The non-linear address sequence may comprise a Gray code sequence where every two adjacent addresses differ by a single bit. The non-linear address sequence may be optimized to minimize transistor switching in the multiplexer tree.

Abstract: A method of reducing power consumption caused by leakage current in an interface circuit between modules that are driven by different power sources is disclosed. The interface circuit includes an output driver that operates by a first power supply voltage in a first mode and does not operate in a second mode in which the first power supply voltage is prevented from being applied, an input buffer that is operated by a second power supply voltage in the first and second modes, and a transmission line that connects an output terminal of the output driver to an input terminal of the input buffer. The interface circuit further includes a current leakage prevention circuit that prevents, in the second mode, a current leakage in the input buffer between a second power supply voltage source that supplies the second power supply voltage and a ground voltage source.

Abstract: A resistor renormalization method for a source driving circuit is provided, wherein the source driving circuit includes a plurality of resistors coupled in series, and the resistors respectively have a resistance and correspond to a number section value. The resistor renormalization method includes the steps of: (A) adding the resistances of the resistors to generate a total resistance; (B) providing a radix, wherein the radix is a natural number; (C) dividing the total resistance by the radix to generate a calculated section value; (D) dividing the resistances of the resistors by the radix to generate a plurality of remainders, respectively, and adding the remainders to generate an accumulated remainder; and (E) setting the number section value and the resistance of each resistor according to a relation between the calculated section value and the number section value and a relation between the remainder of each resistor and the radix.

Abstract: An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.

Abstract: A method for enabling double pumping in a limited switch dynamic logic circuit includes precharging a dynamic node in accordance with a first clock signal and a second clock signal. The dynamic node is evaluated to a first value in response to one or more first input signals of a first evaluation tree in accordance with the first clock signal. The dynamic node is evaluated to a second value in response to one or more second input signals of a second evaluation tree in accordance with the second clock signal.

Abstract: An oscillator includes a voltage controlled oscillator, a PLL circuit, a crystal unit and an oscillator circuit configured to generate a clock, a digital control circuit, and a clock switching unit. The digital control circuit is configured to set an oscillation parameter of the oscillator circuit, and a parameter of the PLL circuit. The clock switching unit is configured to supply an output signal of the voltage controlled oscillator to the digital control circuit as a clock signal so as to cause the digital control circuit to operate using the clock signal when powered on, and configured to supply an output signal of the oscillator circuit to the digital control circuit as a clock signal after the digital control circuit sets the oscillation parameter of the oscillator circuit. An initial voltage is supplied to the voltage controlled oscillator as a control voltage when the oscillator is powered on.

Abstract: A highly integrated monolithic self-compensated oscillator (SCO) with high frequency stability versus temperature variations is described, together with a cost effective single insertion point trimming (SPT) algorithm. The SPT is utilized to adjust the phase and frequency of the SCO to meet frequency stability versus temperature and frequency accuracy requirements for a reference clock. The techniques used in the SPT algorithm provide a robust, fast and low testing cost for the SCO. Moreover, the concepts and techniques utilized in the SCO SPT can be used effectively for any temperature compensated oscillator (TCO) including TCXO, MEMS, FBAR and RC oscillators. Additionally, the described SPT algorithm is capable of measuring the temperature sensitivity of any oscillator, estimating suitable temperature compensation parameters and adjusting the oscillator frequency to the required value simultaneously.

Abstract: In some embodiments, disclosed is an AC amplitude detector to compare the magnitude of an AC signal against a detector threshold level and to provide an indication as to whether the AC magnitude is larger or smaller than the detector threshold level.

Abstract: Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract: A circuit includes first and second capacitances arranged on a first path that connects first and second terminals; a first switch arranged between the first capacitance and the second capacitance; a second switch arranged on a second path that connects a reference voltage section and a first node formed between the first capacitance and the first switch; a third switch arranged on a third path that connects the section and a second node formed between the second capacitance and the first switch; a first resistance arranged on a fourth path that connects the first node and a third node formed between the first terminal and the first capacitance; a second resistance arranged on a fifth path that connects the second node and a fourth node formed between the second terminal and the second capacitance; a fourth switch on the fourth path; and a fifth switch on the fifth path.

Abstract: A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

Abstract: Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.

Abstract: Provided herein are apparatus and methods for fast charge pump holdover on signal interruption. In certain configurations, a clock generator system includes a phase-locked loop (PLL), a fast detect circuit, and a switch electrically coupled to an input of the PLL's loop filter. The fast detect circuit relatively quickly detects when an input signal to the PLL is lost. The fast detect circuit can quickly detect the loss of phase lock and can place the PLL into a holdover such that the frequency of a clock signal generated by the PLL remains within an acceptable range.

Abstract: A radio apparatus includes a first receiver that is a processing unit for amplifying and frequency converting a radio signal received via an antenna, thereby outputting an IF signal; a detector unit for detecting a preamble signal from the IF signal; a second receiver for amplifying and quadrature demodulating the radio signal, thereby generating an I-signal and a Q-signal; a demodulator unit for demodulating the I-signal and Q-signal to generate a data signal; and a control unit for halting the operation of the first receiver and further activating the second receiver when the detector unit detects the preamble signal and for activating the first receiver and halting the operation of the second receiver when the demodulator unit completes the demodulation of the I-signal and Q-signal.

Abstract: Embodiments of a pipeline analog-to-digital converter is provided. In accordance with some embodiments, a pipeline analog-to-digital converter includes a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified residual voltage; a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and a digital correction circuit that corrects the digitized residual according to which zone the digitized residual is found.

Abstract: A bandwidth estimator circuit for an analog to digital converter. The bandwidth estimator computes a bandwidth estimate of an analog signal and includes: an amplitude averaging block configured to determine an average change in amplitude of N samples, a delta time block configured to determine a minimum time difference; a peak voltage block configured to determine the maximum magnitude; a peak to root mean square block configured to determine a ratio of a peak voltage to the root mean square of the magnitude; a bandwidth estimator block configured to compute a product of a ratio of the average change in amplitude to the minimum time difference, multiplied by a ratio of the peak voltage to the root mean square, squared, to the peak voltage multiplied by a constant; and a parameter adjustment circuit configured to modify sampler parameters controlling an analog signal sampling rate. Methods are described.

Abstract: A measurement circuit is provided for measuring the resistance of a variable resistance element biased with an external voltage supply. The measurement circuit includes an analog-to-digital converter (ADC) and a reference generator connected with the ADC. The ADC is operative to receive a reference voltage and a first voltage developed across the variable resistance element, and to generate a digital output signal indicative of a relationship between the first voltage and the reference voltage. The reference generator is operative to generate the reference voltage as a function of the external voltage supply.

Abstract: A system and method are provided for calibrating timing mismatch in an n-path time interleaved analog-to-digital converter (ADC). The method digitizes an analog signal with an n-path interleaved ADC, creating an interleaved ADC signal. In a first process, the phase of the interleaved ADC signal is rotated by 90 degrees, creating a rotated signal. This rotation may be accomplished using a finite impulse response (FIR) filter with taps at {0.5, 0, ?0.5}, enabled as a derivative filter, or as a Hilbert transformation. In a parallel second process, the interleaved ADC signal is delayed, creating a delayed signal. The rotated signal is multiplied by the delayed signal to create a timing error signal. Using the timing error signal, timing errors are accumulated for the ADC signal paths, and corrections are applied that minimize timing errors in each of the n ADC signal paths.

Abstract: A method of providing a wide range of input currents for an analog to digital converter (ADC), the method constituted of: receiving an input current; selecting one of a plurality of selectable ratios; and generating at least one sense current, the magnitudes of the at least one generated sense current and the received input current exhibiting the selected ratio, wherein the ADC is arranged to receive a voltage representation of the at least one generated sense current.

Abstract: Provided is an integrating analog-digital converter. According to the present examples, the resistance against external noise is improved by incorporating a differential amplifier into an integrating analog-digital converter. Some examples also include a section where an input voltage and a reference voltage are simultaneously blocked such that switching noise may be minimized and a reference voltage may also be stably supplied. Further, examples are designed to manage a residue, which may be generated when an integral operation to an analog input value is finished, to be processed not in an additional converter but in control logic itself, thereby reducing a size of a circuit device.

Abstract: An A/D converter includes a delta-sigma processing circuit for A/D conversion by delta-sigma modulation, and a cyclic processing circuit for A/D conversion by cyclic processing of amplification of a residue generated in the A/D conversion. The A/D converter further includes a quantization part for outputting a quantized value of quantized output of the delta-sigma processing circuit and a quantized output of the cyclic processing circuit, and a control circuit for generating an A/D conversion result and switching over a reference voltage based on the quantized value. The delta-sigma processing circuit and the cyclic processing circuit include a sampling capacitor, an integration capacitor and a capacitive D/A converter, which includes a DAC capacitor and add and subtract a charge corresponding to a reference voltage to and from a residue of quantization. The sampling capacitor, the DAC capacitor and the integration capacitor are provided as electrically separate capacitors.

Abstract: Embodiments of the present invention provide systems, methods, and computer storage media directed to hosting a plurality of copies of a digital content. A common component and one or more individual components from one or more copies of the digital content are generated. As such, the common component and the one or more individual components are stored, such that each individual component in conjunction with the common component represents a separate copy of the digital content. In some implementations, a compression ratio may be customized for determining the sizing of the common component and individual component.

Abstract: A hard-decision decoding method includes performing operations necessary for first updating of a check node while loading data, which is input to a decoder, to an input buffer; first updating the check node by using a result of the performing of the operations after storing data, corresponding to one codeword, to the input buffer; and performing low-density parity check (LDPC) decoding by using a result of the first updating of the check node.

Abstract: A method for implementing multi standard programmable low-density parity check decoder in a receiver is provided. The method includes (i) generating, by a control signal generation unit, pre computed control signals associated with a h-matrix, (ii) obtaining, by a control signal storage unit of a hardware decoder unit, the pre computed control signals associated with the h-matrix, (iii) obtaining, by a LLR memory fetch & data align unit, LLR bytes from a LLR memory unit, (iv) rotating, by a rotation and aligning unit, the LLR bytes to obtain aligned valid LLR bytes, (v) processing, by the processing element unit, the aligned valid LLR bytes to obtain an output data, and (vi) decoding, the h-matrix associated with at least one standard and code rates based on the pre computed control signals.

Abstract: A method for determining update candidates in a low-density parity-check decoding process includes dividing the quasi-cyclic columns into groups and identifying an update candidate in each group. One or more of the identified update candidates are then updated. In the first half of iterative process, the higher quality candidate is updated. In the second half of the iterative process, the lower quality candidate is updated.

Abstract: Improving decoding of a set of k data symbols received from several receivers, the data symbols being encoded by a systematic block error correcting code of dimension k and size n. The set of data symbols is received along with a corresponding subset of parity symbols, forming a partial data block comprising m symbols. A partial data block transmitted by one emitter, comprising a set of k data symbols and a subset of (m?k) parity symbols, is received from each receiver. For each received partial data block, a subset of parity symbols is generated and an item of reliability information is computed as a function of the received parity symbols and parity symbols generated from a received set of data symbols. The items of computed reliability information are compared with each other to select one received set of data bits.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. In one case a data processing system is disclosed that includes a decoder circuit operable to apply a low density parity check algorithm to a decoder input to yield an interim decoded output, where the decoder input is a codeword formed of two bit symbols, and where the decoder input is encoded to yield a last layer including at least two different entry values. In addition, the data processing system includes an inverse mapping circuit operable to remap the interim decoded output to yield an overall decoded output.

Abstract: A method for encoding includes receiving input data symbols to be encoded with an Error Correction Code (ECC) so as to produce a code word of the ECC including redundancy symbols. The input data symbols are applied first and second processing stages, such that the first processing stage performs a first polynomial division by a fixed-coefficient polynomial with a first degree of parallelism, and the second processing stage performs a second polynomial division by a configurable-coefficient polynomial with a second degree of parallelism that is smaller than the first degree of parallelism, so as to jointly produce the redundancy symbols.

Abstract: Techniques for optimizing data storage are disclosed herein. In particular, methods and systems for implementing redundancy encoding schemes with data storage systems are described. The redundancy encoding schemes may be scheduled according to system and data characteristics. The schemes may span multiple tiers or layers of a storage system. The schemes may be generated, for example, in accordance with a transaction rate requirement, a data durability requirement or in the context of the age of the stored data. The schemes may be designed to rectify entropy-related effects upon data storage. The schemes may include one or more erasure codes or erasure coding schemes. Additionally, methods and systems for improving and/or accounting for failure correlation of various components of the storage system, including that of storage devices such as hard disk drives, are described.

Abstract: Methods and arrangements for parallelizing turbo encoding computations. At least one processor is provided. Turbo encoding computations are split into first and second parts. Using at least one processor, the computations of the first part are performed. Thereafter, using the at least one processor, the computations of the second part are performed, the second part correcting output provided by the computations of the first part. One of the first and second parts comprises computations performed in parallel and the other of the first and second parts comprises computations performed not in parallel. Other variants and embodiments are broadly contemplated herein.

Abstract: A method of protecting data with application layer forward error correction in a communication system, wherein the communication system includes first devices with legacy receivers and second devices with FEC-enabled receivers, operation of the legacy receivers is not affected by the application layer forward error correction, and the method includes: determining a duration period; assembling packets of source data into source blocks corresponding to the duration period, each source block comprising a number of packets of source data; encoding the source blocks to generate encoded blocks, each encoded block comprising a number of packets of repair data; and transmitting the packets of repair data.