Abstract: A recovery manager discovers replication properties of datastores stored in a storage array, and assigns custom tags to the datastores indicating the discovered replication properties. A user may create storage profiles with rules using any combination of these custom tags describe replication properties. The recovery manager protects a storage profile using a policy-based protection mechanism. Whenever a new replicated datastore is provisioned, the datastore is dynamically tagged with the replication properties of their underlying storage, and will belong to one or more storage profiles. The recovery manager monitors storage profiles for new datastores and protects the newly provisioned datastore dynamically, including any or all of the VMs stored in the datastore.

Abstract: Unifying application log messages using runtime instrumentation includes capturing raw data associated as a log message from an application using an application monitoring module, determining if the raw data is to be filtered based on a filtering configuration, and constructing a log message based on the raw data. A system for unifying application log messages using runtime instrumentation includes a capture engine to capture raw data associated as a log message from an application using an application monitoring module, a determination engine to determine if the raw data is to be filtered based on a filtering configuration, a construction engine to construct a log message based on the raw data, and a log framework monitor engine to monitor an application program interface that invokes a writing action of the log message using at least one log framework to capture the log message in real time.

Abstract: A signal processing device includes at least one timestamp generation component arranged to generate at least one local timestamp value, and to provide the at least one local timestamp value to at least one data link layer module for timestamping of data packets. The signal processing device further includes at least one debug module arranged to receive the at least one local timestamp value and to timestamp debug information based at least partly on the at least one local timestamp value.

Abstract: In an embodiment, a method comprises using a first hub device: establishing one or more secure connections with one or more spoke devices logically arranged as spokes with respect to a data processing system; generating and sending via a high-speed link a hub probe to a second hub device; in response to determining that the second hub device is nonresponsive, transmitting, to the one or more spoke devices a first communication indicating that the second hub device is nonresponsive; using a spoke device, receiving the first communication indicating that the second hub device is nonresponsive; determining whether the spoke device has established a secure connection with the second hub device; in response to determining that the spoke device has established the secure connection with the second hub device, selecting a third hub device, establishing a secure connection with the third hub device, and communicating with the third hub device.

Abstract: The various embodiments described herein include methods and/or devices used to protect data in a storage device. In one aspect, a method includes performing a power fail operation on a first section of the storage device, the first section of the storage device comprising one or more memory group modules. The power fail operation includes supplying power, via one or more energy storage devices, to the one or more memory group modules, where each memory group module includes a respective memory group module controller. The power fail operation also includes supplying power, via an additional energy storage device, to a storage device controller, the storage device controller corresponding to the first section of the storage device. The additional energy storage device is distinct from the one or more energy storage devices and each are distinct from a power source used during normal operation of the storage device.

Abstract: This information processing apparatus includes a display processing unit to perform, on a display device, display for requesting a user to collectively input, for each of plural apparatuses whose activation or stop is to be controlled, a first time for causing a power-supply start to be delayed since a power feeding start or a second time for causing a power-supply stop to be delayed since a power failure, by an uninterruptible power supply that supplies power to the apparatus among one or more uninterruptible power supplies or by a power feeding management group in the uninterruptible power supply; and a setting unit to set, for each of the plural apparatuses, the inputted first time or second time for the uninterruptible power supply that supplies power to the apparatus, via a communication network.

Abstract: Various embodiments are generally directed to techniques for handling errors affecting the at least partially parallel performance of data access commands between nodes of a storage cluster system. An apparatus may include a processor component of a first node, an access component to perform a command received from a client device via a network to alter client device data stored in a first storage device coupled to the first node, a replication component to transmit a replica of the command to a second node via the network to enable performance of the replica by the second node at least partially in parallel, an error component to retry transmission of the replica based on a failure indicated by the second node and a status component to select a status indication to transmit to the client device based on the indication of failure and results of retrial of transmission of the replica.

Abstract: A method, non-transitory computer readable medium and host computing device that stores, by a first virtual storage controller, a plurality of received transactions in a transaction log in an in-memory storage device. The first virtual storage controller is monitored and a determination is made when a failure of the first virtual storage controller has occurred based on the monitoring. When the failure of the first virtual storage controller is determined to have occurred, at least one storage volume previously assigned to the first virtual storage controller is remapped to be assigned to a second virtual storage controller. Additionally, the second virtual storage controller retrieves at least one of the transactions from the transaction log in the in-memory storage device and replays at least one of the transactions.

Abstract: An integrated circuit device comprises multiple cores each comprising one or more separate input and output interfaces, the multiple cores integrated within the integrated circuit device to function as a single computer system. Internal inter-chip connection links are disposed on the integrated circuit device for connecting one or more cores with at least one other core via the one or more separate input and output interfaces. One or more bidirectional access ports are communicatively connected in each path of the inter-chip connection links to enable a separate external access point to each of the one or more separate input and output interfaces of the cores, wherein each of the one or more bidirectional access ports is dynamically selectable as each of an external input interface of the integrated circuit device and an external output interface of the integrated circuit device.

Abstract: An apparatus for detecting fault injection includes functional circuitry and fault detection circuitry. The functional circuitry is configured to receive one or more functional input signals and to process the functional input signals so as to produce one or more functional output signals. The functional circuitry meets a stability condition that specifies that stability of a designated set of one or more of the functional input signals during a first time interval guarantees stability of a designated set of one or more of the functional output signals during a second time interval that is derived from the first time interval. The fault detection circuitry is configured to monitor the designated functional input and output signals, to evaluate the stability condition based on the monitored functional input and output signals, and to detect a fault injection attempt in response to detecting a deviation from the stability condition.

Abstract: According to aspects of the invention there are provided methods and apparatus for monitoring, analysing and/or optimising the performance of a mobile device. The mobile device includes a memory with computer readable instructions stored thereon associated with a diagnostic application, which when executed on a processor, has a first level of permissions for accessing the mobile device, and associated with a performance monitoring component, which when executed on the processor, has a second level of permissions for accessing the mobile device. The diagnostic application and performance monitoring component communicate to retrieve performance-related data associated with execution of an application on the mobile device, where the performance-related data is accessible using the second level of permissions.

Abstract: Disclosed is a memory device in which the state of the memory may be set by a mechanical action, with or without mains power present. The memory state may be detected by a microcontroller. The state for the memory device may be reset by a microcontroller. The microcontroller may be external to an apparatus containing the memory device, adjacent to or within the apparatus.

Abstract: Systems and methods for dynamically programming retimers for computer communications are disclosed. For example, in one aspect, a machine implemented method is disclosed that includes: detecting a cable related event at a port coupled to another device via a cable; determine a cable type and a cable length from a storage location of the port; determining if the cable type and the cable length are different from a previously stored cable type and cable length connecting the port to the other device; and when either the cable type or the cable length are different than the previously stored cable type and cable length, programming a retimer device based on the cable type and length.

Abstract: A method for monitoring software application performance and one or more device states affecting a software application on a periodic basis on a mobile device. The method includes one or more computer processors identifying a software application on a mobile device. The method further includes the one or more computer processors identifying a plurality of sampling plans and one or more respective triggers within the plurality of sampling plans that are respectively associated with the software application and are stored on the mobile device. The method further includes the one or more computer processors determining a first value associated with the one or more respective triggers. The method further includes the one or more computer processors selecting a first sampling plan from the plurality of sampling plans for the software application based, at least in part, on the value associated with the one or more respective triggers.

Abstract: An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

Abstract: The systems and method described herein provide smart power scheduling for an electronic device. A user can specify a desired battery duration for the electronic device. Smart power scheduling can modify operation of the electronic device, when appropriate, so that the desired battery duration is met. The user may, for example, know that she will be unable to charge her smartphone for 10 hours and specify a desired battery duration of 10 hours. If during the 10 hours, the user plays a game on the smartphone that drains the battery too fast to meet the 10-hour desired battery duration, the smartphone can modify its operations, for example, by lowering the graphics resolution, to achieve the user-specified desired battery duration. When smart power scheduling modifies operations, it may limit the impact on the user experience, for example, background tasks may be modified before foreground tasks are modified.

Abstract: An application is implemented in the production environment in which the application will be used. Two or more backend systems are used to implement different versions of the application using the production environment in which the application will actually be used and accessed. Actual user data is received. A first portion of the actual user data is routed and processed in the production environment using a first version of the application and a first backend system of the two or more backend systems. A second portion of the actual user data is also routed and processed in the production environment but using a second version of the application and a second backend system of the two or more backend systems. The results data is then analyzed to evaluate the various versions of the application in the production environment.

Abstract: A system for performance testing a web application initializes to be instrumented a subset of methods of the web application to be tested in response to a request, and then tests the application based on the subset of methods. The system generates an instrumented call tree and corresponding stack traces for each request in response to the testing, and determines one or more methods that take longer than a predetermined time period to execute using the instrumented call trees and the stack traces. The system then determines additional methods to be tested and adds the determined additional methods to the subset of methods and repeats the testing.

Abstract: Existing program code, which is executable on one or more computers forming part of a distributed computer system, is analyzed. The analysis identifies log output instructions present in the program code. Log output instructions are those statements or other code that generate log messages related to service requests processed by the program code. A log model is generated using the analysis. The log model is representative of causal relationships among service requests defined by the program code. The log model can then be applied to logs containing log messages generated by execution of the program code, during its normal operation, to group log messages for improved analysis, including visualization, of the performance and behaviour of the distributed computer system.

Abstract: A system for network software debugging comprises a processor, an input interface, and an output interface. The processor is configured to determine a set of available components of a selected component type, and determine a set of backup processes running on the component. The input interface is configured to receive a selection of a backup process of the set of backup processes. The output interface is configured to provide an indication of a change of verbosity level.

Abstract: A storage module may include a controller that has hardware path that includes a plurality of hardware modules configured to perform a plurality of processes associated with execution of a host request. The storage module may also include a firmware module having a processor that executes firmware to perform at least some of the plurality of processes performed by the hardware modules. The firmware module performs the processes when the hardware modules are not able to successfully perform them.

Abstract: A memory management apparatus and method are provided herein. The memory management apparatus includes a memory management list generation unit, a memory allocation unit, and a memory release unit. The memory management list generation unit generates a memory management list adapted to have all memory blocks divided into a plurality of memory blocks and to indicate whether each of the memory blocks has been allocated. The memory allocation unit allocates a memory region that belongs to the memory management list and that corresponds to an amount of memory requested for allocation in response to a memory allocation request. The memory release unit releases a memory region that belongs to the memory management list and that corresponds to a memory region to be released in response to a memory release request.

Abstract: A method relates to receiving, by a processing device executing a virtual machine, bytecode comprising an object to be loaded into a memory space, the object being tagged with a garbage collection descriptor, wherein the garbage collection descriptor is generated according to an annotation to the object in a source code, determining, in view of the garbage collection descriptor, a region of the memory space to store the object, wherein the memory space comprises a first region to store a first set of objects that have survived less than a pre-determined number of rounds of garbage collection and a second region to store a second set of objects that have survived at least the pre-determined number of rounds of garbage collection in the first region, and storing the object in the region of the memory space.

Abstract: Techniques are provided for using bitmaps to indicate which items, in a set of items, are invalid. The bitmaps include an “active” bitmap and one or more “temporal clones”. The active bitmap indicates which items in the set are currently valid. The temporal clones are outdated versions of the active bitmap that indicate which items in the set were invalid at previously points in time. Temporal clones may not be very different from each other. Therefore, temporal clones may be efficiently compressed. For example, a bitmap may be selected as a “base bitmap”, and one or more other bitmaps are encoded using delta encoding. Run length encoding may then be applied to further compress the bitmap information. These bitmaps may then be used to determine which items are valid relative to past-version requests.

Abstract: Techniques are disclosed for improving application responsiveness, and particularly applications used to present rich media content, by precaching nearby but not-yet-displayed content, so that content can be immediately ready to display. A precache window can be used to determine what undisplayed content is precached, in accordance with an embodiment. The size of the precache window, and hence the amount of content that can be precached for later display, is dynamic in nature and is determined based on a number of variables, such as the distance of the content from being visible and the estimated memory consumption of the content. In addition, the dynamic precache window can be recalculated in real-time in response to events and/or as the user interacts with the content in a way that causes a significant enough change to warrant a new memory limit estimate be performed. Out-of-memory errors may be handled by reducing precache window.

Abstract: An apparatus is connected to a main memory, includes a cache memory holding data and a memory storing prediction information in plural areas thereof. The prediction information is referenced to determine whether to execute prefetch, which holds data from the main memory to the cache memory, in a case where a plurality of unrolled instructions produced by unrolling a target instruction included in a loop sentence are executed individually, and corresponds to individual memory accesses executed at certain address intervals in accordance with the respective unrolled instructions. The apparatus executes memory access to the main memory, and executes the prefetch. When the plurality of unrolled instructions are executed individually, the apparatus consolidates a plurality of pieces of prediction information respectively stored in the plural areas of the memory into one based on the number-of-unrolling information, and stores the consolidated prediction information into any one of the plural areas.

Abstract: A total bytes written (TBW) requirement associated with solid state storage is obtained. A size of a cache associated with the solid state storage is determined based at least in part on the TBW requirement.

Abstract: An integrated nonvolatile memory control subsystem and method are disclosed. The integrated nonvolatile memory control subsystem includes a nonvolatile buffer cache, a nonvolatile journal area, nonvolatile storage, and an integrated memory control unit. The integrated memory control unit performs a read operation, a write operation, a commit operation and a checkpoint operation on the cache blocks of the nonvolatile buffer cache and the journal blocks of the nonvolatile journal area. The integrated memory control unit sets each of data blocks of the nonvolatile storage as one among valid state, erasable state and invalid state, depending on being cached or not, being journaled or not, and being a clean cache or not, so as to maintain an authentic original up-to-date consistent data within any one of the nonvolatile buffer cache, the nonvolatile journal area and the nonvolatile storage.

Abstract: Implementations disclosed herein provide a method comprising detecting a power supply status, determining a media cache cleaning scheme based on the detected power supply status, and performing the determined cleaning scheme until a predetermined threshold is reached.

Abstract: Provided are methods and systems for de-duplicating cache lines in physical memory by detecting cache line data patterns and building a link-list between multiple physical addresses and their common data value. In this manner, the methods and systems are applied to achieve de-duplication of an on-chip cache. A cache line filter includes one table that defines the most commonly duplicated content patterns and a second table that saves pattern numbers from the first table and the physical address for she duplicated cache line. Since a cache line duplicate can be detected during a write operation, each write can involve table lookup and comparison. If there is a hit in the table, only the address is saved instead of the entire data string.

Abstract: Volatile memory devices corresponding to a first memory hierarchy may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device corresponding to a second memory hierarchy may be on a second memory module that is coupled to the first memory module by a second signal path. Memory transactions for the nonvolatile memory device may be transferred from the memory controller to the first memory hierarchy using the first signal path, and data associated with an accumulation of the memory transactions may be written from the first memory hierarchy to the second memory hierarchy using the second signal path and a first and second control signal. The first control signal may be generated in view of a detection of wear and the second control signal may be generated in view of a detection of a defect.

Abstract: A storage module may include a controller that is configured to perform a read operation to read data stored in at least one memory, where the data is associated with logical address information. In order to perform the read operation, the controller may be configured to retrieve a preliminary physical address associated with the logical address information, and initiate a data retrieval process for a first version of the data stored at the preliminary physical address prior to confirming a final physical address associated with the logical address information.

Abstract: Provided are methods and systems for managing memory using a hardware-based page filter designed to distinguish between active and inactive pages (“hot” and “cold” pages, respectively) so that inactive pages can be compressed prior to the occurrence of a page fault. The methods and systems are designed to achieve, among other things, lower cost, longer battery life, and faster user response. Whereas existing approaches for memory management are based on pixel or frame buffer compression, the methods and systems provided focus on the CPU's program (e.g., generic data structure). Focusing on hardware-accelerated memory compression to offload CPU translates higher power efficiency (e.g., ASIC is approximately 100× lower power than CPU) and higher performance (e.g., ASIC is approximately 10× faster than CPU), and also allows for hardware-assisted memory management to offload OS/kernel, which significantly increases response time.

Abstract: A method and an apparatus for determining a physical address are disclosed. According to the present disclosure, a page size is obtained according to the higher-order N bits of a linear address, where N is greater than 0 and less than a quantity of bits of the linear address; an index number of a translation lookaside buffer TLB is obtained according to the page size; a mask is obtained according to the page size and a supported minimum page size; a label of the TLB is obtained according to the mask; the higher-order MAC1 bits of a physical address corresponding to the linear address are obtained by searching the TLB according to the index number and the label; and the physical address is obtained according to the mask, the supported minimum page, and the higher-order MAC1 bits of the physical address.

Abstract: A peripheral component interconnect (PCI) device includes a first memory which includes a plurality of page buffers, a base address register which includes a plurality of base addresses, and a first address translation unit which translates each of the plurality of base addresses to a corresponding one of a plurality of virtual addresses. A map table includes a plurality of map table entries each accessed in correspondence to each of the plurality of virtual addresses, and maps each of the plurality of virtual addresses onto a physical address of physical addresses of the plurality of page buffers. The first address translation unit translates each of the plurality of virtual addresses to a corresponding one of the physical addresses using the map table.

Abstract: Slave device circuitry, including processing circuitry which is configured to determine a new session identification value; determine a seed value using a secure hash algorithm on a previously determined seed value; determine a slave number from using the secure hash algorithm on the new session identification value, the determined seed value, and a serial number of the slave device associated with the slave device circuitry; receive a host number from the host imaging apparatus and calculate a session key using a hash-based algorithm computation on the host number, the slave number, the new session identification value, and a stored encryption key. The session key has a first portion for performing encryption and decryption operations on data to be transmitted and data received by the slave device, respectively, and a second portion for generating a new address value of the slave device for communicating with the host.

Abstract: Information handling system secret protection is enhanced by encrypting secrets into a common file and breaking up the encrypted file into plural portions stored at plural memory devices, such as across plural DIMMs disposed in the information handling system. In one embodiment, a decryption key to decrypt the encrypted file is broken into plural portions stored at the plural memory devices. Upon detection of a predetermined security factor, such as an indication of removal of a the encrypted file is removed from the plural portions.

Abstract: Data access optimization features the innovative use of a writer-present flag when acquiring read-locks and write-locks. Setting a writer-present flag indicates that a writer desires to modify a particular data. This serves as an indicator to readers and writers waiting to acquire read-locks or write-locks not to acquire a lock, but rather to continue waiting (i.e., spinning) until the write-present flag is cleared. As opposed to conventional techniques in which readers and writers are not locked out until the writer acquires the write-lock, the writer-present flag locks out other readers and writers once a writer begins waiting for a write-lock (that is, sets a writer-present flag). This feature allows a write-lock method to acquire a write-lock without having to contend with waiting readers and writers trying to obtain read-locks and write-locks, such as when using conventional spinlock implementations.

Abstract: The embodiments are directed to methods and systems for sending and receiving signals between one or more peripheral devices connected to a dongle system and an operating system. The methods and systems can detect when a dongle system has been connected to a mobile computing device. The methods and systems can receive an input to use the dongle system with a local operating system or a remote operating system. The methods and systems can also establish a communication channel between the local operating system and the remote operating system, and exchange signals between the dongle system and the remote operating system using one or more virtual filters.

Abstract: A data processing system is provided which includes a processor nest communicatively coupled to an input/output bus by a bus controller, and a service interface controller communicatively coupled to the processor nest. The system includes storage for storing commands for the bus controller and associated command data and resulting status data, the storage being communicatively coupled to the processor nest and the bus controller. The service interface controller is configured, in response to received service commands, to read and write the storage, to execute the command specified in the storage, to retrieve the result of the command, and to store the result in the storage.

Abstract: A method and apparatus for reconfiguring hardware structures to pipeline the execution of multiple special purpose hardware implemented functions, without saving intermediate results to memory, is provided. Pipelining functions in a program is typically performed by a first function saving its results (the “intermediate results”) to memory, and a second function subsequently accessing the memory to use the intermediate results as input. Saving and accessing intermediate results stored in memory incurs a heavy performance penalty, requires more power, consumes more memory bandwidth, and increases the memory footprint. Due to the ability to redirect the input and output of the hardware structures, intermediate results are passed directly from one special purpose hardware implemented function to another without storing the intermediate results in memory.

Abstract: Techniques for emulating a configuration space by a peripheral device may include receiving a configuration access request, determining that the configuration access request is for a configuration space other than a native configuration space of the peripheral device, and retrieving an emulated configuration from an emulated configuration space. The configuration access request can then be serviced by using the emulated configuration.

Abstract: Provided are a method and apparatus for method and apparatus for encoding registers in a memory module.

Abstract: Data access in a storage device managed by a storage controller is carried out by receiving in the storage controller offsets in objects directly from a plurality of requesting entities of a computer system. The computer controls a mapping mechanism operated by the storage controller, wherein the mapping mechanism relates the offsets in the objects into physical addresses of the data on the storage device, and wherein the data is accessed at the physical addresses.

Abstract: An extensible host controller applied to a host includes a universal serial bus (USB) module, a control unit, and a peripheral component interconnect express (PCIE) bus. The USB module includes a USB unit and a predetermined unit. The PCIE bus is coupled to the control unit, wherein the PCIE bus supports a USB mode and a predetermined mode. When a first host with a first extensible host controller is connected to the USB module, the control unit makes the host utilize the USB mode and the USB unit, or the predetermined mode and the predetermined unit to communicate with the first host according to a determination way.

Abstract: A smart harness may comprise a connector configured to selectively plug into and be removable from an Electronic Control Unit (“ECU”) of a vehicle, a first On-Board Diagnostics device (“first OBD device”), and a second On-Board Diagnostics device (“second OBD device”). The smart harness may further comprise at least one transceiver configured to receive and send diagnostic information between the ECU and the first OBD device and the second OBD device. The smart harness may further comprise a processor and a memory having a program communicatively connected to the processor.

Abstract: A system may include date flow module circuits configured between electronic devices or circuits that may affect and/or intercept the flow of data being communicated between electronic devices. The data flow module circuits may communicate with an external controller that may want to intervene in the data communication. The data flow module circuits may be configured in a pass mode or in an intervention mode. In the pass mode, a data flow module circuit may pass on data it receives without intervention by the external controller. In the intervention mode, the data flow module circuit may receive instructions from the external controller as to the data that the external controller wants the data flow module to output.

Abstract: In one example, a master device connected in a serial-peripheral interface (SPI) daisy chain configuration with a plurality of servant devices, wherein the master device is configured to output a master data output to a first servant data input of a first servant device of a plurality of servant devices, wherein the plurality of servant devices are connected in a serial-peripheral interface (SPI) daisy chain configuration with the master device. The master device further configured to receive a master data input from a last servant device of the plurality of servant devices, wherein the master data input comprises an in-frame response of the plurality of servant devices, and wherein the in-frame response is received by the master device in a single SPI communication frame.

Abstract: A method for accessing a device in a primary peripheral component interconnect express (PCIe) domain from a secondary PCIe domain includes determining which one or more virtual functions of the device in the primary PCIe domain are to be made available to the secondary PCIe domain. A virtual function driver is installed in the primary PCIe domain associated with the one or more virtual functions. Information corresponding to the one or more virtual functions is provided to the secondary PCIe domain. A virtual function driver associated with the one or more virtual functions is installed in the secondary PCIe domain from the information. The virtual function driver in the secondary PCIe domain has same properties as the virtual function driver in the primary PCIe domain. The device in the primary PCIe domain is accessed from the virtual function driver in the secondary PCIe domain.

Abstract: Signaling to control transmit/receive mode transitions of a serial half-duplex transceiver coupled externally to an integrated circuit is provided by the integrated circuit separately from a host processor of the integrated circuit with which the transceiver communicates. This can avoid slow transceiver turn-around times that may be associated with host processor control of the mode transitions.