Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern and a first alignment mark and a second reticle is used to form a second pattern and a second alignment mark in a same layer. A third reticle is aligned to the first alignment mark and the second alignment mark, to obtain an overlay correction value; additionally, a third reticle is aligned to the first alignment mark to obtain a first overlay correction value, a third reticle is aligned to the second alignment mark to obtain a second overlay correction value, and a total overlay correction value is obtained by trading off the first overlay correction value and the second overlay correction value. The third reticle is used to form a third pattern by aligning the third reticle with the total overlay correction value.

Abstract: A semiconductor device includes an interlayer insulating layer having openings, contact plugs formed in lower parts of the openings, wherein the contact plugs include a first conductive layer, and bit lines formed in upper parts of the openings and coupled to the contact plugs, wherein the bit lines include a second conductive layer.

Abstract: A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.

Abstract: A method is disclosed to form a metal-oxysilicate diffusion barrier for a damascene metallization. A trench is formed in an Inter Layer Dielectric (ILD) material. An oxysilicate formation-enhancement layer comprising silicon, carbon, oxygen, a constituent component of the ILD, or a combination thereof, is formed in the trench. A barrier seed layer is formed on the oxysilicate formation-enhancement layer comprising an elemental metal selected from a first group of elemental metals in combination with an elemental metal selected from a second group of elemental metals. An elemental metal in the second group is immiscible in copper or an alloy thereof, has a diffusion constant greater than a self-diffusion of copper or an alloy thereof; does not reducing silicon-oxygen bonds during oxysilicate formation; and promotes adhesion of copper or an alloy of copper to the metal-oxysilicate barrier diffusion layer. The structure is then annealed to form a metal-oxysilicate diffusion barrier.

Abstract: A method of forming a conductive structure includes forming a first opening and a second opening in a dielectric layer on a substrate, wherein the first opening is narrower than the second opening. The method further includes depositing a diffusion barrier layer to line the first opening and the second opening. The method further includes forming a metal layer over the diffusion barrier layer to fill at least portions of the first opening and the second opening, wherein a maximum thickness of the metal layer in the first opening is greater than a maximum thickness of the metal layer in the second opening.

Abstract: A method and apparatus for processing a substrate are provided. In some implementations, the method comprises providing a silicon substrate having an aperture containing an exposed silicon contact surface at a bottom of the aperture, depositing a metal seed layer on the exposed silicon contact surface and exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer.

Abstract: A semiconductor device is provided. The device includes a substrate with a cell and a peripheral area, and an insulating layer. The insulating layer comprises a first region located on the cell area and having outer edge along the cell area, a second region located on the peripheral area and having inner edge along the cell area, a third region located on an area between the cell and the peripheral area and a fourth region located between the second and the third region and forming a boundary with the third region. A conductive member is embedded in the first and the third region and no conductive member is embedded in the fourth region. The boundary has a curbed portion.

Abstract: The present invention is notably directed to a method of fabrication of a microfluidic chip (1). comprising: providing (S10-S20) a wafer (10, 12) of semiconductor material having a diamond cubic crystal structure, exhibiting two opposite main surfaces (S1, S2), one on each side of the wafer, and having, each, a normal in the <100> or <110> direction; and performing (S30) self-limited, anisotropic wet etching steps on each of the two main surfaces on each side of the wafer, to create a via (20, 20a) extending transversely through the thickness of the wafer, at a location such that the resulting via connects an in-plane microchannel (31) on a first one (51) of the two main surfaces to a second one (S2) of the two main surfaces, the via exhibiting slanted sidewalls (20s) as a result of the self-limited wet etching. The invention further concerns microfluidic chips accordingly obtained.

Abstract: A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch apparatus includes a plasma etch chamber. The plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber, a cathode assembly disposed below the plasma source, and a support pedestal for supporting a substrate carrier below the plasma source. The plasma etch apparatus also includes a transfer chamber coupled to the plasma etch chamber. The transfer chamber includes a transfer arm for supporting a substantial portion of a dicing tape of the substrate carrier, the transfer arm configured to transfer a sample from the support pedestal following an etch singulation process.

Abstract: A method of severing a semiconductor device composite includes a carrier having a main surface and a semiconductor layer sequence arranged on the main surface including forming a separating trench in the semiconductor device composite by a first laser cut such that the separating trench only partially severs the semiconductor device composite in a vertical direction running perpendicular to the main surface, and severing the semiconductor device composite completely along the separating trench with a severing cut with a laser.

Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.

Abstract: Provided are a semiconductor device and a fabricating method thereof.

Abstract: A method of processing a workpiece to create a doped fin structure is disclosed. A portion of the workpiece is subjected to a pre-amorphizing implant to create an amorphized region. This amorphized region is then implanted with dopant species, at an implant energy and dose so that the dopant species are contained within the amorphized region. The doped amorphized region is then subjected to a laser melt anneal which crystallizes the amorphized region. The dopant profile is box-like, and the dopant is confined to the previously amorphized region.

Abstract: Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.

Abstract: In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate. A first metal layer is formed on the substrate to cover the first semiconductor pattern. A first heat treatment process is performed such that the first semiconductor pattern and the first metal layer react with each other to form a first metal-semiconductor composite pattern in the first region and a semiconductor material of the substrate and the first metal layer react with each other to form a second metal-semiconductor composite pattern in the second region. The first metal-semiconductor composite pattern is removed from the substrate. A second metal layer is formed on the substrate to cover the second metal-semiconductor composite pattern. The second metal layer includes a material different from the first metal layer.

Abstract: A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided. A plurality of transistors are formed on the silicon including surface in at least one PMOS region and at least one NMOS region, where the plurality of transistors include at least one exposed p-type surface region and at least one exposed n-type surface region. Pre-silicide cleaning removes oxide from the exposed p-type surface regions and exposed n-type surface regions. A plurality of metals are deposited including Yb and Pt to form at least one metal layer on the substrate. The metal layer is heated to induce formation of an inhomogeneous silicide layer including both Ptsilicide and Ybsilicide on the exposed p-type and exposed n-type surface regions. Unreacted metal of the metal layer is stripped.

Abstract: A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included.

Abstract: A method, and the resulting structure, of forming two fins with different types of strain and material on the same substrate.

Abstract: A method for testing a monolithic stacked integrated circuit (IC) is provided. The method includes receiving a layer of the IC. The layer has a first surface and a second surface, and the layer includes a substrate. The method further includes attaching probe pads to the first surface, and applying a first fault testing to the IC through the probe pads. The method further includes forming another layer of the IC over the second surface, and applying a second fault testing to the IC through the probe pads.

Abstract: A plasma processing apparatus includes a processing chamber configured to perform a plasma processing on a sample, a first radio frequency power supply configured to generate a plasma, a sample stage configured to place the sample thereon, a second radio frequency power supply configured to supply a radio frequency power to the sample stage, a mass flow controller configured to supply a gas into the processing chamber, and a control device configured to change the radio frequency power supplied from the first radio frequency power supply or the second radio frequency power supply based on a change of plasma impedance after a first gas is switched to a second gas.

Abstract: Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.

Abstract: A printed wiring board includes a power supply conductor pattern arranged on one conductor layer, one ground conductor pattern arranged on the one conductor layer, and another ground conductor pattern arranged on the another conductor layer so as to be opposed to the power supply conductor pattern. The power supply conductor pattern includes a power supply pad on which a terminal of a capacitor is to be bonded. The one ground conductor pattern includes a ground pad on which another terminal of the capacitor is to be bonded. A slit is formed in the another ground conductor pattern so as to pass through a projection portion defined by projecting the power supply pad onto the another ground conductor pattern and divide a projection portion defined by projecting the power supply conductor pattern onto the another ground conductor pattern.

Abstract: A semiconductor package. Implementations may include a substrate including a metallic baseplate coupled with an electrically insulative layer and a plurality of metallic traces coupled to the electrically insulative layer on a surface of the electrically insulative layer opposing a surface of the electrically insulative layer coupled to the metallic baseplate. The plurality of metallic traces may include at least two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the surface of the electrically insulative layer coupled with the metallic baseplate. The package may include at least one semiconductor device coupled to the substrate, a mold compound that encapsulates the power electronic device and at least a portion of the substrate, and at least one package electrical connector coupled with the substrate.

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

Abstract: In some embodiments, a semiconductor device includes a first die, a second die coupled to a first surface of the first die, and a third die coupled to the first surface of the first die. The semiconductor device further includes an underfill material disposed between the first die and the second die and between the first die and the third die. A first volume of the underfill material for the second die is different than a second volume of the underfill material for the third die.

Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a dielectric layer, a component, and a first patterned conductive layer. The encapsulation layer has a first surface. The component is within the encapsulation layer and has a front surface and a plurality of pads on the front surface. The dielectric layer is on the first surface of the encapsulation layer, and defines a plurality of via holes; wherein the plurality of pads of the component are against the dielectric layer; and wherein the dielectric layer has a second surface opposite the first surface of the encapsulation layer. Each of plurality of via holes extends from the second surface of the dielectric layer to a respective one of the plurality of the pads. The first patterned conductive layer is within the dielectric layer and surrounds the via holes.

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.

Abstract: A mold package includes a substrate having a first surface and a second surface disposed opposite to the first surface, a wiring part disposed on the first surface in protruded manner, a molding resin, and a resin film. The molding resin partially seals the first surface of the substrate and the wiring part and intersects with the wiring part. The resin film is disposed between the first surface of the substrate and the end of the molding resin, and seals the wiring part and the first surface of the substrate adjacent to the wiring part. The resin film includes a first portion disposed inside the molding resin and a second portion disposed outside the molding resin. An upper surface of the second portion is lower than an upper surface of the first portion and has less uneven portions than the upper surface of the first portion.

Abstract: The present invention provides a micropackaged device comprising: a substrate for securing a device with a corrosion barrier affixed to the substrate, wherein the corrosion barrier comprises a first thin-film layer, a metal film coating the thin-film layer and a second thin-film layer to provide a sandwich layer; and optionally at least one feedthrough disposed in the substrate to permit at least one input and or at least one output line into the micropackaged device, wherein the micropackaged device is encapsulated by the corrosion barrier. Methods of producing the micropackaged device are also disclosed.

Abstract: A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipation plate arranged on an upper surface of the semiconductor element with an adhesive arranged in between, and an encapsulation resin filling a gap between the heat dissipation plate and the wiring substrate. The heat dissipation plate includes a body and a projection. The body is overlapped with the semiconductor element in a plan view and has a larger planar shape than the semiconductor element. The projection is formed integrally with the body. The projection projects outward from an end of the body and is located below the body. The encapsulation resin covers upper and lower surfaces of the projection. The body includes an upper surface exposed from the encapsulation resin.

Abstract: A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.

Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

Abstract: Semiconductor devices having through-electrodes are provided. The semiconductor devices may include a substrate, a through-electrode penetrating vertically through the substrate, a circuit layer on the substrate and metal lines in the circuit layer. The metal lines may include two first metals on opposing edges of a top surface of the through-electrode and second metals above the top surface of the through-electrode. At least some of the second metals may not vertically overlap the two first metals.

Abstract: A semiconductor device package includes a first substrate, which has a lower substrate surface and an upper substrate surface. A conductive dummy gate structure is disposed over the upper substrate surface. An interconnect structure is disposed over the conductive dummy gate structure. The interconnect structure includes a plurality of metal layers disposed within a dielectric structure and at least one of the metal layers is electrically coupled to the conductive dummy gate structure. A conductive through-substrate via extends from the lower substrate surface to an underside of the conductive dummy gate structure and is electrically coupled to the conductive dummy gate structure.

Abstract: A semiconductor die arrangement comprising a first die including at least one semiconductor device; a second die including at least one semiconductor device; a lead frame associated with the first die and comprising one or more lead fingers, wherein the second die is mounted on one of the lead fingers and electrically connected to a further element by a bond wire.

Abstract: A semiconductor device, includes a die pad that has a first main surface and a second main surface located on the opposite side of the first main surface; a lead arranged next to the die pad; a semiconductor chip that has a surface, a first electrode and a second electrode formed on the surface, and a reverse side located on the opposite side of the surface, and is mounted on a chip mounting area of the first main of the die pad; a first wire that electrically couples the first electrode of the semiconductor chip and the lead; a second wire that electrically couples the second electrode of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wire, and the second wire.

Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.

Abstract: A double-sided chip on film (COF) packaging structure and a manufacturing method thereof are disclosed. The double-sided COF structure includes a metal layer, a first insulating layer, a second insulating layer, a chip, and an encapsulant. The first insulating layer and second insulating layer are disposed on a first surface and a second surface of metal layer respectively. The first surface and second surface are opposite. The first insulating layer includes a first part and a second part separated from each other. An accommodating space is existed between the first part and the second part and a part of the first surface is exposed. The chip is accommodated in the accommodating space and disposed on the exposed part of the first surface. The encapsulant fills the spaces between the chip and the first part and between the chip and the second part to form the double-sided COF packaging structure.

Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and having a surface exposed from the first surface of the dielectric layer; a plurality of conductive posts embedded in the dielectric layer and electrically connected to the first circuit layer and having one ends exposed from the second surface of the dielectric layer; a second circuit layer formed on the second surface of the dielectric layer and electrically connected the ends of the conductive posts exposed from the second surface of the dielectric layer; and a plurality of protruding elements formed on the surface of the first circuit layer exposed from the first surface of the dielectric layer, thereby providing a large contact area so as to strengthen bonding between a semiconductor chip and the first circuit layer of the package structure.

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

Abstract: A printed circuit board includes: an insulation layer including circuit patterns, the circuit patterns having a groove formed therein; a metal protection layer (disposed in the groove; a solder resist layer disposed on the insulation layer and having an opening exposing the circuit patterns; and a solder bump disposed on the opening.

Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.

Abstract: A wiring board includes a core substrate including an insulating layer and a conductor layer formed on the insulating layer, and a build-up layer laminated on the substrate and including an inter-layer insulating layer and a conductor layer laminated on the inter-layer. The substrate has opening penetrating through the insulating layer such that surface of the conductor layer in the substrate is forming bottom of the opening, the substrate has a via conductor formed in the opening and including plating filling the opening, the conductor layer in the substrate includes a metal foil, the conductor layer in the build-up layer includes a metal foil, and the metal foil in the substrate has surface in contact with the surface of the insulating layer such that the surface of the metal foil in the substrate has surface roughness smaller than surface roughness of surface of the metal foil in the build-up layer.

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Abstract: A power module, having a printed circuit board core, which contains at least one electronic power component embedded in an insulating layer, the core being arranged between two heat dissipation plates wherein each heat dissipation plate has a metal outer layer and a metal inner layer electrically separated from said metal outer layer by a thermally conductive, electrically insulating intermediate layer, and electrode terminals of the at least one power component are guided out from the core via terminal lines, wherein the printed circuit board core on both sides of the insulating layer has a conductor layer, at least one conductor layer is structured at least in portions, and each conductor layer is connected at least in portions via a conductive, metal intermediate layer to a metal inner layer of the heat dissipation plate, contacts run from the structured conductor layer to the electrode terminals of the at least one power component, and at least one power terminal of the at least one power component is con

Abstract: A semiconductor structure includes a substrate comprising a plurality of layers formed thereon, at least a first device formed in one of the layers formed thereon, a drawn region enclosing the first device, and a plurality of dummy structures in another layer. The dummy structures are formed in a first region correspondingly outside of the drawing region and in a second region correspondingly inside of the drawing region.