Abstract: Memory die can be stacked to form a three-dimensional integrated circuit. For example, through-silicon vias (TSVs) can permit signals to pass vertically through the three-dimensional integrated circuit. Disclosed herein are apparatuses and methods to perform post package trimming of memory die, which advantageously permits the memory die to be trimmed after the memory die is stacked, such that test and trimming characteristics are relatively close to that which will be actually be encountered.

Abstract: A semiconductor device may include a common coupling block suitable for coupling a plurality of first data lines to a plurality of second data lines in response to a common control signal, which is activated regardless of a data bandwidth option mode, a first coupling block suitable for coupling a part of the plurality of second data lines to a part of a plurality of third data lines in response to a first operation control signal, a second coupling block suitable for coupling the other part of the plurality of second data lines to the other part of the plurality of third data lines in response to a second operation control signal, and a control block suitable for activating one or more of the first and second operation control signals based on the data bandwidth option mode, during a data input/output operation.

Abstract: A memory device including a stack semiconductor device including; an upper substrate vertically stacked on a lower substrate, the upper substrate including N upper through-silicon vias (UTSV) and upper driving circuits, and the lower substrate including N lower through-silicon vias (LTSV) and lower driving circuits, wherein each one of the upper driving circuits is stagger-connected between a Kth UTSV and a (K+1)th LTSV, where ‘N’ is a natural number greater than 1, and ‘K’ is a natural number ranging from 1 to (N?1).

Abstract: A semiconductor memory may include: a storage unit suitable for storing a minimum operation interval between row command operations, a detection unit suitable for detecting whether row command signals inputted for the row command operations are activated at the minimum operation interval, a latching unit suitable for generating flag signals by latching the row command signals, and a shifting unit suitable for shifting the flag signals based on the minimum operation interval in response to an output signal of the detection unit, and generating an internal row command signals.

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract: A circuit includes a first power node that receives a first operational voltage having a first operational voltage level and a second power node that receives a second operational voltage having a second operational voltage level different from the first operational voltage level. A memory cell is coupled with the first power node, the memory cell configured to store a logic value, and a tracking cell is coupled with the second power node, the tracking cell configured to generate a signal having a timing responsive to the second operational voltage level. The circuit is configured to read the logic value of the memory cell based on the signal.

Abstract: Provided is a neuromorphic device including first and second lower electrodes formed on a substrate to be electrically separated, first and second lower insulating film stacks formed at least on respective surfaces of the first and second lower electrodes, first, second, and third doped regions formed at left and right sides of the first and second lower electrodes, first and second semiconductor regions formed on the first and second lower insulating film stacks, an upper insulating film stack formed on the first and second semiconductor regions and the first, second, and third doped regions, and an upper electrode formed on the upper insulating film stack. Accordingly, a specified neuromorphic device can be reconfigured to have arbitrarily inhibitory or excitatory functionality by using the first and second lower electrodes and the lower insulating film stacks including charge storage layers formed on the surfaces of the electrodes.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell.

Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to a memory device having a controller configured to cause a write operation to be performed on a variable resistance memory cell, which includes application of two successive access pulses having opposite polarities, and methods of using the same.

Abstract: Methods are provided for use with a memory array that includes a selected memory cell coupled to a selected word line and a selected bit line, with the selected word line biased at a read voltage. The method include coupling a sense amplifier to the selected bit line, the sense amplifier including a capacitor integrator, a single-transistor amplifier and a level shifter, maintaining the selected bit line at a voltage of substantially 0V using the single-transistor amplifier and the level shifter, and integrating a selected bit line current on the capacitor integrator.

Abstract: A resistive memory device. Implementations may include an array of memory cells including resistive memory elements which are coupled to isolation transistors and which may include a magnetic tunnel junction. A decoder decodes input address information to select a row of the array. A binarizer coupled to the memory array assigns binary weights to outputs of the memory array output through bit lines coupled to the memory cells. A summer sums the binary weighted outputs, and a quantizer generates an output digital code corresponding to data stored in a plurality of memory cells during a prior program cycle. The outputs of the memory array may be currents or voltages. In implementations multiple arrays of memory cells may be utilized and their respective outputs combined to form higher bit outputs, such as eight bit, twelve bit, sixteen bit, and so forth.

Abstract: A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information.

Abstract: A method is for operating a memory device including a plurality of memory cells disposed in regions where a plurality of first signal lines and a plurality of second signal lines cross each other. The method includes applying an initial voltage to the plurality of first signal lines, floating the plurality of first signal lines to which the initial voltage is applied, applying a second inhibit voltage to the plurality of second signal lines, and increasing voltage levels of the plurality of first signal lines to a first inhibit voltage level via capacitive coupling between the plurality of first signal lines which are floated and the plurality of second signal lines to which the second inhibit voltage is applied.

Abstract: A method includes, in a data storage device including a resistive memory, receiving an erase command to erase a portion of the resistive memory. The method further includes sending shaped data to be stored at the portion of the resistive memory responsive to the erase command.

Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.

Abstract: Apparatuses and methods for a non-volatile memory scheme are described herein. An example apparatus may include a memory block including a plurality of subblocks of memory cells and further may include a control unit. The control unit may be configured to program a first access line group of each subblock of the plurality of subblocks during a program operation and to program a second access line group of each subblock of the plurality of subblocks during the program operation responsive to programming the first access line group of each of the plurality of subblocks.

Abstract: Methods of biasing in memory devices facilitate memory device programming operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source, where the data line is biased to a potential greater than a potential to which the source is biased during a programming operation performed on the selected memory cell.

Abstract: A method of operating the semiconductor device includes performing an erase operation on a plurality of memory cells, performing a back-tunneling operation by injecting electrons into a storage node from a gate electrode of a memory cell, selected among the plurality of memory cells, and performing a program operation by injecting electrons into the storage node from a channel layer of the selected memory cell.

Abstract: An operation method of a storage device including a nonvolatile memory and a memory controller controlling the nonvolatile memory, includes transmitting a multi-program command to the nonvolatile memory by the memory controller; and programming memory cells connected to two or more word lines by the nonvolatile memory in response to the multi-program command.

Abstract: An erase method of a nonvolatile memory device includes applying an erase voltage to a substrate; sensing a temperature of a memory cell array; setting a delay time based on the temperature of the memory cell array, wherein the delay time starts in response to the erase voltage being applied to the substrate; applying a ground voltage to a ground selection line connected to a ground selection transistor during the delay time; and increasing a voltage of the ground selection line after the delay time.

Abstract: Methods and devices for erasing information stored on an electronic semiconductor component in a plurality of non-volatile memory elements are described. Irradiating the semiconductor component with erasing radiation until a target dose has been absorbed by the semiconductor component, the erasing radiation penetrating the semiconductor component, results in an ionization effect which influences the concentration of the charge carriers stored on the memory elements such that a statistical distribution of the threshold voltages of the memory elements forms a contiguous region.

Abstract: Embodiments are provided that include a method including providing a first voltage to a memory cell prior to an operation, wherein a magnitude of the first voltage is approximately 5 volts. The method further includes providing a second voltage to the memory cell during the operation, wherein a magnitude of the second voltage is in the range of approximately 1.0 and 1.5 volts. The method also includes determining a state of the memory cell after providing the first voltage and the second voltage.

Abstract: An optimal read threshold estimation method includes determining a flip difference corresponding to an optimal step size ?opt, estimating a first slope m1 at a first read point and a second slope m2 at a second read point, and obtaining an optimal read threshold (XLPopt) as the intersection of a first line with the first slope m1 and a second line with the second slope m2.

Abstract: A read-threshold calibration method in a solid state storage system including measuring a threshold voltage distribution of solid state storage elements; determining a threshold voltage; decoding data according to the determined threshold voltage; filtering the threshold voltage distribution of solid state storage elements with a predetermined filter length when the decoding fails; changing the filter length; and repeating the determining, decoding, filtering, and changing steps with the changed filter length until the decoding is successful.

Abstract: A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

Abstract: A shift register circuit may include a first latch capable of latching an input signal in synchronization with a first clock, a first flip-flop capable of latching the output signal of the first latch in synchronization with a second dock having the same skew as the first clock, a second latch capable of latching the output signal of the first flip-flop in synchronization with a third clock having a different skew from the second clock, and a second flip-flop capable of latching the output signal of the second latch circuit in synchronization with a fourth clock having the same skew as the third clock.

Abstract: A shift register unit, a shift register, a gate drive circuit and a display device, the shift register unit, comprising: an input module; an output module configured to output a first clock signal of a first clock signal terminal to an output terminal of the shift register unit according to a potential of the pull-up node at an output phase; a reset module configured to pull down the potentials of the pull-up node and the output terminal of the shift register unit according to a reset signal at a reset phase; and a pull-down module configured to pull down the potentials of the pull-up node and the output terminal according to a second clock signal of a second clock signal terminal at a pull-down phase. Compared to the related art, the structure of the shift register unit provided by the present disclosure is simpler.

Abstract: Systems and methods for self-testing archival memory devices are described. The memory device includes a data storage component capable of being coded with data. The memory device further includes a read-write mechanism configured to read, write, and delete data stored on the data storage component. The memory device includes a read-write controller configured to control the read-write mechanism based on input received through a device interface of the memory device, wherein the device interface of the memory device is configured to connect to an external computing device. The memory device further includes a diagnostic controller configured to perform a test on at least one of the data stored on the data storage component, the data storage component, and the read-write mechanism. The memory device includes a power source configured to provide operational power to the diagnostic controller when the memory device is not connected to an external power source.

Abstract: A test system may include: a vector storage unit suitable for storing a first test vector corresponding to a first test operation; a test target suitable for performing a test operation corresponding to the test vector stored in a vector storage unit; a comparison unit suitable for comparing a first test result to an expected value to output a first test result value, wherein the first test result is transferred from the test target as a result of the first test operation based on the first test vector; and a vector control unit suitable for modifying the first test vector to generate a second test vector corresponding to a second test operation.

Abstract: Systems and methods for self-testing archival memory devices are described. The memory device includes a data storage component capable of being coded with data. The memory device further includes a read-write mechanism configured to read, write, and delete data stored on the data storage component. The memory device includes a read-write controller configured to control the read-write mechanism based on input received through a device interface of the memory device, wherein the device interface of the memory device is configured to connect to an external computing device. The memory device further includes a diagnostic controller configured to perform a test on at least one of the data stored on the data storage component, the data storage component, and the read-write mechanism. The memory device includes a power source configured to provide operational power to the diagnostic controller when the memory device is not connected to an external power source.

Abstract: A first signal and a second signal associated with a circuit may be identified. A first count of a number of times that the second signal is associated with a transition when the first signal is at a first value may be determined. Furthermore, a second count of a number of times that the second signal is associated with a transition when the first signal is at a second value may be determined. A value corresponding to the dependence between the second signal and the first signal may be calculated based on the first count and the second count.

Abstract: An integrated circuit has a first circuit portion on a first level and a second circuit portion on a second level different from the first level. The first circuit portion includes a first cell having a first voltage value at a first node and a second voltage value at a second node. The second circuit portion includes a second cell coupled with the first cell, the second cell being selectively controllable to supply a voltage to the first cell based on an instruction to supply the voltage. The instruction to supply the voltage is based on a determined mismatch between the first voltage value and the second voltage value being greater than a predetermined threshold value.

Abstract: An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response to

Abstract: A repair circuit includes a column repair signal generation block suitable for comparing an input address with respective first and second repair addresses in response to a mode control signal, and generating first and second column repair signals; a normal decoder suitable for accessing any one of a first normal column line corresponding to the input address and a second normal column line corresponding to an address that is different in terms of a most significant bit from the input address, in response to the first and second column repair signals; and a redundancy decoder suitable for decoding the first repair address in response to the first and second column repair signals, wherein the second repair address is generated by inverting a most significant bit of the first repair signal.

Abstract: A visual indicator display device includes a bracelet, a transparent capillary chamber, and a displacement member. The transparent capillary chamber is matched to an indicia and has a primary length and a width less than the primary length. The displacement member is functionally disposed at one end of the capillary chamber and is responsive to a measureable input for moving a fluid contained therein a defined amount.

Abstract: A fuel rack for nuclear fuel assemblies includes a base plate and an array of cells for holding fuel assemblies. The array of cells includes: a plurality of first slotted plates slidably interlocked with one another to form a top portion of the array of cells, the plurality of first slotted plates formed of a first material; a plurality of second slotted plates slidably interlocked with one another to form a middle portion of the array of cells, the plurality of second slotted plates formed of a second material, the first and second materials being metallurgically incompatible; and a plurality of third slotted plates slidably interlocked with one another to form a bottom portion of the array of cells, the plurality of third slotted plates formed of the first material and connected to a top surface of the base plate.

Abstract: A ventilation system operating method for a service personnel-accessible operations room or control room in a nuclear plant or nuclear power plant enables a supply of decontaminated fresh air at least for a few hours in the event of serious incidents involving the release of radioactive activity. The content of radioactive inert gases in the fresh air supplied to the operations room should be as low as possible. Therefore, an air supply line is guided from an external inlet to the operations room, a first fan and a first inert gas adsorber column are connected into the air supply line, an air discharge line is guided from the operations room to an external outlet, a second fan and a second inert gas adsorber column are connected into the air discharge line, and a switchover device interchanges the roles of the first and second inert gas adsorber columns.

Abstract: Provided is a metal wire. The metal wire includes a copper layer, and at least one barrier layer. The barrier layer is disposed on at least one of an upper part and a lower part of the copper layer. The barrier layer includes an alloy including copper, nickel, and zinc.

Abstract: Example embodiments relate to a nanostructure including a conductive region and a nonconductive region, wherein the conductive region includes at least one first nanowire, and the nonconductive region includes at least one second nanowire that is at least partially sectioned, a method of preparing the nanostructure, and a panel unit including the nanostructure.

Abstract: Provided is a conductive resin composition for microwave heating capable of suppressing the generation of sparks when microwave heating is performed. A conductive resin composition for microwave heating comprising a non-carbonaceous conductive filler, a curable and insulating binder resin, and a carbonaceous material having a higher volume resistivity value than the non-carbonaceous conductive filler, the carbonaceous material having an aspect ratio of 20 or less, and the content of the carbonaceous material being 1 to 20 parts by mass, relative to the total of 100 parts by mass of the non-carbonaceous conductive filler and the curable and insulating binder resin. The carbonaceous material efficiently absorbs the microwave, and thus, when the microwave is irradiated to heat and cure the conductive resin composition, generation of sparks can be suppressed.

Abstract: The invention relates to a conductive paste composition useful in the manufacture of photovoltaic cell electrodes, especially electrodes contacting the p-type emitter of an n-type base cell. The paste composition may comprise a source of a conductive metal, a glass frit such as a lead borate, aluminum metal powder, and a boron source that may be at least one of elemental boron, a non-oxide, boron-containing substance, or a combination thereof, all dispersed in an organic vehicle that renders the composition suitable for screen printing or other like application method. Also provided are a semiconductor device such as a photovoltaic cell having an electrode made with the paste composition, and a method for its manufacture.

Abstract: An object is to provide a heat-conductive sheet being excellent in insulation properties and thermal anisotropy and having high heat-dissipating properties. An insulating heat-conductive sheet including insulating highly heat-conductive fibers penetrating in a thickness direction of the sheet and a binder resin, wherein the insulating highly heat-conductive fibers penetrating in the thickness direction have a penetration density greater than or equal to 6%, and the insulating heat-conductive sheet has a ratio of thermal conductivity in the thickness direction to thermal conductivity in a planar direction greater than or equal to 2, and an initial dielectric breakdown strength greater than or equal to 20 kV/mm.

Abstract: A multilayer composite conductor comprises an inner layer and an outer layer. The inner layer comprises at least one wire which has a conductivity of 60% to 70% IACS as a core of the multilayer composite conductor; wherein a volume of the inner layer is 40% to 55% of a total volume of the multilayer composite conductor; and the outer layer comprises multiple wires which have a conductivity of 70% to 98% IACS, and the outer layer is wound around the inner layer; wherein a volume of the outer layer is 45% to 60% of the total volume of the multilayer composite conductor. In another aspect, the present invention also provides a method for manufacturing a multilayer composite conductor. At the same current-carrying surface, the multilayer composite conductor of the present invention saves more than 60% of copper usage, thereby achieving light weight and low cost.

Abstract: A heat shield for use with cables in a nuclear environment can include a thermal insulator. The thermal insulator can have a low thermal conductivity and can be formed of a silica glass fiber material, an aerogel, or an aerogel-derived material. The heat shield can mitigate a 650° C. temperature spike caused by a severe accident condition. Cables including such heat shields can operate through a nuclear accident that causes an initial 650° C. temperature spike.

Abstract: Described herein are foamable compositions and methods of making foamed compositions. The foamable composition comprises at least one polymer and a foaming agent. The foaming agent comprises a talc or a talc derivative. The polymers described herein comprise a substantially non-halogenated polymer. One or more additives are added to render the compositions flame retardant and/or smoke suppressant. Also described are Power over Ethernet (PoE) cables, having at least one electrical conduit comprising an electrically conductive core, an insulation that at least partially surrounds said electrically conductive core and a polymeric separator extending from a proximal end to a distal end and having at least one channel adapted for receiving the at least one electrical conduit. The PoE cables are capable of carrying about 1 watt to about 200 watts of power.

Abstract: A high-frequency electric wire is provided with a conductor which formed by compressing multiple wire strands, each of which is obtained by coating an outside of a wire rod made of insulating resin with a metal layer, and a sheath provided on the conductor. Each of the wire strands of the conductor is compressed in such a way that a deformation ratio of the wire strand exceeds 0% and is 20% or less. The compression is performed, for example, during bundling and sheathing of the multiple wire strands.

Abstract: Electrically-conductive articles are prepared to have electrically-conductive metallic grids and electrically-conductive metallic connectors (BUS lines) on one or both supporting sides of a transparent substrate. The electrically-conductive metallic connectors are designed with one metallic main wire that comprises two or more adjacent metallic micro-wires in bundled patterns. These bundled patterns and metallic micro-wires are designed with specific dimensions and configurations to provide optimal fidelity (or correspondence) to the mask image used to provide such patterns. The electrically-conductive articles can be prepared using various manufacturing technologies and can be used as parts of various electronic devices including touch screen devices. The electrically-conductive metallic grids and connectors can be prepared and designed using various technologies that are amenable to obtaining very fine lines in predetermined patterns.

Abstract: A tool for mounting a protective sleeve onto a wire. According to example forms, the protective sleeve is resiliently-flexible and longitudinally-slitted and the wire is in the form of an audio cable. The tool includes a tube-mounting assembly and a wire holder. According to some example forms, the tool includes a handle for grasping the tool during use. In some example forms, the wire is in the form of a charging cable.

Abstract: An insulating system includes an electrically insulating, substantially disk-shaped insulating configuration which spans a base surface. The insulation configuration includes at least one first and one second sub-element. A joining gap is disposed between the two sub-elements. An assembly method for an insulating system is also provided.