Abstract: Aspects of the present disclosure are directed towards a method of receiving a first command for a virtual machine (VM) instance. This includes performing automatic command line parsing on the first command. This can further include associating, based on automatic command line parsing, a first tag with the VM instance. This can further include causing the first tag to be displayed as associated with the VM instance.

Abstract: In a distributed server storage environment, a set of like tasks to be performed is organized into a first group, and a last used processing group associated with the like tasks is stored. Upon a subsequent dispatch, the last used processing group is compared to other processing groups and the tasks are assigned to a processing group based upon a predetermined threshold.

Abstract: An operating system of a data processing system receives a request from a first process to acquire an exclusive lock for accessing a resource of the data processing system. A second priority of a second process is increased to reduce total execution time. The second process is currently in possession of the exclusive lock for performing a transactional operation with the resource. The second priority was lower than a first priority of the first process. The operating system notifies the second process to indicate that another process is waiting for the exclusive lock to allow the second process to complete or roll back the transactional operation and to release the exclusive lock thereafter.

Abstract: In one embodiment, a system includes a processor and logic integrated with and/or executable by the processor. The logic is adapted to: define a hardware feature policy for one or more hardware components of a system; and enable and/or disable one or more hardware features of one or more of the hardware components based on the hardware feature policy, wherein the hardware feature policy comprises instructions to enable and/or disable access to the one or most hardware features based on one or more criteria selected from a group consisting of: a feature access schedule; a volume feature access group; a job feature access group; and an user feature access group.

Abstract: In one embodiment, a method includes defining a hardware feature policy for one or more hardware components of a system; and enabling and/or disabling one or more hardware features of one or more of the hardware components based on the hardware feature policy, where the hardware feature policy comprises instructions to enable and/or disable access to the one or more hardware features based on one or more criteria selected from the group consisting of: a feature access schedule; a volume feature access group; a job feature access group; and an user feature access group.

Abstract: In a parallel computing method performed by a parallel computing system comprising a plurality of central processing units (CPUs), a main process executes. Tasks are executed in parallel with the main process on CPUs not used in executing the main process. Results of completed tasks are stored in a cache, from which the main process retrieves completed task results when needed. The initiation of task execution is controlled by a priority ranking of tasks based on at least probabilities that task results will be needed by the main process and time limits for executing the tasks. The priority ranking of tasks is from the vantage point of a current execution point in the main process and is updated as the main process executes. An executing task may be pre-empted by a task having higher priority if no idle CPU is available.

Abstract: Tasks scheduled to be performed at future times within a virtual space may be managed. Selections of one or more tasks performable within the virtual space may be received. The one or more tasks may include a first task associated with a first duration. The first task may be scheduled to be performed at a first time. The first time may be the first duration later than a time of receipt of the selection of the first task. Managing the scheduling of the first task may include one or more of (1) delaying performance of the first task so that the first task is scheduled to be performed at a time later than the first time, (2) advancing performance of the first task so that the first task is scheduled to be performed at a time before the first time, or (3) canceling performance of the first task.

Abstract: Systems, methods, and machine-readable and executable instructions are provided for dynamically ranking and scheduling monitoring tasks. Dynamically ranking and scheduling monitoring tasks can include determining an updated ranking for each of a number of monitoring tasks, where the updated ranking can include analyzing historical measurements of each of the number of monitoring tasks. An order of execution can be scheduled for each of the number of monitoring tasks based on the updated ranking for each of the number of monitoring tasks.

Abstract: Methods and system for optimizing an execution of a business process are disclosed. In one aspect, a request to execute a business process is received. The business process is executed on multiple threads, which may include multiple computations. The business process is optimized by determining an optimal number of threads for executing the business process by a thread optimization model. From the determined optimal number of threads, the computations in the threads may be distributed or reallocated iteratively by executing an inter-thread computations optimization model. Executing the thread optimization model and the inter-thread computations optimization model optimizes the execution of the business process.

Abstract: An electronic apparatus generates a workflow for processing data with a plurality of functions in combination. The electronic apparatus includes a function accepting unit and a workflow generating unit. The functions accepted include an edit function that edits data based on settings and an execution result notification function that indicates an execution result obtained from the functions executed before the execution result notification function in the workflow. The execution result notification function indicates that it can accept a return instruction, and upon acceptance of the return instruction, the execution result notification function returns the execution position to the function specified by the accepted return instruction. After the execution position is returned in response to the return instruction, the settings of at least one of the edit functions located between the function specified by the return instruction and the execution result notification function in the workflow can be changed.

Abstract: An asynchronous multiple-core processor may be adapted for carrying out sets of known tasks, such as the tasks in the LAPACK and BLAS packages. Conveniently, the known tasks may be handled by the asynchronous multiple-core processor in a manner that may be considered to be more power efficient than carrying out the same known tasks on a single-core processor. Indeed, some of the power savings are realized through the use of token-based single core processors. Use of such token-based single core processors may be considered to be power efficient due to the lack of a global clock tree.

Abstract: A multiprocessor computer system and method for use therein are provided for assigning processes to processor nodes. The system can determine a first pair of processes and a second pair of processes, each process of the first pair of processes executing on different nodes and each process of the second pair of processes executing on different nodes. The system can determine a first priority value of the first pair of processes, based at least in part on a first resource access rate of the first pair of processes; and determine a second priority value of the second pair of processes, based at least in part on a second resource access rate of the second pair of processes. The system can determine the first priority value is greater than the second priority value; and determine to reassign a first process of the first pair of processes to a first node, wherein a second process of the first pair of processes is executing on the first node.

Abstract: Dynamic pool reallocation performed by the following steps: (i) defining a plurality of resource pools including a first pool and a second pool, where each resource pool has a plurality of assigned resources; (ii) receiving a plurality of jobs to be executed; (iii) for each job of the plurality of jobs, assigning a respective resource pool, of the plurality of resource pools, to be used in completing the job; (iv) determining a preliminary schedule for executing the jobs on their respective resource pools; (v) determining whether the preliminary schedule will cause any jobs to miss service level agreement (SLA) deadlines corresponding to the job; (vi) executing the plurality of jobs on their respectively assigned resource pools; and (vii) re-assigning first resource from the second pool to the first pool during at least some of the time of the execution of the first job by the first resource pool.

Abstract: Resource restrictions are associated with a user identifier. A resource restriction agent receives operating system calls related for resources and provides resource request data to a resource agent. The resource agent determines whether the resource is restricted based on the resource request data and resource restriction data and generates access data based on the determination. The resource restriction agent grants or denies the system call based on the access data.

Abstract: A computer-implemented method, carried out by one or more processors, for managing resources in a server environment. In an embodiment, the method includes determining to prepare one or more virtual resources for activation of one or more allocated host resources, based, at least in part, on virtual resource definitions. The one or more allocated host resources and the one or more virtual resources are activated. Activation of the one or more virtual resources is finalized, wherein finalizing the activation includes updating the virtual resource definitions.

Abstract: Techniques are described for managing program execution capacity, such as for a group of computing nodes that are provided for executing one or more programs for a user. In some situations, dynamic program execution capacity modifications for a computing node group that is in use may be performed periodically or otherwise in a recurrent manner, such as to aggregate multiple modifications that are requested or otherwise determined to be made during a period of time, and with the aggregation of multiple determined modifications being able to be performed in various manners. Modifications may be requested or otherwise determined in various manners, including based on dynamic instructions specified by the user, and on satisfaction of triggers that are previously defined by the user. In some situations, the techniques are used in conjunction with a fee-based program execution service that executes multiple programs on behalf of multiple users of the service.

Abstract: In the present invention, a management apparatus includes a unit configured to store management information including a throughput of each of a plurality of computers, a unit configured to acquire a request value which includes a throughput that is required for executing a program from a program execution computer to which execution of a program has been assigned among a plurality of computers, a selecting unit configured to select a computer of a throughput compliant with the request value from among a plurality of computers, and a switchover control unit configured to allocate the program allocated to the program execution computer to the selected computer.

Abstract: A memory management system for managing objects which represent memory in a multi-threaded operating system extracts the ID of the home free-list from the object header to determine whether the object is remote and adds the object to a remote object list if the object is determined to be remote. The memory management system determines whether the number of objects on the remote object list exceeds a threshold. If the threshold is exceeded, the system batch-removes the objects on the remote object list and then adds those objects to the appropriate one or more remote home free-lists.

Abstract: An apparatus includes a monitoring unit configured to monitor memory usage of a process in which multiple application programs are running, and a control unit configured to terminate one or more of the application programs when the memory usage of the process exceeds a first threshold.

Abstract: Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.

Abstract: A system is disclosed for rendering low latency resource objects by providing the latest position data from a central processing unit for the low latency resource object right before a graphic processing unit is to render the low latency resource object.

Abstract: A method and system are provided for performing the computational execution of automation tasks with automation devices by combining one or more central processing units (CPU) and one or more Graphics Processing Units (GPU). The control tasks and/or control algorithms are executed by the single-core or multi-core control unit (CPU) and a multi-core-graphics processor (GPU) or both in parallel at the same time.

Abstract: A recursive solution to a bin-packing algorithm provides efficient allocation of computing or communications resources to resource consumers in a computer or network system. The algorithm determines resource requirement vectors for the consumers that specify amounts of multiple resource types required for each consumer, thereby forming a multi-dimensional bin-packing problem. The algorithm assigns the resource consumers to corresponding groups of computing or communication resources by recursively exploring partial solutions that assign the consumers to the groups by extending the partial solutions via recursion until the requirements in the resource requirement vectors are met.

Abstract: A portable electronic apparatus includes an operating system comprising an application layer, an application framework layer, a libraries layer and a kernel layer. The application layer includes a cloud user interface allowing a user to perform an interactive function. The application framework layer includes a plurality of cloud components and at least a cloud service. The libraries layer includes a plurality of cloud managers. The kernel layer includes a cloud server driver, which is connected to the cloud managers to start the cloud service, so that the cloud service calls one of the cloud components according to the interactive function. By such configuration, the portable electronic apparatus of this invention can carry a private cloud to provide the service of a portable personal cloud.

Abstract: A method is proposed for exchanging a data set between a transmitting module, associated with a first domain, and a destination module associated with a second domain. The transmitting module and the destination module are adapted to be loaded into a browser module having access to a local database for recording data and accessing the data recorded by one or more modules belonging to a single browsing domain and to any module loaded in the browser module that is also associated with said single browsing domain. The method comprises the following steps: storage, by a storage module associated with a third domain, of the data set in the local database; requesting a receiving module, associated with the third browsing domain, to read the data set; reading, by the receiving module, of the data set in the local database.

Abstract: A graph processing system includes a graph API (Application Program Interface), as executed on a processor of a computer and as capable of implementing any of a plurality of graph operators to express computations of input graph analytics applications. A run-time system, executed by the processor, implements graph operators specified by each graph API function and deploys the implemented graph operators to a selected computing system. A library contains multiple implementations for each graph API function, each implementation predetermined as being optimal for a specific set of conditions met by a graph being processed, for functional capabilities of a specific computing system on which the graph is being processed, and for resources available on that specific computing system.

Abstract: Detecting stalling of a software process in a computer system includes receiving identification of a task thread group executing in a work process executing on a computer system. The task thread group includes one or more threads and the receiving includes receiving identification of the one or more threads by a control process executing on a computer system. The detecting includes detecting whether there is a thread state change for the task thread group, marking the task as running responsive to detecting a thread state change for the task thread group, marking the task as stalled responsive to detecting an absence of a thread state change for at least a predefined amount of time, and marking the work process as stalled responsive detecting an absence of a predetermined signal from the work process for at least a predefined amount of time.

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract: A system and method for processing an input data stream in a first data format of a plurality of first data formats to an output data stream in a second data format of a plurality of second data formats. A plurality of input connector modules receive respective input data streams and at least one input queue stores the received input data streams. A plurality of job threads is operatively connected to the at least one input queue, each job thread formatting a stored input data stream to produce an output data stream. At least one output queue stores the output data streams from the plurality of job threads. A plurality of output connector modules is operatively connected to the at least one output queue, the output connector modules supplying respective output data streams.

Abstract: A method, system and computer program product are provided for implementing distributed debug data collection and analysis for a hardware I/O adapter, such as, a Single Root Input/Output Virtualization (SRIOV) adapter in a virtualized system. A predetermined event triggers a base error collection sequence. Adapter driver data is collected and virtual function (VF) device drivers are locked out responsive to triggering the base error collection sequence. Adapter debug data is collected and the adapter is reinitialized including an indication to VF drivers if VF error data is to be collected. The virtual function (VF) device drivers are unlocked allowing the VF device drivers to commence recovery of a respective virtual function (VF).

Abstract: Subject matter disclosed herein relates to on-the-fly remapping a memory device by hardware-switching data paths to locations of the memory device.

Abstract: An adaptive network has respective network nodes and network connections between the network nodes, the network nodes each having a transceiver which is coupled with a respective network connection. The respective transceiver is designed for providing a mean error value (MSE_i) which is representative of deviations of a received signal from predefined reference signal values. In a reference operating state of the adaptive network, a respective reference error value (MSE_REF) is determined as a function of the mean error value (MSE_i) provided by the respective transceiver. In at least one predefined operating state of the adaptive network, a respective actual error value (MSE_AV) is determined as a function of the mean error value (MSE_i) provided by the respective transceiver.

Abstract: The present disclosure includes methods, devices, and systems for error detection or correction of stored signals in memory devices. An example method includes determining whether to perform error correction operations on contents of a non-volatile memory array. Determining whether to correct can include determining whether a level of errors in pre-programmed signals in the non-volatile memory array exceeds a bit error rate threshold, where the pre-programmed signals are different from the contents of the non-volatile memory array, and performing error correction on the contents of the non-volatile memory array if the level of errors exceeds the bit error rate threshold.

Abstract: An integrated circuit comprises a write bus coupled to a register for storing control data. A storage unit is arranged to store reference signature data encoding a reference collective state of the register. First logic circuitry generates actual signature data encoding the actual collective state of the register. Second logic circuitry is coupled to the storage unit, receives the actual signature data and compares the actual signature data with the reference signature data. The second logic circuitry comprises an alert output to provide an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register. An alert inhibitor comprises a control input and is responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output.

Abstract: An information processing apparatus according to one aspect of the present disclosure includes an input/output control portion and a restart control portion. The input/output control portion is configured to be able to have a plurality of electronic devices connected thereto, and is configured to control input/output between each electronic device and the information processing apparatus. The restart control portion is configured to switch whether to restart the input/output control portion in a case where an abnormality defined in advance has occurred with respect to an electronic device, in accordance with the number of the electronic devices connected to the input/output control portion.

Abstract: A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block.

Abstract: A content addressable memory (CAM) includes a first entry which includes one or more bits, a second entry which includes one or more bits, first comparison circuitry configured to compare each bit of a comparand to a corresponding bit of the one or more bits of the first entry and to provide a hit/miss indicator in response thereto, and second comparison circuitry configured to compare each bit of the one or more bits of the first entry to a corresponding bit of the one or more bits of the second entry and to provide a fault indicator in response thereto.

Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.

Abstract: A method and system for reducing data transfers between memory controller and multi-level cell (MLC) non-volatile memory during programming passes of a word line (WL) in the non-volatile memory. The system includes a controller and non-volatile memory having multiple WLs, each WL having a plurality of MLC memory cells. The controller stores received data in volatile memory until a target WL amount of data is received. The controller pre-encodes the received data into direct WL programming data for each programming pass necessary to program a target MLC WL. All direct WL programming data for all programming passes are stored in the volatile memory before programming. Different portions of direct WL programming data are transmitted from the controller to the non-volatile memory each pass. The received data may be deleted from the volatile memory before transmitting at least a portion of the direct WL programming data to the non-volatile memory.

Abstract: A method begins by a dispersed storage (DS) processing module sending a plurality of undecodeable portions of a plurality of data files via a public wireless communication network to one or more targeted devices of a private wireless communication network. The method continues with the DS processing module sending data content indicators regarding the plurality of data files and in response to a selection of a data file of the plurality of data files based on a corresponding one of the data content indicators, sending, via the private wireless communication network, one or more encoded data slices of each of one or more sets of encoded data slices of the data file such that, for each of the one or more sets of encoded data slices, the one or more targeted devices obtains at least a decode threshold number of encoded data slices to decode the data file.

Abstract: In one embodiment, a method includes receiving data. The method further includes splitting the data into a plurality of fixed-size blocks. Each block comprises a plurality of bytes. In addition, the method includes, for each block of the plurality of fixed-size blocks, calculating an error-correction byte. The method also includes appending the error-correction byte to the block as one of the plurality of bytes. Moreover, the method includes calculating, as part of the block, a parity bit for each of the plurality of bytes. Furthermore, the method includes separating the block into a plurality of bit streams that are perpendicular to the plurality of bytes. Each bit position of the block corresponds to one of the plurality of bit streams. Also, the method includes causing the plurality of bit streams to be stored on a plurality of storage elements in a bit-striped fashion.

Abstract: An apparatus including a storage array, a primary controller, a secondary controller and a solid state device. The storage array may be configured to be accessed by a plurality of controllers. A first of the plurality of the controllers may be configured as the primary controller configured to read and write to and from the storage array during a normal condition. A second of the plurality of the controllers may be configured as the secondary controller configured to read and write to and from the storage array during a fault condition. The solid state device may be configured to (i) store data and (ii) be accessed by the storage array and the secondary controller.

Abstract: A system for processing data comprises a deduplicating system, an interface, and a processor. The deduplicating system stores a copy of data stored in a data storage system by storing a set of segments that is able to reconstruct the data stored in the data storage system. The interface receives an indication to revert data stored in the data storage system to a state of data at a snapshot time stored in the deduplicating system. The processor is configured to determine a subset of the data stored in the data storage system that has changed between the data stored in the data storage system and the state of data at the snapshot time stored in the deduplicating system using a first list of fingerprints associated with the data stored on the data storage system and a second list of fingerprints associated with the state of data at the snapshot time stored in the deduplicating system.

Abstract: A Multi-Tenant Disaster Recovery Management System and method for intelligently and optimally allocating computing resources between multiple subscribers, the system comprising: one or more Multi-Tenant Disaster Recovery Management Server logically connected to one or more Production Site and one or more cloud based Disaster Recovery Site; a Network connecting said Multi-Tenant Disaster Recovery Management Server with said Production Site and said cloud based Disaster Recovery Site, wherein said Multi-Tenant Disaster Recovery Management Server is provided with at least one Disaster Recovery (DR) Manager Module, at least one Drill Scheduler Module, at least one Drill Executor Module, at least one WS Interface Module, at least one Usage Monitor Module and at least one Report Manager Module.

Abstract: Embodiments of the present invention disclose a method for recovery of a two-phase commit transaction. A computer transmits a first transaction identifier to a data store, wherein the first transaction identifier defines a two-phase commit transaction. The computer transmits a prepare command for the first transaction identifier to a first resource manager. The computer determines if a failure and restart occurred within a distributed data processing environment, wherein the failure and restart occurs after the first resource manager receives an end command, but prior to completing execution of the prepare command for the first transaction identifier. Responsive to determining the failure and restart did occur within the distributed data processing environment, the computer retrieves the first transaction identifier from the data store. The computer transmits a rollback command for the retrieved first transaction identifier to the first resource manager.

Abstract: Seamless failover in a database replication environment which has a primary database server and a plurality of standby database servers, is described. An example method includes orderly terminating transactions on the primary database server, where the transactions are originated from client applications. The transaction logs of the primary database server are drained and the transaction logs are replicated from the primary database server to the plurality of standby database servers. One of the standby database servers is designated as a new primary database server processing user transactions.

Abstract: The technology disclosed herein provides a method of verifying data read from a data block when the cell number of the data block does not match an ECC value stored in the data block. In particular, the method includes designating as unusable a data block in an indexed sequence of data blocks, wherein each data block is associated with a physical index; associating a cell number with a subsequent usable data block following the identified data block in the indexed sequence; and recording in an offset table accessible by an error detection and correction module an offset in association with the cell number of the subsequent usable data block, wherein the combination of the offset and the cell number represents a seed for the error detection and correction module.

Abstract: A method of providing high integrity communication in a high integrity processing system having at least two redundant application processors in a non-lockstep configuration where the redundant application processors are running the same application and where the redundant application processors are connected to at least one input/output processor by a communication channel.

Abstract: A storage system is provided with a plurality of physical storage devices, a cache memory, a control device that is coupled to the plurality of physical storage devices and the cache memory, and a buffer part. The buffer part is a storage region that is formed by using at least a part of a storage region of the plurality of physical storage devices and that is configured to temporarily store at least one target data element that is to be transmitted to a predetermined target. The control device stores a target data element into a cache region that has been allocated to a buffer region (that is a part of the cache memory and that is a storage region of a write destination of the target data element for the buffer part). The control device transmits the target data element from the cache memory.

Abstract: In an embodiment, a method provides first and second storage pools having a plurality of corresponding storage blocks to a storage solution. The method monitors each storage block of the first plurality for an indication of failure by either (a) simultaneously writing a same data to a storage block of the first plurality and a corresponding storage block of the second plurality and, if writing the same data to the corresponding storage block of the second plurality completes before writing the same data to the storage block of the first plurality, indicating the first plurality of storage to be failed or (b) employing an internal procedure of the storage solution. The method, upon determining the indication, replaces the storage block with an unused storage block from a plurality of backup storage blocks or declaring the entire storage solution at a lower performance level.