Abstract: Cache control is provided. A request for ownership of a requested cache line is received from a first processing node. The requested cache line is owned by a second processing node. A coherency message is issued to the second processing node. A shared buffer is caused to store a speculative copy of the requested cache line. Whether a change to the requested cache line occurred is determined. At least one of the requested cache line or the speculative copy is assigned to the first processing node.

Abstract: Maintaining store order with high throughput in a distributed shared memory system. A request is received for a first ordered data store and a coherency check is initiated. A signal is sent that pipelining of a second ordered data store can be initiated. If a delay condition is encountered during the coherency check for the first ordered data store, rejection of the first ordered data store is signaled. If a delay condition is not encountered during the coherency check for the first ordered data store, a signal is sent indicating a readiness to continue pipelining of the second ordered data store.

Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include initializing, by a processor executing a file system in communication with a block manager managing multiple storage regions on a storage device, a file system write cache to have a default cache size, the default cache size corresponding to a first storage capacity of a default number of the storage regions. Upon detecting that a current number of the storage regions that are not in use by the block manager is less than the default number, the file system write cache is resized to a reduced cache size that corresponds to a second storage capacity of the current number of the storage regions. While the file system write cache has the reduced cache size, the file system write cache can be resized back to the default cache size as unused storage regions become available.

Abstract: A high performance instruction cache method for facilitating operation of a processor core coupled to a first memory containing executable instructions, and a second memory with a faster speed than the first memory is provided. The method includes examining instructions from the first memory filled into the second memory and extracting instruction information containing at least branch information. The method also includes creating a plurality of tracks based on the extracted instruction information. Further, the method includes filling at least one or more instructions that are possibly executed by the processor core from the first memory into the second memory based on one or more tracks from a plurality of instruction tracks.

Abstract: Techniques are generally described for cache management in a processor with a cache. In response to receiving a bulk memory modification instruction, data blocks of the cache associated with the bulk memory modification instruction may be identified. A cache coherence state of the identified data blocks may also be identified. The updated cache coherence state may be indicative of a zero value of the data blocks and the cache coherence state of the identified data blocks may be updated without modification to a cache data array.

Abstract: Storage tracks from at least one host are destaged from the write cache rank when it is determined that the at least one host is idle with respect to a first set of ranks, and storage tracks are refrained from being destaged from each rank when it is determined that the at least one host is not idle with respect to a second set of ranks.

Abstract: Store merge processing device stores a plurality of entries, with regard to a plurality of first write instructions that are a plurality of write instructions issued by an external device, have access addresses including upper and lower addresses, of which upper addresses are equal and have equal block sizes for writing data to a storage, the entries including identification information for identifying a block size, a plurality of pieces of block data, address information indicating an upper address, and storage information indicating a storage state for each piece of the block data in association with one another; and when the entries include an entry of which identification and address information matches those of a second write instruction, writes the block data included in the second write instruction in a position specified by the access address in the entry, and updates the storage information regarding the block data.

Abstract: Disclosed herein is a digital rights management system that includes a storage module that stores a usage right for digital content in a tamper-resistant portion of a memory. The system also includes a flag status module that generates a flag corresponding with a transfer status of the usage right, sets the flag to one of a plurality of transfer statuses, and stores the flag in the tamper-resistant portion of the memory. The transfer statuses include a status indicating a request for the usage right was generated by a device with a usage right recovery mechanism.

Abstract: A device includes: a storage medium control unit provided for each type of storage medium to at least read out information from the storage medium; a linkage unit that determines an application program corresponding to a type of a storage medium from which information is to be read out, through a first acquisition unit that acquires first correspondence information in which each application program is associated with a type of a storage medium from which the application program uses information, and determines a storage medium control unit corresponding to the type of the storage medium, through a second acquisition unit that acquires second correspondence information in which a storage medium control unit is associated with a type of a storage medium from which the storage medium control unit can read out information; and a management unit that enables the determined application program to use the determined storage medium control unit.

Abstract: A processor for processing stream data at a high speed is provided. The processor may include a functional unit to perform an operation on the stream data, an input interface module to perform relaying between the functional unit and an external data producer module that is used to input the stream data to the processor, and an output interface module to perform relaying between the functional unit and an external data consumer module that is used to receive an input of result data regarding a result of the operation performed by the functional unit.

Abstract: The application discloses a buffer device and a method for controlling data access to an internal memory. The buffer device has a central buffer module coupled to a memory interface to receive a command/address signal via a command/address channel. The central buffer module is configured to detect whether a destination address of the received command/address signal is within a predefined address space, and generate a security read/write signal when the command/address signal is within the predefined address space. The buffer device further has a data buffer module coupled between the memory interface and a memory module to buffer data therebetween. The data buffer module is configured to store reference data, compare the buffered data with the reference data in response to the security read/write signal, and determine whether or not to restrict exchange of the buffered data between the memory module and the memory interface.

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

Abstract: A modular control apparatus, having a head module, and at least one supply module and peripheral module arranged on the head module and having a bus structure. The supply module and the peripheral module have a base module part, an electronic module part and a connection module part. The base module parts are arranged next to one another and provide the bus structure that electrically couples the head module, the supply module and the peripheral module to one another. The supply module additionally comprises an electrical line that runs from the connection module part through the electronic module part to the base module part and connects the supply connection of the supply module to the bus structure. An overload identification unit is arranged at the electrical line and determines a parameter of the electrical line and produces a warning signal if the parameter exceeds a threshold value.

Abstract: A system includes a host device, an external bus and a storage device. A driver is installed in the host device. The external bus is connected with the host device. The external bus supports a communication protocol. The storage device includes a controlling circuit and a non-volatile memory. After the storage device issues a request to the host device according to the communication protocol, a reserved space is created in a host memory of the host device in response to the request, and a device information from the storage device is stored into the reserved space. While the host device issues a first command to operate the storage device, the first command is converted into a second command by the driver according to the device information, and then the second command is transmitted to the storage device.

Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to assert an in-band IRQ. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

Abstract: A system includes: a first processor; a second processor; and a communication bus configured to couple the first processor and the second processor; wherein the first processor is configured to obtain a bus usage rate by monitoring a delay time period of data transfer in the communication bus, determine whether to offload a processing on received data based on the monitored bus usage rate, and offload the processing to the second processor when the processing is determined to be offloaded.

Abstract: Reversible connectors for accessory devices are described. In one or more implementations, a connector cable for an accessory of a host computing device is configured such that a head of the connector cable may be plugged into a corresponding port of the host in either orientation (straight or reverse). The host computing device is configured to sample signals associated with allocated pins of the connector to detect connection of the connector to an accessory port and to ascertain an orientation of the connector. A combination of high and low values of signals conveyed via these allocated pins upon insertion of the connector may be used by a controller of the host to distinguish between different types of devices and to resolve the orientation of the connector cable. A switching mechanism of the host computing device may then be configured to automatically route signals accordingly.

Abstract: A High Speed Link System providing network and data transfer capabilities, implemented via standard input/output (I/O) device controllers, protocols, cables and components, to connect one or more Host computing systems, comprising a System, Apparatus and Method is claimed; and described in one or more embodiments. An illustrative embodiment of the invention connects two or more Host systems via USB 3.0 ports and cables, establishing Network, Control, Data Exchange, and Power management required to route and transfer data at high speeds, as well as resource sharing. A Link System established using USB 3.0 operates at the full 4.8 Gbps, eliminating losses inherent when translating to, or encapsulating within, a network protocol, such as the Internet Protocol. Method claimed herein describes how two or more connected Host systems, detect one another, and establish separate communication and data exchange bridges, wherein control sequences from the Hosts' application direct the operation of the Apparatus.

Abstract: An input/output control device is connected to an input/output switch which transfers a received input/output instruction to an input/output device whose local address is specified in the input/output instruction. The input/output control device includes a memory and circuitry. The memory stores specific information about a processor and a conversion table for converting a logical address of the input/output device into the local address, with the specific information and the conversion table each being associated with a device group that includes the processor and the input/output device. The circuitry identifies the device group based on the specific information about the processor of sender which information is obtained. The circuitry converts the logical address included in the input/output instruction into the local address which is obtained from the conversion table for the identified device group, and then sends the input/output instruction to the input/output switch.

Abstract: A signal interface unit for use on an aircraft includes a microcontroller, at least one connector, and first and second communication links. The first communication link is connected between the microcontroller and the at least one connector. The microcontroller is configured to transmit and receive data on the first communication link. The second communication link is connected to the microcontroller. The microcontroller is configured to send and receive data on an aircraft data bus using the second communication link.

Abstract: A method and apparatus are provided for implementing modal selection of a bimodal coherent accelerator in a computer system. Implementing modal selection of a bimodal coherent accelerator using a PCI-Express standard Vendor Specific Extended Capability (VSEC) structure or CAPI VSEC data in the configuration space of a CAPI-capable PCIE adapter and procedures defined in the Coherent Accelerator Interface Architecture (CAIA) to enable and control a coherent coprocessor adapter over PCIE. A CAPI-capable PCIE adapter is enabled to be bimodal and operate in conventional PCI-Express (PCIE) transaction modes or CAPI modes that utilize CAIA coherence and programming interface capabilities.

Abstract: A computing system for housing a number of storage devices includes a number of device cages, and a backplane coupled to each of the device cages to electrically couple a number of the storage devices to the computing system. The backplane includes a number of device combination signal and power interfaces located on a first side of the backplane to couple a number of the storage devices to the backplane. The backplane further includes a number of combination signal and power interfaces located on a second side of the backplane to couple the backplane to the computing system. The backplane further includes a number of signal connectors to couple the backplane to the computing system.

Abstract: Systems and methods for managing name assignments in a Fibre Channel (FC) storage arrays are provided. One example method includes receiving a port name for a slot of a controller of the FC storage array. The slot of the controller is configured to receive an FC card for providing communication between the FC storage array and an FC fabric. The method includes binding the port name to the slot of the controller, and the port name is saved to a database managed by the controller. The method further includes assigning the port name to the FC card when installed in the slot. The FC card is swappable with other FC cards, and thus other FC card will also maintain the port name of the slot.

Abstract: A data storage device may comprise a first non-volatile memory, configured to store storage System-On-Chip (SOC) data and protocol bridge data; a storage SOC comprising circuitry configured to control the data storage device and to, upon power-on, retrieve the storage SOC data from the first non-volatile memory and configure itself according to the retrieved storage SOC data; a bus coupled to the storage SOC; and a protocol bridge coupled to the bus and comprising circuitry configured to translate between a first and a second communication protocol and to, upon power-on, retrieve the protocol bridge data from the first non-volatile memory via the storage SOC and the bus and configure itself according to the retrieved protocol bridge data.

Abstract: Systems and techniques for single-wire communications are described. A described system includes a host device, and a slave device coupled with the host device via a single-wire bus. The host device can be configured to transmit synchronization information based on transitions over the single-wire bus. The slave device can be configured to detect the transitions on the single-wire bus, determine timing information of the host device based on a first transition of the transitions and a second transition of the transitions, determine a predicted start time of a host sampling window based on the timing information, and determine, based on a predicted charging duration, whether to perform a charge operation before the predicted start time or after a predicted end time of the host sampling window. The charge operation can include drawing power from the single-wire bus to charge the device.

Abstract: A method and apparatus are provided for implementing modal selection of a bimodal coherent accelerator in a computer system. Implementing modal selection of a bimodal coherent accelerator using a PCI-Express standard Vendor Specific Extended Capability (VSEC) structure or CAPI VSEC data in the configuration space of a CAPI-capable PCIE adapter and procedures defined in the Coherent Accelerator Interface Architecture (CAIA) to enable and control a coherent coprocessor adapter over PCIE. A CAPI-capable PCIE adapter is enabled to be bimodal and operate in conventional PCI-Express (PCIE) transaction modes or CAPI modes that utilize CAIA coherence and programming interface capabilities.

Abstract: A circuit device includes a detection circuit adapted to output first through n-th detection data, and a serial interface adapted to output the first through n-th detection data as serial data. In the case in which i-th detection data (1?i?n) out of the first through n-th detection data is M bits, and j-th detection data (1?j?n, j?i) is N bits (N<M), the serial interface outputs the serial data added with (M?N) complementary bits on an MSB side of the j-th detection data.

Abstract: An electronic device and method of communication using a USB interface through full duplex transmission are disclosed. A method of performing data communication by an electronic device includes detecting a connection of an electronic device through an interface, configuring the electronic device as a host or a slave for data communication of first data in response to the connection of the electronic device, performing first data communication based on a first communication path according to a first standard for the first data in response to detecting the configuration, detecting performance of data communication of second data while the data communication of the first data is performed, configuring the electronic device as the host or the slave for the data communication of the second data and performing second data communication based on a second communication path according to a second standard for the second data in response to the configuration.

Abstract: In one embodiment, a system includes non-volatile memory (NVM) configured to store data, a memory controller connected to the NVM via a NVM interface, a network interface card (NIC) connected to the memory controller, a processor, the logic being configured to: initiate cluster parameters that govern how a NVM cluster will function and operate, multicast cluster parameters of the NVM cluster at predetermined intervals to any other node in the NVM cluster, and map submission and completion queues of any shared NVM on other nodes in the NVM cluster to the memory controller based on details of the shared NVM on the other nodes in the NVM cluster, wherein the submission queue is configured to store commands to access the shared NVM and the completion queue is configured to store completed commands after being processed through the submission queue.

Abstract: Systems and methods for transforming a Central Processing Unit (CPU) socket into a memory and/or Input/Output (I/O) expander. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a plurality of CPU sockets, each of the CPU sockets having one or more cores, and each of the one or more cores being associated with a respective one or more electronic circuits, the one or more electronic circuits including at least one of: a memory controller or an input/output (I/O) controller; and a Basic Input/Output System (BIOS) circuit coupled to the plurality of CPU sockets, the BIOS circuit having access to program instructions that, upon execution by the BIOS, cause the IHS to: initialize the plurality of CPU sockets; and report an electronic circuit associated to a first core of a first CPU socket as being instead associated with a second core of a second CPU socket.

Abstract: Methods and apparatuses for automatically generating a mobile-optimized website from an existing website are disclosed.

Abstract: Techniques are described for outputting web page components, or gadgets, on a web page or other graphical user interface. A gadget automatically conforms to particular styles based on the styles of the other gadgets and of controlling relationships to the other gadgets that are determined from page analysis and other policies.

Abstract: A system and method for bifurcated presentation of e-content on an e-reading device is disclosed. One embodiment includes a primary display of an e-reading device for presenting a page of an e-book thereon. In addition, a secondary display is also coupled with the e-reading device for presenting a portion of the page of the e-book thereon, wherein the primary display and the secondary display are not concurrently visible from a same plane of view.

Abstract: Methods, apparatuses, systems, and computer-readable media are provided for associating audio information with a web page. A graphical interface includes a representation of audio content and enables a user of a client computer to select marker locations in the audio content such that each of the marker locations identify respective temporal locations in the audio content. A set of marker embed instructions is automatically generated for the marker locations. The marker embed instructions are transmitted to the client computer for insertion into browser instructions for the web page to generate one or more selectable graphical markers on the web page. Each of the one or more selectable graphical markers on the web page is associated with a marker location in the audio content and used to initiate playback of a selected portion of the audio content.

Abstract: A computer processor circuit can be used to receive a resizing request that includes parameters for resizing a user interface containing a plurality of visual elements. In response to the request, the computer processor circuit can access a set of one or more data files specifying: links to binary image data files for the plurality of visual elements; a set of nodes forming a plurality of vector paths for at least one of the plurality of visual elements; and a set of rules defining different image resizing properties for different vector paths of the plurality of vector paths. The computer processor circuit can then create a resized version of the user interface by modifying the plurality of visual elements according to the set of rules and to the parameters for resizing.

Abstract: An information processing apparatus identifies a plurality of tag sections and a plurality of original text sections in input character data that includes a tag having a variable section. The information processing apparatus converts each of a plurality of tags included in the plurality of tag sections into a plurality of first-type codes that respectively corresponds to tag contents of the plurality of tags. The information processing apparatus converts original texts in the plurality of original text sections into a plurality of second-type codes. The information processing apparatus outputs an encoded data including the plurality of first-type codes and the plurality of second-type codes, positional relationships of the plurality of tags and the original texts in the input character data being maintained with corresponding plurality of first-type codes and corresponding plurality of second-type codes in the encoded data.

Abstract: A user-initiated data recognition and data conversion process allows for the conversion of unstructured data to structured data from a capture of an optical character recognition image with the unstructured data underneath. A method for converting unstructured data to structured data includes uploading a digital representation of a document to an optical character recognition server, scaling the digital representation of the document to fit the display size of a mobile device, using a touch interface to select unstructured data from the scaled digital representation of the document, populating the selected unstructured data in an electronic record to create structured data, and storing the structured data on a remote server.

Abstract: A syllabus editing system is described hereafter for editing a course syllabus. The syllabus editing system aids the user in adjusting what learning objects are included in a syllabus. The system further checks dependency violations in an edited syllabus, where a dependency violation occurs when fundamental concepts for a particular learning object are not presented prior to the particular learning object within the flow of the syllabus. Embodiments provide information about detected dependency violations, information about learning objects that may be used to correct the dependency violations, and information helpful in aiding a user in editing the syllabus intelligently. Furthermore, embodiments provide an option to automatically correct dependency violations. Such an automatic correction involves identifying one or more solutions to the dependency violation.

Abstract: Disclosed is a screenshot processing method including: generating a screenshot of a displayed screen; determining at least one target area, to which a preset function is added, from a whole area of the generated screenshot; and generating a screenshot file where data for executing the preset function is combined with the screenshot.

Abstract: A server device, including: a document acquisition unit configured to acquire a document including a reference to a resource in response to a client request; a resource acquisition unit configured to acquire the resource; an abbreviated character string generation unit configured to generate abbreviated character strings of character strings included in the document and the resource and add records associating the character strings with the abbreviated character strings; an abbreviated character string writing unit configured to replace the character strings with the abbreviated character strings in the document and the resource; a document transmission unit configured to transmit the document including the abbreviated character string to the client; and a resource transmission unit configured to transmit the resource including the abbreviated character string to the client. The server device speeds up provision of a document to a client by utilizing throughput of a server.

Abstract: Techniques are disclosed for facilitating the process of undoing and redoing modifications that are made to content using an online content management system (CMS). As a user makes changes to content, such as by editing a webpage using a web-based CMS, a history of the user's modifications is generated and stored locally on the client. When the user invokes an undo command, the modification history can be used to determine a previous state of the content and restore the content to that previous state. Similarly, when the user invokes a redo command, the modification history can be used to return to a state that had previously been undone. In some embodiments, the process of undoing or redoing the user's modifications is selectively performed on either a client side or a server side of the online system, depending on the type of content that is being manipulated.

Abstract: Systems and methods for selectively erasing a portion of an electronic document are provided. An example method includes: receiving a user selected area of the electronic document that includes information to be erased, where the electronic document includes a background portion; determining whether the user selected area includes a corresponding text layer; and responsive to determining that the user selected area comprises the text layer, erasing a text portion corresponding to the text layer without modifying the background portion, where erasing the text portion includes coloring the text portion based on a color of the background portion that is adjacent to the text portion.

Abstract: Improved authoring techniques enable digital forms to be configured so as to facilitate subsequent analysis of how specific consumer segments interact with such forms. As a form author defines and manipulates the fields that comprise a form, selected fields can be designated as dimensions across which metrics can be analyzed. Depending on the particular type of data being collected, author-designated dimensions are optionally transformed into more meaningful categories. For instance, a “household income” field can be transformed into lower- and higher-income segments. If the form author wishes to later analyze metrics such as interaction time and errors encountered, consumers can be segmented on the basis of such dimensions. For example, the form author may understand which income segment requires the most time to complete a form. In general, this provides information with respect to how certain segments interact with a digital form, thereby enabling form authors to improve consumer experience.

Abstract: Techniques are disclosed for identifying and populating static form fields using prior responses to similar form fields. An example method includes receiving an electronic form having, encoded in the form, static text and a static form field for containing information specific to a given user of the electronic form. Using an image recognition algorithm, a fillable form field candidate is identified based on a graphical representation of the static form field. An attribute of the fillable form field candidate can be identified based on the static text. A suggested response for populating the fillable form field candidate is selected from prior responses to other form fields having at least one attribute in common with the identified attribute of the fillable form field candidate. The prior responses are inputs obtained from or associated with the given user. The suggested response is presented to the user for subsequent acceptance or rejection.

Abstract: According to various embodiments of the disclosure techniques for generating outgoing messages are disclosed. The technique includes receiving a request to generate an outgoing message for a recipient and retrieving one or more recipient preferences of the recipient from a recipient preferences database. The one or more recipient preferences relate to customization of messages that are to be delivered to the recipient. The technique further includes retrieving a message template from a plurality of message templates stored in a message template database based on the request and the one or more recipient preferences. The technique also includes generating the outgoing message based on the retrieved message template and the one or more recipient preferences, and providing the outgoing message to the recipient.

Abstract: An example method for generating a regular expression includes: acquiring a preset character string; acquiring a to-be-collected character string in the preset character string in response to a trigger instruction; recognizing a character string before the to-be-collected character string from the preset character string, the character string before the to-be-collected character string being used as a first character string; recognizing a character string after the to-be-collected character string from the preset character string, the character string after the to-be-collected character string being used as a second character string; and generating a regular expression of the to-be-collected character string by a first preset rule according to character features of the to-be-collected character string, the first character string and the second character string. The techniques of the present disclosure generate the regular expression of the character string needed by a user.

Abstract: Disclosed is a device for generating an aligned corpus based on unsupervised-learning alignment, and a method thereof, a device for analyzing a destructive expression morpheme using an aligned corpus, and a method for analyzing a morpheme thereof. The morpheme analyzing device includes a knowledge database and an analyzer. The knowledge database includes an aligned corpus for storing a plurality of knowledge information sets used for a per-language morpheme analysis, and stores a morpheme dictionary for storing morpheme information corresponding to a normal expression and normal expression information corresponding to a destructive expression (here, the destructive expression represents an expression that is erroneous in orthography or is not normalized and standardized).

Abstract: The current document is directed to methods and systems for identifying symbols corresponding to symbol images in a scanned-document image or other text-containing image, with the symbols corresponding to Chinese or Japanese characters, to Korean morpho-syllabic blocks, or to symbols of other languages that use a large number of symbols for writing and printing. In one implementation, the methods and systems to which the current document is directed create and store a decision tree, the nodes of which include classifiers that each recognizes the symbol that corresponds to a symbol image. Input of a symbol image to the decision tree and processing of the symbol image through one or more nodes of the decision tree returns a symbol corresponding to the symbol image.

Abstract: Analysis of incomplete natural language expressions using n-gram analysis and contextual information allows one or more domains to be predicted. For each domain, intent a likely intent of the user is determined using n-gram analysis and contextual information. Intent may correspond to functions of a domain application. In such a case, information required for the functions to execute the application may be populated using n-gram analysis and/or contextual information. The application may then be presented to the user for confirmation of intent. Confirmation of intent along with the incomplete natural language expression and contextual information may then be used to train one or more models used to predict user intent based on incomplete natural language expressions.

Abstract: Examples of the present disclosure describe generation of a multi-arc confusion network to improve, for example, an ability to return alternatives to output generated. A confusion network comprising token representations of lexicalized hypotheses and normalized hypotheses is generated. Each arc of the confusion network represents a token of a lexicalized hypothesis or a normalized hypothesis. The confusion network is transformed into a multi-arc confusion network, wherein the transforming comprising realigning at least one token of the confusion network to span multiple arcs of the confusion network. Other examples are also described.