Abstract: A driver includes a driving block suitable for driving a data transferred through a first signal line to a second signal line, a first precharge unit suitable for precharging the second signal line with a first driving power during a first precharge operation; and a second precharge unit suitable for precharging the second signal line with a second driving power which is different from the first driving power during a second precharge operation performed subsequent to the first precharge operation.

Abstract: An apparatus having a circuit and a decoder is disclosed. The circuit is configured to adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.

Abstract: A semiconductor device may include: a plurality of data pads; a plurality of data buffers each suitable for buffering a signal inputted through a first input node using a voltage inputted through a second input node, and outputting the buffered signal; and a calibration control unit suitable for generating a test signal in a calibration mode, adjusting the level of the test signal, receiving outputs of the plurality of data buffers while adjusting the level of the test signal, and adjusting offsets of the data buffers such that the logical values of the outputs of the data buffers transit when the test signal has a target level.

Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix.

Abstract: A memory device includes a memory array having a plurality of rows and columns of array blocks disposed in array block areas, array blocks including sub-arrays of memory cells arranged in rows and columns with word lines disposed in a patterned gate layer along the rows and one or more patterned conductor layers including bit lines disposed along the columns. A plurality of sets of local word line drivers is arranged in rows and columns disposed adjacent to corresponding array blocks. A set of global word line drivers driving global word lines disposed in an overlying patterned conductor layer over the one or more patterned conductor layers in the array blocks.

Abstract: A semiconductor apparatus includes a plurality of memory blocks divided into an even mat group and an odd mat group; and an active control block configured to activate any one group of the even mat group and the odd mat group at a first timing in response to a plurality of test signals, and activate the other group at a second timing.

Abstract: Provided is a semiconductor device. The semiconductor device includes memory blocks including select transistors electrically coupled to local select lines and memory cells electrically coupled to local word lines, a first connection circuit configured to electrically couple the local select lines of a selected memory block and global select lines according to a block select signal, and formed in a first well region of a substrate, and a second connection circuit configured to electrically couple the local word lines of the selected memory block and global word lines according to the block selection signal, and formed in a second well region of the substrate.

Abstract: In an approach for storing frames of a video, a computer divides a video into one or more frames. The computer identifies a frame type associated with an individual frame within the divided one or more frames, wherein the identified frame type includes one of the following: an I-frame, a B-frame, and a P-frame. The computer stores the individual frame within a corresponding storage location based on the associated identified frame type.

Abstract: Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.

Abstract: A magnetic device includes a first magnetic layer, known as storage layer, having a uniaxial anisotropy with an easy magnetization axis in the plane of the storage layer and having a magnetization of variable direction having two positions of equilibrium along the easy magnetization axis, a second magnetic layer, known as electron spin polarization layer, having a magnetization perpendicular to that of the storage layer and situated out of plane of the electron spin polarization layer, a device configured to make circulate in the layers, and perpendicularly thereto, a current to switch from one position of equilibrium of the direction of magnetization of the storage layer to the other. The device further includes a device to apply a magnetic field, known as transverse field, the direction of which is substantially parallel to the plane of the storage layer and substantially perpendicular to the easy magnetization axis of the storage layer.

Abstract: A method includes, at a resistive memory device, determining an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance. The first effective reference resistance is based on a first set of reference cells of the resistive memory device and the second effective reference resistance is based on a second set of reference cells of the resistive memory device. The method includes trimming a reference resistance at least partially based on the average effective reference resistance level. Trimming the reference resistance includes, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance.

Abstract: Aspects for adjusting resistive memory write driver strength based on write error rate (WER) are disclosed. In one aspect, a write driver strength control circuit is provided to adjust a write current provided to a resistive memory based on a WER of the resistive memory. The write driver strength control circuit includes a tracking circuit configured to determine the WER of the resistive memory based on write operations performed on resistive memory elements. The write driver strength control circuit includes a write current calculator circuit configured to compare the WER to a target WER that represents the desired yield performance level of the resistive memory. A write current adjust circuit in the write driver strength control circuit is configured to adjust the write current based on this comparison. The write driver strength control circuit adjusts the write current to perform write operations while reducing write errors associated with breakdown voltage.

Abstract: Techniques and circuits for storing and retrieving data using spin-torque magnetic memory cells as anti-fuses are presented. Circuits are included to allow higher-magnitude voltages and currents to be applied to magnetic memory cells to intentionally break down the dielectric layer included the magnetic tunnel junction. Magnetic memory cells having a normal-resistance magnetic tunnel junction with an intact dielectric layer are used to store a first data state, and magnetic memory cells having a magnetic tunnel junction with a broken-down dielectric layer are used to store a second data state. Data can be stored in such a manner during wafer probe and then later read out directly or copied into other magnetic or non-magnetic memory on the device for use in operations after the device is included in a system.

Abstract: A semiconductor device includes a memory cell array including a normal memory cell array and a redundancy memory cell array, a normal refresh counter suitable for generating a normal address for performing a refresh operation to the normal memory cell array with a first period during a refresh mode and a redundancy refresh counter suitable for generating a redundancy address for performing a refresh operation to the redundancy memory cell with a second period shorter than the first period.

Abstract: A storage control device includes: a partial unit buffer configured to hold at least one data assigned to a partial unit, in which the partial unit is one of a plurality of partial units that are each a division of a write unit for a memory; and a request generation section configured to generate, upon indication of a busy state in the memory for any of the partial units, a write request for the write unit of the memory when the holding of the data assigned to that partial unit is possible in the partial unit buffer.

Abstract: A memory device may include a power-up control circuit and a first set of boost voltage generators. The power-up control circuit may be configured to consecutively activate a first set of power-up signals with a first delay time between each power-up signal of the first set of power-up signals in response to a rise of a power supply voltage and a reset signal having a first logic level at an initial stage of power-up. The first set of boost voltage generators may be configured to generate an internal boost voltage based on an external boost voltage and the first set of power-up signals. The first set of boost voltage generators may be configured to activate before the reset signal transitions from the first logic level to a second logic level opposite to the first logic level.

Abstract: One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles. The command receiver is activated based on a first control signal. The first control signal is activated in response to the first internal chip select signal. The first control signal is deactivated in response to the second control signal.

Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

Abstract: Systems, methods, and other embodiments associated with improving a static noise margin of memory cells by using charge sharing to under-drive a wordline are described. In one embodiment, a system includes power logic to, in response to a memory request, connect a voltage source with a virtual power network to store an electric charge within the virtual power network based on a voltage from the voltage source. The virtual power network includes a network of interconnects that electrically connect a plurality of driver interconnects. The system includes wordline logic to under-drive a requested wordline of a plurality of wordlines by connecting the requested wordline with the virtual power network to share the electric charge stored in the virtual power network with the requested wordline. The wordline logic under-drives a voltage of the requested wordline to be lower than a source voltage provided by the voltage source.

Abstract: A semiconductor memory device according to an embodiment includes first and second storages that enable writing and reading of data. The first decoding line and the third decoding line are electrically connected to each other. The first bit line and the third bit line are electrically connected to each other.

Abstract: A static random access memory (SRAM) including at least a memory cell array, a first data line connected to the memory cell array, and a read assist unit connected to the first data line. The read assist unit is configured to suppress a voltage level of the first data line during a read operation of the memory cell array.

Abstract: An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.

Abstract: An integrated circuit (IC) device can include a memory array section comprising a plurality of memory arrays that each include memory cells for storing data values; a data path section having switching circuits configured to enable data paths between the memory arrays and a plurality of input/outputs (I/Os) of the IC device; and a power fill control circuit configured to activate power-fill circuits in the IC device to perform non-mission mode operations that consume current, the amount of non-mission mode operations varying in response to mission mode circuit activity in the IC device; wherein mission mode circuit activity includes circuit activity resulting from a user input to the IC device.

Abstract: A memory is provided with a write assist circuit that responds to an indication that a write operation on a modeled memory cell is successful by releasing a negative bit line boost.

Abstract: Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.

Abstract: Invention provides an apparatus and method for performing signal processing on a crossbar array of resistive memory devices. The invention is implemented using one or multiple crossbar arrays of resistive memory devices in conjunction with devices for converting input real number representations to voltage waveforms, devices for converting current waveforms into voltage waveforms, and devices for converting voltage waveforms to real numbers outputs.

Abstract: A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.

Abstract: A semiconductor integrated circuit device and a system including the same, configured for sensing a pure leakage current of a cell array and improving a read error is disclosed. The system a controller and a memory configured to interface with the controller. The memory includes a semiconductor integrated circuit device includes a leakage current sensing unit configured to sense a pure leakage current of a cell array according to a command of the controller; and a determination circuit unit configured to compare a voltage level of an input node with a reference voltage and determine a state of read data while in a read mode. The voltage level of the input node is decided by comparing an output current and a read current and the output current is decided by summing the pure leakage current and a reference current.

Abstract: Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.

Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.

Abstract: Embodiments include a system, an apparatus, a device, and a method. The apparatus includes a processor, a dynamic memory, and a hardware-implemented memory control circuit. The hardware-implemented control circuit includes a control circuit for establishing an extended refresh period of the dynamic memory based at least in part on a monitored result that indicates an occurrence of a memory loss in the dynamic memory. The hardware-implemented control circuit also includes a control circuit for causing a refresh of the dynamic memory during each of at least two extended refresh periods.

Abstract: A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.

Abstract: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

Abstract: A storage module and method are provided for using healing effects of a quarantine process. In one embodiment, a storage module is provided comprising a controller and a memory. The controller is configured to identify a set of memory cells in the memory that contains a bit error rate above a threshold, wherein the bit error rate is above the threshold due to trapped charge in dielectrics of the memory cells. The controller is also configured to quarantine the set of memory cells for a period of time, wherein while the set of memory cells is quarantined, heat generated by the storage module anneals the set of memory cells to at least partially remove the trapped charge.

Abstract: A charge pump system includes a plurality of pump units, a control circuit, and a detection circuit. The plurality of pump units are used for generating a pump output voltage. The control circuit is coupled to the plurality of pump units and is used for controlling each pump unit of the plurality of pump units. The detection circuit is coupled to the control circuit and the plurality of pump units and is used for detecting the pump output voltage. When the pump output voltage is greater than a predetermined value, the detection circuit generates and latches a control signal to enable the control circuit. After the control circuit is enabled, when the pump output voltage is detected to be smaller than the predetermined value, the detection circuit generates a first pump enable signal to the control circuit for enabling a first pump unit of the plurality of pump units.

Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

Abstract: A method of protecting data of a flash memory is provided. The method includes detecting primary power applied to the flash memory, and applying secondary power converted from the primary power to the flash memory. The primary power is compared to first and second values, and a writing-protection pin of the flash memory is enabled when the detected primary power reaches a predetermined value.

Abstract: Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.

Abstract: A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. The controller is configured to cause the memory device to apply a programming pulse to control gates of the group of memory cells. The controller is configured to determine an amount of disturb experienced by the group of memory cells responsive to the programming pulse. The controller is configured to determine a program window responsive to the amount of disturb.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program pulse applying operation and a verify operation on the memory cell array, a pass/fail check circuit performing a pass/fail check operation on a program operation including the program pulse applying operation and the verify operation, and a control logic controlling the peripheral circuit and the pass/fall check circuit to perform the pass/fail check operation during the program pulse applying operation.

Abstract: The present invention provides a method and apparatus that includes a timing device circuit for generating a timing signal, a RAM coupled to the timing device circuit, an OTP NVM and selection logic. The RAM is operable upon receiving a burn address to read configuration data in the RAM beginning at the burn address and the OTP NVM is operable to burn the configuration data read from RAM into the OTP NVM. The OTP NVM is configured to read configuration data in the OTP NVM and the RAM is configured to store the configuration data from the OTP NVM beginning at an address in the RAM corresponding to a read start address to define a timing device configuration in the RAM.

Abstract: Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators.

Abstract: A memory device to correct a defect cell generated after packing is performed includes a memory cell array in which a plurality of memory cells are arranged, a repair circuit unit including a first storage unit to store defect cell information in the memory cell array, and a fuse circuit unit including a second storage unit that is programmed according to the defect cell information stored in the first storage unit. The first storage unit includes a volatile memory device, and the second storage unit includes a non-volatile memory device.

Abstract: Systems and methods for improving NAND flash memory yields by identifying memory blocks with benign word line defects. Memory blocks including word line defects may be classified as incomplete memory blocks and may be used for storing data fragments. A data fragment may correspond with data written into memory cells associated with one or more contiguous word lines within a memory block that does not include a bad word line. In some cases, firmware associated with a NAND flash memory device may identify one or more data fragments based on the location of bad word lines within a memory block. A word line defect may be considered a benign defect if the defect does not prevent memory cells connected to other word lines within a memory block from being programmed and/or read reliably.

Abstract: A semiconductor memory device may include: a memory cell array including first and second word lines coupled to first and second memory cells, respectively; a word line driving unit suitable for selectively driving the first and second word lines; and a test control unit suitable for enabling the first word line to write test data to the first memory cell, and enabling the second word line to write the test data to the second memory cell, during a test operation.

Abstract: A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module.

Abstract: Provided is a compensation circuit including a memory cell array including a normal area and a redundancy area for repairing defects occurred in the normal area, a compensation time control circuit that activates a compensation start signal for a sense amplifier coupled to the normal area and the redundancy area in response to an active command, and a compensation control signal generation circuit that starts a compensation operation in response to the compensation start signal, and stops a compensation start signal for a sense amplifier coupled to an unselected word line in response to a fuse compare completion pulse and a compare address.

Abstract: In one embodiment, a fuel bundle for a liquid metal cooled reactor includes a channel, a nose assembly secured to a lower end of the channel, a plurality of fuel rods disposed within the channel, and an internal mixer disposed within the channel above the plurality of fuel rods. The internal mixer includes peripheral flow control members and interior flow control members. The peripheral flow control members are located near walls of the channel, and the interior flow control members are located towards a longitudinal center of the housing. At least one of the peripheral flow control members is configured to direct liquid metal flowing through the channel towards an interior of the channel, and at least one of the interior flow control members is configured to direct liquid metal flowing through the channel away from the interior of the channel.