Abstract: A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.

Abstract: A method of introducing N/P dopants in PMOS and NMOS fins at the SSRW layer without complicated processing and the resulting device are provided. Embodiments include forming a plurality of p-type and n-type fins on a substrate, the plurality of p-type and n-type fins formed with an ISSG or pad oxide layer; performing an n-well implant into the substrate through the ISSG or pad oxide layer; performing a first SRPD on the ISSG or pad oxide layer of the plurality of p-type fins; performing a p-well implant into the substrate through the ISSG or pad oxide layer; performing a second SRPD on the ISSG or pad oxide layer of the plurality of n-type fins; and driving the n-well and p-well implants and the SRPD dopants into a portion of the plurality of p-type and n-type fins.

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a second pad electrically disconnected from the first pad; applying at least one electrical test potential to at least one of the first pad and the second pad; and electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential.

Abstract: An overlay measuring method includes irradiating an electron beam onto a sample, including a multi-layered structure of overlapped upper and lower patterns formed thereon, to obtain an actual image of the upper and lower patterns. A first image representing the upper pattern and a second image representing the lower pattern are obtained from the actual image. A reference position for the upper and lower patterns is determined from a design image of the upper and lower patterns. A position deviation of the upper pattern with respect to the reference position in the first image and a position deviation of the lower pattern with respect to the reference position in the second image are calculated to determine an overlay between the upper pattern and the lower pattern.

Abstract: Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate. According to the present invention, reliability can be improved by increasing bonding areas and bonding strength of semiconductor devices as well as processibilty can be enhanced and failure is reduced by adjusting a step difference with respect to an arrangement and height of the semiconductor devices. Further, a processing time resulting from an omission of a wire bonding process is reduced.

Abstract: An insertion vertical electrode region and part of a case-contact horizontal electrode region of an electrode insertion part of an external electrode is inserted and molded in an intra-case insertion region of a housing case. Inserting the case-contact horizontal electrode region, which serves as part of the electrode insertion part, in the intra-case insertion region allows the upper and lower surfaces of the case-contact horizontal electrode region to be in contact with the intra-case insertion region.

Abstract: A circuit module includes: a wiring substrate including a mounting surface having first and second areas and a terminal surface on the other side of the mounting surface; a plurality of electronic components mounted on the first and second areas; a sealing layer that covers the plurality of electronic components, is formed of an insulation material, and includes a groove portion formed along a boundary between the first and second areas; a conductive shield including a first shield portion that covers an outer surface of the sealing layer and a second shield portion provided in the groove portion; and a conductive layer including a wiring portion that is provided on the mounting surface and electrically connects the terminal surface and the second shield portion, and a thickening portion that is provided in the wiring portion and partially thickens a connection area of the wiring portion with the second shield portion.

Abstract: Provided are a curable composition and its use. The curable composition can exhibit excellent processibility and workability. The curable composition exhibits excellent light extraction efficiency, hardness, thermal and shock resistance, moisture resistance, gas permeability and adhesiveness, after curing. In addition, the curable composition can provide a cured product that exhibits long-lasting durability and reliability, and that does not cause whitening and surface stickiness even under harsh conditions.

Abstract: A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel to an interface between the molding compound and the buffer layer and around a circumference of the opening. Other embodiments contemplate an additional package bonded to the package, and methods for forming the package.

Abstract: A loop heat pipe system includes a loop heat pipe (LHP), a temperature sensor, a heater and a controller. The temperature sensor measures temperature of a working fluid portion of the LHP in which the working fluid has different phases depending on whether or not the LHP is in a disable status not to start up a heat transportation, in which a liquid phase of the working fluid does not exist in an evaporator of the LHP. The heater heats a heating target part of a vapor line. The controller, in order to start up the LHP, turns on the heater, monitors temperature of the heating target part using the temperature sensor, and turns off the heater when detecting a change in the monitored temperature, caused by condensation of a vapor phase of the working fluid.

Abstract: Effective utilization of a parallel flow air-cooled microchannel array at the micro electro mechanical systems (MEMS) scale is prohibited by unfavorable flow patterns in simple rectangular arrays. The primary problem encountered is the inability of the flow stream to penetrate a sufficient depth into the fin core to achieve the desired fin efficiency. Embodiments of the present invention overcome this problem using a manifold with open nozzle discharge and integrated lateral exhaust along with a microchannel array cooler with micro spreading cavities for internal air distribution.

Abstract: A wafer frontside-backside through silicon via and methods of manufacture are disclosed. The method includes forming a plurality of frontside metalized vias into a partial depth of a substrate. The method further includes forming a backside via in the substrate which exposes, from the backside, the plurality of frontside metalized vias. The method further includes forming a metal in the via in contact with the plurality of metalized frontside vias.

Abstract: A semiconductor device includes a conductive portion having semiconductor elements provided on a substrate, a case housing the conductive portion, and a lead terminal integrated into the case to be directly connected to the semiconductor elements or an interconnection of the substrate. The lead terminal has a stress relief shape for reliving stress generated in the lead terminal.

Abstract: A structure to improve saw singulation quality and wettability of integrated circuit packages (140) is assembled with lead frames (112) having half-etched recesses (134) in leads. In one embodiment, the structure is a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the lead frame strip. In another embodiment, the structure is a semiconductor device package (140) that includes a semiconductor device encapsulated in a package body (142) having a plurality of leads (120). Each lead has an exposed portion external to the package. There is recess (134) at a corner of each lead. Each recess has a generally concave configuration. Each recess is filled with a removable material (300).

Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.

Abstract: An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of the die and dielectric material embedding a portion of a thickness dimension of the die; and a plurality of carrier contact points disposed at a gradation between the device side of the die and the embedded thickness dimension of the die and configured for connecting the carrier to a substrate. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; forming a build-up carrier adjacent a device side of a die, wherein the build-up carrier includes a dielectric material defining a gradation between the device side of the die and a backside of the die, the gradation including a plurality of carrier contact points; and separating the die and the carrier from the sacrificial substrate.

Abstract: A wiring substrate includes, a base wiring substrate including a first wiring layer, a first insulating layer in which the first wiring layer is buried and a first via hole is formed under the first wiring layer, and a second wiring layer formed under the first insulating layer and connected to the first wiring layer through the first via hole, and a re-wiring portion including a second insulating layer formed on the base wiring substrate and having a second via hole formed on the first wiring layer, and a re-wiring layer formed on the second insulating layer and connected to the first wiring layer through the second via hole. The re-wiring layer is formed of a seed layer and a metal plating layer provided on the seed layer, and the seed layer is equal to or wider in width than the metal plating layer.

Abstract: A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.

Abstract: The invention relates to a field of semiconductor manufacturing technology, more particularly, to a method for preparing three-dimensional integrated inductor-capacitor structure, which can realize the inductor-capacitor of three-dimensional structure, and form three-dimensional spiral inductor centering on the magnetic cores of single direction around through the preparation of the interconnected top metal conducting wires and bottom metal conducting wires, which can gain capacitance and inductance at the same time in a relatively small space, and reduce the production costs, and also greatly improves the inductance magnetic flux in order to increase the inductance value and reduce eddy current, and improve the quality factor Q value and the performance of inductance coil.

Abstract: A fuse circuit includes a substrate, a top semiconductor layer doped a first conductivity type having a well doped a second conductivity type formed therein including a well contact. A field dielectric layer (FOX) is on the semiconductor layer. A fuse is on the FOX within the well including a fuse body including electrically conductive material having a first and second fuse contact. A transistor is formed in the semiconductor layer including a control terminal (CT) with CT contact, a first terminal (FT) with FT contact, and a second terminal (ST) with a ST contact. A coupling path is between the CT contact and well contact, a first resistor is coupled between the FT contact and CT contact, and a coupling path is between the ST contact and the first fuse contact.

Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed on a second metal layer of the semiconductor device, and directly under the metal pad.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Abstract: This is directed to self-shielded components and methods for making the same. A self-shielded component can include an electromagnetic interference (EMI) shield that contains circuitry within a shielded space defined by the EMI shield. Self-shielding can be achieved by interfacing a conformal shield layer to a ground layer disposed on or within a substrate of the self-shielded component. The combination of the conformal shield layer and the around layer can form a boundary of the shielded space that envelops circuitry requiring shielding. This enables the self-shielded component to be mounted to a circuit board without requiring a shield can or other processing to impart EMI shielding. In addition, the self-shielded components include the benefits of EMI shielding while simultaneously decreasing space requirements.

Abstract: Provided is a composite substrate manufacturing method, including at least: a first raw board deforming step of preparing a first substrate by deforming a first raw board having at least one surface as a minor surface into a state in which the minor surface warps outward; and a joining step of joining, after the first raw board deforming step, a protruding surface of the first substrate and one surface of a second substrate to each other, thereby manufacturing a composite substrate including the first substrate and the second substrate, in which the second substrate is any one substrate selected from a substrate having both surfaces as substantially flat surfaces and a substrate that warps so that a surface thereof to be joined to the first substrate warps outward. Also provided are a semiconductor element manufacturing method, a composite substrate and a semiconductor element manufactured.

Abstract: A semiconductor package includes a semiconductor chip electrically connected to a substrate, and a molding part including first molding members and second molding members arranged in an alternating pattern. The first molding members have a first physical flexibility which is different from a second physical flexibility of the second molding members.

Abstract: A resin-sealed semiconductor device includes a mesa-type semiconductor element which includes a mesa-type semiconductor base body having a pn junction exposure portion in an outer peripheral tapered region surrounding a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin which seals the mesa-type semiconductor element, wherein the glass layer is formed by forming a layer made of a predetermined glass composition for protecting a semiconductor junction which substantially contains no Pb such that the layer covers the outer peripheral tapered region and, subsequently, by baking the layer made of the glass composition for protecting a semiconductor junction.

Abstract: A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a plurality of circuit elements formed at the substrate and a plurality of electrical connections provided in the one or more interconnect layers. A die seal is provided in the one or more interconnect layers. A die seal leakage detection material is arranged in the one or more interconnect layers between the die seal and the plurality of electrical connections. The die seal provides a protection of the die seal leakage detection material from moisture if the die seal is intact. The die seal leakage detection material is adapted for providing a detectable modification of the circuit after an exposure of the die seal leakage detection material to moisture.

Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes both a static wire mesh and an active wire mesh. The wire meshes can be formed in the same layer over the circuits to be protected or in different layers. The wire meshes also may cover the entire chip area or only predetermined areas, such as over secure memory and register areas. The wire meshes are connected to a tamper detection module, which monitors the meshes and any signals transmitted via the meshes to detect attempts to access the protected circuits via micro-probing.

Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

Abstract: An embedded package includes a core layer having a cavity, a first semiconductor chip disposed in the cavity, and bumps disposed on a top surface of the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the core layer, pads disposed on a top surface of the second semiconductor chip, and a first insulation layer disposed on the core layer and the first and second semiconductor chips. The first insulation layer has first openings that expose the bumps and second openings that expose the pads, and the first and second openings have a similar depth.

Abstract: Integrated circuit (IC) packages and methods of forming the IC packages are provided. In an embodiment, IC dies are formed and are placed on a carrier to form a packaged semiconductor device. An encapsulant is formed over the IC dies and between the neighboring IC dies. The encapsulant and the IC dies are planarized to expose contacts on top surfaces of the IC dies, and redistribution layers (RDLs) are formed over the planarized encapsulant and the planarized IC dies. Openings are formed in a topmost dielectric layer of the RDLs to expose interconnects in the RDL, and a conductive seed layer is formed over the RDL and in the openings. Connectors of a first type and connectors of a second type are formed over the seed layer in the openings. The packaged semiconductor device is diced into individual IC packages.

Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening. The opening of the first metal layer has a bottom and one or more sides extending from the bottom. A second metal layer is on the first metal layer. The first metal layer and the second metal layer provide a bowl-shaped structure. An inner surface of the bowl-shaped structure is defined responsive to the opening of the first metal layer and the second metal layer thereon. The opening of the bowl-shaped structure is configured to receive and at least partially retain a bonding material during a reflow process.

Abstract: A power converter includes a bus bar, a semiconductor device, a lead, and solder. The bus bar has a vertical wall. The semiconductor device includes an electrode. The lead has one end connected to the bus bar and another end connected to the semiconductor device to supply power from the bus bar to the electrode of the semiconductor device via the lead. The one end of the lead includes a bending part which is spaced away from the bus bar by a predetermined distance and which is inclined in a vertical downward direction. The vertical wall of the bus bar and the bending part are bonded to each other via the solder. The vertical wall extends in a substantially vertical direction to face the bending part.

Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.

Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.

Abstract: Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.

Abstract: A semiconductor optoelectronic device comprises a growth substrate; a semiconductor epitaxial stack formed on the growth substrate comprising a sacrificial layer with electrical conductivity formed on the growth substrate; a first semiconductor material layer having a first electrical conductivity formed on the sacrificial layer, and a second semiconductor material layer having a second electrical conductivity formed on the first semiconductor material layer; and a first electrode directly formed on the growth substrate and electrically connected to the semiconductor epitaxial stack via the growth substrate.

Abstract: A silicon interposer includes a silicon substrate having a front side and a rear side opposite to the front side; a first integrated circuit chip disposed in the front side of the silicon substrate; a second integrated circuit chip disposed in the front side of the silicon substrate and being in close proximity to the first integrated circuit chip; a dummy kerf region between the first integrated circuit chip and the second integrated circuit chip; and at least a circuit device disposed in the front side of the silicon substrate within the kerf region.

Abstract: A semiconductor package includes a package substrate. A first semiconductor chip is mounted on the package substrate. The first semiconductor chip includes a first chip region and first chip pads formed on a top surface of the first chip region. A second semiconductor chip is mounted on the package substrate. The second semiconductor chip includes a second chip region and second chip pads formed on a top surface of the second chip region. A boundary region having a groove divides the first chip region and the second chip region. The first chip region, the second chip region and the boundary region share a semiconductor substrate of a one-body type.

Abstract: A semiconductor device is provided with a base member having a front surface and a plurality of semiconductor chips provided on the front surface and each having a long side and a short side, the plurality of semiconductor chips being aligned so that the long sides are faced with each other. The plurality of semiconductor chips are provided diagonally, respectively, so that the adjacent semiconductor chips are inclined to the same side in a planar view of the front surface.

Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.

Abstract: A semiconductor device for protection from electrostatic discharge includes a number of modules for protection from electrostatic discharge. Each module includes a thyristor having terminals and a gate, and a diode coupled in antiparallel to the terminals of the thyristor. Each module is sized to share a saturation current with neighboring modules when an electrostatic discharge current is received. A resistive network couples modules between two terminals. A triggering circuit includes a common triggering output that is coupled to the gate of the thyristor of each module and a common buried semiconductor layer contacts each module.

Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.

Abstract: A semiconductor power device is supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.

Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.

Abstract: Embodiments herein describe a decoupling capacitor that may include multiple fin and gate structures electrically insulated from a conductor (e.g., a metal layer) by a thin dielectric. The fins and gates may be electrically coupled to a first voltage rail (e.g., VHIGH) while the conductor is coupled to a second voltage rail (e.g., VLOW). In this manner, the fins and gates in combination form a first “plate” which is electrically insulated from the conductor which forms a second “plate” of a capacitor. In one embodiment, the decoupling capacitor is formed on the same substrate as the finFETs, and thus, can be disposed proximate to the finFETs—e.g., on the same layer in the chip or side-by-side. In one example, at least a portion of the decoupling capacitor and the finFET may be formed using the same fabrication steps.

Abstract: An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond anneal.