Abstract: A device with multiple encapsulated functional layers, includes a substrate, a first functional layer positioned above a top surface of the substrate, the functional layer including a first device portion, a first encapsulating layer encapsulating the first functional layer, a second functional layer positioned above the first encapsulating layer, the second functional layer including a second device portion, and a second encapsulating layer encapsulating the second functional layer.

Abstract: This document discusses, among other things, an inertial measurement system including a device layer including a single proof-mass 3-axis accelerometer, a cap wafer bonded to a first surface of the device layer, and a via wafer bonded to a second surface of the device layer, wherein the cap wafer and the via wafer are configured to encapsulate the single proof-mass 3-axis accelerometer. The single proof-mass 3-axis accelerometer can be suspended about a single, central anchor, and can include separate x, y, and z-axis flexure bearings, wherein the x and y-axis flexure bearings are symmetrical about the single, central anchor and the z-axis flexure is not symmetrical about the single, central anchor.

Abstract: An n?-type semiconductor substrate (1) includes an active region and a terminal region disposed outside the active region. A p+-type anode layer (2) is formed in a portion of an upper surface of the n?-type semiconductor substrate (1) in the active region. A plurality of p+-type guard ring layers (3) are formed in a portion of the upper surface of the n?-type semiconductor substrate (1) in the terminal region. An n+-type cathode layer (5) is formed in a lower surface of the n?-type semiconductor substrate (1). An anode electrode (6) is connected to the p+-type anode layer (2). A metallic cathode electrode (7) is connected to the n+-type cathode layer (5). A recess (8) is formed by trenching the n+-type cathode layer (5) in the terminal region. The cathode electrode (7) is also formed in the recess (8).

Abstract: Silicon Carbide (SiC) PiN Diodes are provided having a reverse blocking voltage (VR) from about 3.0 kV to about 10.0 kV and a forward voltage (VF) of less than about 4.3 V.

Abstract: Embodiments include apparatuses and methods related to a compound varactor. A first varactor in the compound varactor may include a collector layer and a first base layer that is arranged in a first plurality of parallel fingers. A second varactor in the compound varactor may include a second base layer arranged in a second plurality of parallel fingers, and the base layer may be coupled with the collector layer. In embodiments, the fingers of the base layers of the first varactor and the second varactor may be interleaved with one another. Other embodiments may be disclosed or claimed herein.

Abstract: An image pickup module includes: a wiring board including a first main surface on which chip electrodes are disposed and a second main surface on which the cable electrodes connected respectively to the chip electrodes via respective through wirings are disposed; an image pickup device chip including external electrodes bonded respectively to the chip electrodes; and a cable including conductive wires bonded respectively to the cable electrodes, in which all of the cable electrodes are disposed in a region not facing a region where the chip electrodes are disposed.

Abstract: A solar battery cell and related methodology are provided which enable a TAB wire to be accurately connected to an intended position, thus allowing a possible increase in manufacturing costs to be suppressed. The solar battery cell can include a substrate, a plurality of finger electrodes formed on a light receiving surface of the substrate, and a back surface electrode on a back surface of the substrate, the back surface electrode to be connected to a plurality of finger electrodes on an adjacent cell by applying a first TAB wire via a conductive adhesive, wherein the back surface electrode has omitted portions arranged to define at least one alignment marking indicative of a position where the first TAB wire is to be applied, the at least one alignment marking having a width less than a width of said first TAB wire.

Abstract: Methods of fabricating metal wrap through solar cells and modules for thin silicon solar cells, including epitaxial silicon solar cells, are described. These metal wrap through solar cells have a planar back contact geometry for the base and emitter contacts. Fabrication of a metal wrap through solar cell may comprise: providing a photovoltaic device attached at the emitter side of the device to a solar glass by an encapsulant, the device including busbars on the device emitter; forming vias through the device base and emitter, the vias terminating in the busbars; depositing a conformal dielectric film over the surface of the vias and the back surface of the base; removing portions of the conformal dielectric film from the ends of the vias for exposing the busbars and from field areas of the base; and forming separate electrical contacts to the busbars and the field areas on the back surface of the solar cell.

Abstract: Use of chemical mechanical polishing (CMP) and/or pure mechanical polishing to separate sub-cells in a thin film solar cell. In one embodiment the CMP is only used to separate the active, thin film layer into sub-cells, with scribing still being used to achieve sub-cell separation in conductive layers above and below the active, thin film layer. Also, the active layer may be placed over a series of protrusions so that the CMP removes the active layer that is over the protrusion, while leaving intact the flat, planar portions of the active layer. In this way, the removed active layer, from over the protrusions then becomes the division between sub-cells in the active layer.

Abstract: Methods for laser irradiation aluminum doping for monocrystalline silicon substrates are provided. According to one aspect of the disclosed subject matter, aluminum metal contacts are formed directly on a surface of a monocrystalline silicon substrate. The aluminum metal contact is selectively heated via laser irradiation, thereby causing the aluminum and a portion of the monocrystalline silicon substrate in proximity to the aluminum to reach a temperature sufficient to allow at least a portion of the silicon to dissolve in the aluminum. The aluminum and the portion of the monocrystalline silicon substrate in proximity to the aluminum is allowed to cool, thereby forming an aluminum-rich doped silicon layer on the monocrystalline silicon substrate.

Abstract: A method for doping a semiconductor substrate is disclosed wherein a layer of a first conductivity type is first formed followed by forming a blocking layer with an open area. An etch process is performed through the open area to remove the layer of the first conductivity type to exposed the top surface of the semiconductor substrate. Dopant ions are introduced to form a dopant region of a second conductivity type on the beneath the top surface of the semiconductor substrate wherein the dopant region of the second conductivity type is not in contact with the dopant layer of the first conductivity type that is not etched off thus forming a PN structure to form diodes for the interdigitated back contact photovoltaic cells. Since the ion doping processes are self-aligned, the mask requirements are minimized and the production cost for solar cells are reduced.

Abstract: A photovoltaic cell comprises a first subcell formed of a Group IV semiconductor material, a second subcell formed of a Group II-VI semiconductor material, and a tunnel homojunction interposed between the first and second subcells. A first side of the tunnel homojunction is formed by a first layer that is adjacent to a top surface of the first subcell. The first layer is of a first conductivity type and is comprised of a highly doped Group IV semiconductor material. The other side of the tunnel homojunction is formed by a second layer that adjoins the lower surface of the second subcell. The second layer is of a second conductivity type opposite the first conductivity type and also is comprised of a highly doped Group IV semiconductor material. The tunnel homojunction permits photoelectric series current to flow through the subcells.

Abstract: A light-induced diode-like response in multi-layered MoSe2 field-effect transistors resulting from a difference in the size of the Schottky barriers between drain and source contacts, wherein each barrier can be modeled as a Schottky diode but with opposite senses of current rectification, wherein the diode response results from the light induced promotion of photo-generated carriers across the smaller barrier. The sense of current rectification can be controlled by the gate voltage which is able to modulate the relative amplitude between both barriers, yielding a photovoltaic response.

Abstract: According to one embodiment, a photoconductive semiconductor switch includes a structure of nanopowder of a high band gap material, where the nanopowder is optically transparent, and where the nanopowder has a physical characteristic of formation from a sol-gel process. According to another embodiment, a method includes mixing a sol-gel precursor compound, a hydroxy benzene and an aldehyde in a solvent thereby creating a mixture, causing the mixture to gel thereby forming a wet gel, drying the wet gel to form a nanopowder, and applying a thermal treatment to form a SiC nanopowder.

Abstract: Provided is a method of disassembling a photovoltaic module. The method includes: applying heat to the photovoltaic module in an oxidizing atmosphere; removing an insulating protective layer wrapping a photovoltaic cell of the photovoltaic module; and obtaining the photovoltaic cell of the photovoltaic module.

Abstract: A method of forming an interdigitated back contact solar cell is described. The method uses a deposition process to create a doped glass layer on the substrate, which, when diffused, created either the emitter or back surface fields. The deposition process may also create an oxide layer on top of the doped glass layer. This oxide layer serves as a mask for a subsequent ion implant. This ion implant directs ions having the opposite conductivity of the doped glass layer into exposed regions of the substrate. A thermal process is used to diffuse the dopant from the doped glass layer into the substrate and repair any damage caused by the ion implant.

Abstract: A method of forming infra red detector arrays is described, starting with the manufacture of a wafer. The wafer is formed from a GaAs or GaAs/Si substrate having CMT deposited thereon by MOVPE. The CMT deposited comprises a number of layers of differing composition, the composition being controlled during the MOVPE process and being dependent on the thickness of the layer deposited. Other layers are positioned between the active CMT layers and the substrate. A CdTe buffer layer aids the deposition of the CMT on the substrate and an etch stop layer is also provided. Once the wafer is formed, the buffer layer, the etch stop layer and all intervening layers are etched away leaving a wafer suitable for further processing into an infra red detector.

Abstract: The present invention relates to a method for coating a solar panel to reduce the amount of light being received by the solar panel's photovoltaic cells and reduce their electrical output. The method comprises the step of coating the light-receiving area of said solar panel with a sufficient thickness of a coating composition which is adapted to reduce the amount of light reaching the photovoltaic cells such that the resulting electrical output of said solar panel is reduced to below a level which causes physiological injury. The invention also relates to a composition for coating the light-receiving area of a solar panel comprising: a binder and an opacifier, wherein the opacifier is included in a sufficient quantity such that a predetermined film thickness of said composition reduces light transmission therethrough such that the resulting electrical output of said solar panel is reduced to below the predetermined level.

Abstract: Disclosed is a light emitting device including a substrate, a first conductive semiconductor layer disposed on the substrate, an active layer disposed on the first conductive semiconductor layer, and a second conductive semiconductor layer disposed on the active layer, wherein the first conductive semiconductor layer comprises a first layer provided at the upper surface thereof with a notch, a second layer disposed on the first layer and a third layer disposed on the second layer, wherein the first conductive semiconductor layer further comprises a blocking layer between the first layer and the second layer and the blocking layer is disposed along the notch. The light emitting device can reduce leakage current by dislocation and improve resistance to static electricity.

Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.

Abstract: A light emitting element includes: a laminated body including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer in this order, the second conductive semiconductor layer having a light extraction surface; and a recombination suppression structure provided in vicinity of an end surface of the active layer, the recombination suppression structure having a bandgap larger than a bandgap of the active layer.

Abstract: An integrated hybrid crystal Light Emitting Diode (“LED”) display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite III-Nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended III-V or II-VI compound semiconductor on the opposite side of c-plane sapphire media. The c-plane sapphire media may be a bulk single crystalline c-plane sapphire wafer, a thin free standing c-plane sapphire layer, or crack-and-bonded c-plane sapphire layer on any substrate. The bandgap energies and lattice constants of the compound semiconductor alloys may be changed by mixing different amounts of ingredients of the same group into the compound semiconductor. The bandgap energy and lattice constant may be engineered by changing the alloy composition within the cubic group IV, group III-V, and group II-VI semiconductors and within the hexagonal III-Nitrides.

Abstract: A light emitting device package includes a substrate having a first cavity and a second cavity directly under the first cavity, a light emitting part on the second cavity, a first metal layer on an inner side surface of the substrate, a second metal layer on the inner side surface of the substrate, a third metal layer on a bottom surface of the substrate, the third metal layer electrically connected to the first metal layer by a first via hole, a fourth metal layer on the bottom surface of the substrate, the fourth metal layer electrically connected to the second metal layer by a second via hole, and a fifth metal layer on the bottom surface of the substrate, the fifth metal layer disposed between the first via hole and the second via hole.

Abstract: A production method of a substrate for nitride semiconductor device comprising a mask formation step of using a metal nitride as a base material and forming a mask having a prescribed shape on the above-described base material, a three-dimensional structure growth step of growing a three-dimensional structure made of the same material as the base material on the base material having the mask formed thereon using a selective growth technique so that a layer having a higher index plane is formed on the lateral face, and an active layer growth step of growing an active layer containing a rare earth element on the lateral face of the above-described three-dimensional structure using an organometallic vapor phase epitaxial method.

Abstract: A light emitting device includes a metal layer, a light emitting structure, an electrode disposed on a first upper portion of a second conductive type semiconductor layer, a current spreading portion disposed on a second upper portion of the second conductive type semiconductor layer, an adhesive layer disposed under a first conductive type semiconductor layer, an insulating layer disposed between the electrode and the adhesive layer, a passivation layer disposed on a side surface of the light emitting structure and on a at least one upper surface of the light emitting structure, and a reflective layer disposed between the metal layer and the first conductive type semiconductor layer.

Abstract: A high-efficiency light emitting diode including: a semiconductor stack positioned on a support substrate, including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; an insulating layer disposed in an opening that divides the p-type compound semiconductor layer and active layer; a transparent electrode layer disposed on the insulating layer and the p-type compound semiconductor layer; a reflective insulating layer covering the transparent electrode layer, to reflect light from the active layer away from the support substrate; a p-electrode covering the reflective insulating layer; and an n-electrode is formed on top of the n-type compound semiconductor layer. The p-electrode is electrically connected to the transparent electrode layer through the insulating layer.

Abstract: A carrier for an optoelectronic unit has a carrier material which includes polyethylene terephthalate which contains reflector particles and a further filler. Methods for the production of the optoelectronic unit and the carrier are also disclosed.

Abstract: A light emitting device is provided. The light emitting device includes a blue light emitting diode (LED); and phosphors including first to third phosphors, wherein the first phosphor is excited by light emitted from the blue LED, emits light having a main wavelength of about 495 nm to about 510 nm, and includes BaSi2O2N2:Eu or (Bax,Sr1-x)Si2O2N2:Eu where 0<x<1, the second phosphor is excited by light emitted from the blue LED, emits light having a main wavelength of about 555 nm to about 575 nm, and includes Lu3Al5O12:Ce or (Lux,Gd1-x)3Al5O12:Ce where 0<x<1, and the third phosphor is excited by light emitted from the blue LED, emits light having a main wavelength of about 580 nm to about 605 nm, and includes (Cax,Sr1-x)AlSiN3:Eu where 0<x<1.

Abstract: Disclosed is a light-emitting device (1) including a light-emitting element (2) emitting primary light, and a light converter (3) absorbing a part of the primary light emitted from the light-emitting element (2) and emitting secondary light having a longer wavelength than the primary light. The light converter (3) contains a green light-emitting phosphor (4) and a red light-emitting phosphor (5). The green light-emitting phosphor (4) is composed of at least one phosphor selected from a divalent europium-activated oxynitride phosphor substantially represented by the following formula: EuaSibAlcOdNe and a divalent europium-activated silicate phosphor substantially represented by the following formula: 2(Ba1-f-gMIfEug)O.SiO2, while the red light-emitting phosphor (5) is composed of at least one phosphor selected from tetravalent manganese-activated fluoro-tetravalent metalate phosphors substantially represented by the following formulae: MII2(MIII1-hMnh)F6 and/or MIV(MIII1-hMnh)F6.

Abstract: A light emitting device comprising: a package having a recess; a light emitting element mounted in the recess of the package; a transmissive member provided above the light emitting element; a sealing resin that seals the recess of the package; a first fluorescent material contained in the transmissive member; and a second fluorescent material contained in the sealing resin and having a specific gravity different from that of the first fluorescent material, wherein a greater amount of the second fluorescent material is distributed to a side of the light emitting element than above the light emitting element, and a side surface of the light emitting element is exposed on the sealing resin.

Abstract: A molded package, comprising: a molded resin having a recess for accommodating a light emitting element; a ceramic substrate disposed in a bottom of the recess, the ceramic substrate having one surface exposed from the bottom of the recess and the other surface exposed from a rear surface of the molded resin; and a lead disposed at a lower part of the molded resin, the light emitting element being mounted on the one surface of the ceramic substrate, the lead being in contact with at least one side surface of the ceramic substrate to hold the ceramic substrate.

Abstract: A semiconductor light-emitting device includes a substrate, an LED chip mounted on the substrate, and a resin package covering the LED chip. The substrate includes a base and a wiring pattern formed on the base. The resin package includes a lens. The base includes an upper surface, a lower surface and a side surface extending between the upper surface and the lower surface. The LED chip is mounted on the upper surface of the base. The side surface of the base is oriented in a lateral direction. The wiring pattern includes a pair of first mount portions and a pair of second mount portions. The paired first mount portions are formed on the lower surface of the base. The paired second mount portions are oriented in the lateral direction and offset from the side surface of the base in the lateral direction.

Abstract: Disclosed are a light emitting device and a method for manufacturing the same. The light emitting device includes a substrate having a lead frame, a light emitting diode mounted on the substrate, a mold member formed on the substrate and the light emitting diode, and a reflecting member having an opening portion at one side thereof and being inclined at an outer portion of the mold member.

Abstract: Various embodiments of light emitting devices, assemblies, and methods of manufacturing are described herein. In one embodiment, a method for manufacturing a lighting emitting device includes forming a light emitting structure, and depositing a barrier material, a mirror material, and a bonding material on the light emitting structure in series. The bonding material contains nickel (Ni). The method also includes placing the light emitting structure onto a silicon substrate with the bonding material in contact with the silicon substrate and annealing the light emitting structure and the silicon substrate. As a result, a nickel silicide (NiSi) material is formed at an interface between the silicon substrate and the bonding material to mechanically couple the light emitting structure to the silicon substrate.

Abstract: A manufacturing method of an LED package structure includes the steps of providing a base; disposing an LED chip on the base; electrically connecting the base and the LED chip by at least one metal wire, wherein the metal wire has an apex, and a height between the apex and a top surface of the LED chip is defined as a loop height; adhering a first phosphor sheet to the LED chip by a B-stage resin of the first phosphor sheet, wherein the first phosphor sheet covers the top surface, the side surface, and the electrode of the LED chip, the thickness of the first phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the first phosphor sheet; and disposing an encapsulation resin in the base to encapsulate the LED chip, the metal wire, and the first phosphor sheet.

Abstract: A light emitting diode (LED) package includes an LED chip, a first lead frame and a second lead frame electrically connected to the LED chip and separated by a space, and a housing disposed on the first lead frame and the second lead frame. The housing includes an external housing surrounding a cavity, the cavity exposing a first portion of the first lead frame and a first portion of the second lead frame, and an internal housing disposed in the space, the internal housing covering a top portion of the first lead frame and a top portion of the second lead frame.

Abstract: In a thermoelectric conversion module, each of a p-type element and an n-type element is configured by aligning a plurality of particles in series and connecting the particles to each other. Around a connection part in which the particles are connected to each other, a protrusion is protruded. The protrusion has a shape of continuously extending around the entire periphery of the connection part. The protrusion may be partly interrupted, but in such a case, a circumferential length of one interrupted portion is less than one half of the periphery of the connection part.

Abstract: The invention relates to a semiconductor device, a method for manufacturing a semiconductor device and an electronic thermoelectric power generation device, a semiconductor device having a thermoelectric conversion element that is embedded in a semiconductor chip so as to be integrated with a semiconductor circuit can be implemented. A semiconductor substrate is provided with a through opening for a region in which a thermoelectric conversion element is to be formed, and a thermoelectric conversion element is embedded in the through opening, where the thermoelectric conversion element includes: a number of penetrating rods made of a thermoelectric conversion material; and an insulating reinforcement layer in which the penetrating rods are embedded and of which the thermal conductivity is lower than that of the thermoelectric conversion material.

Abstract: A process for constructing a superconducting Josephson-based nonvolatile quantum memory device comprising: sequentially depositing on a silicon substrate a thermal oxide buffer layer, a superconductor bottom-electrode thin film, and an oxide isolation layer; patterning an active window having dimensions smaller that 10 nanometers in the oxide isolation layer; then sequentially depositing a bottom tunnel oxide layer, a charge-trapping layer, a top cap, and a top superconductor electrode layer; defining an active region by dry etching down to the oxide isolation layer while protecting the active region from etch chemistry; depositing a device passivation layer; defining and patterning vias from a top of the device passivation layer to the superconductor bottom-electrode thin film and to the top superconductor electrode of the active region; and depositing metal interconnect into the vias.

Abstract: A coplanar waveguide device includes a coplanar waveguide structure disposed on a substrate, at least one qubit coupled to the coplanar waveguide structure and an add-on chip having a metallized trench, and disposed over the substrate.

Abstract: Provided are superconducting circuits and method of forming thereof. A superconducting circuit may include a low loss dielectric (LLD) layer formed from one or both of polycrystalline silicon or polycrystalline germanium. The LLD layer may be formed at a low temperature (e.g., less than about 525° C.) using chemical vapor deposition (CVD). Addition of germanium may help to lower the deposition temperature and improve crystallinity of the resulting layer. The LLD layer is formed without adding silicides at the interface of the LLD layer and metal electrode. In some embodiments, an initial layer (e.g., a seed layer or a protective layer) may be formed on a metal electrode prior to forming the LLD layer. For example, the initial layer may include one of zinc sulfide, polycrystalline germanium, or polycrystalline silicon. The initial layer may be deposited at a low pressure (e.g., less than 10 Torr) to ensure higher levels of crystallinity.

Abstract: A displacement member with a driving element that includes first and second side surfaces that extend in a first direction and top and bottom surfaces that extend in a second direction perpendicular to the first direction. The driving element is a piezoelectric element that expands and contracts in the second direction when a pulsed voltage is applied. Further, an elastic conversion element is provided that contains the driving element and includes a first portion that is disposed adjacent the top surface of the driving element and that includes a displacement portion that is displaced downwardly and upwardly in the first direction when the driving element expands and contracts in the second direction, respectively.

Abstract: Described herein are methods for controlling a piezoelectric element, for example, for use in a fuel injector, safely and efficiently at higher frequencies without causing damage to the fuel injector due to excessive heating. Methods incorporating features of the present invention can utilize waveform generation, waveform scaling and power amplification to drive a piezoelectric element. In some embodiments, various operating conditions are utilized to determine a scaling value which is compared to a target value to determine the level of scaling to be utilized with a generated waveform.

Abstract: A piezoelectric/electrostrictive element includes a substrate, an adhesive layer, a first conductive layer, an anchor portion and a second conductive layer. The substrate contains a ceramic as a main component. The substrate has a main surface. The adhesive layer is formed on the main surface of the substrate. The adhesive layer contains a metal oxide as a main component. The first conductive layer is formed on the adhesive layer. The anchor portion is formed on the adhesive layer. The anchor portion is embedded in the conductive layer. The anchor portion contains glass as a main component. The second conductive layer is disposed opposite to the first conductive layer with the substrate located in-between.

Abstract: A stackable piezoelectric actuator component (100) comprises a stack (10) of piezoelectric layers (11) and electrode layers (12) arranged therebetween, a voltage supply device (20) arranged outside the stack (10) and serving for making electrical contact with the electrode layers, a contact connection (30) for applying a voltage to the voltage supply device (20) and a further contact connection (40), which is electrically coupled to the voltage supply device (20). The contact connection (30) and the further contact connection (40) are designed complementarily with respect to one another in such a way that a further stackable piezoelectric actuator component (200), comprising at least a contact connection or a further contact connection (30, 40), can be electrically coupled to the actuator component (100).

Abstract: A piezoelectric actuator of the invention includes: a piezoelectric element; a base body having an upper surface which is in contact with a lower end portion of the piezoelectric element; and a case having an inner surface which is in contact with an upper end portion of the piezoelectric element, the case storing the piezoelectric element therein, the upper surface of the base body and the case being joined to each other. The case includes a cylindrical portion including a cylindrical main body and a plurality of grooves formed all around a perimeter thereof, and a collar portion disposed at a lower end side of the cylindrical portion. At least one of the plurality of grooves has a sectional profile taken along a plane perpendicular to a vertical direction whose oblateness differs from that of a sectional profile of the cylindrical main body.

Abstract: In a method of growing p-type nanowires, a nanowire growth solution of zinc nitrate (Zn(NO3)2), hexamethylenetetramine (HMTA) and polyethylenemine (800 Mw PEI) is prepared. A dopant solution to the growth solution, the dopant solution including an equal molar ration of sodium hydroxide (NaOH), glycolic acid (C2H4O3) and antimony acetate (Sb(CH3COO)3) in water is prepared. The dopant solution and the growth solution combine to generate a resulting solution that includes antimony to zinc in a ratio of between 0.2% molar to 2.0% molar, the resulting solution having a top surface. An ammonia solution is added to the resulting solution. A ZnO seed layer is applied to a substrate and the substrate is placed into the top surface of the resulting solution with the ZnO seed layer facing downwardly for a predetermined time until Sb-doped ZnO nanowires having a length of at least 5 ?m have grown from the ZnO seed layer.

Abstract: A MTJ in an MRAM array is disclosed with a composite free layer having a lower crystalline layer contacting a tunnel barrier and an upper amorphous layer for improved bit switching performance. According to one embodiment, the amorphous layer has a NiFeM1/NiFeM2 configuration where M1 and M2 are Mg, Hf, Zr, Nb, or Ta, and M1 is unequal to M2. The crystalline layer is Fe, Ni, or FeB with a thickness of at least 6 Angstroms that affords a high magnetoresistive ratio. The M1 and M2 elements in the NiFeM1 and NiFeM2 layers each have a content of 5 to 30 atomic %. The NiFeM1/NiFeM2 configuration substantially reduces bit line switching current and number of shorted bits. In an alternative embodiment, the crystalline layer may be a Fe/NiFe bilayer. Annealing at 300° C. to 360° C. provides a high magnetoresistive ratio of about 150%.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction crossing the first direction, a resistance variable layer interposed between the first lines and the second lines, a tunnel barrier layer interposed between the resistance variable layer and the first lines, and an intermediate electrode layer interposed between the resistance variable layer and the tunnel barrier layer. The tunnel barrier layer and the intermediate electrode layer overlap with at least two neighboring intersection regions of the first lines and the second lines.

Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.