Abstract: A method for physical vapor deposition of an aluminum nitride film, comprising: positioning a substrate and an aluminum target in a chamber; vacuuming the chamber so that a chamber pressure is at a base pressure between 7.1×10?7-5×10?6 torr; conducting a working gas composed of argon gas and nitrogen gas into the chamber so that the chamber pressure is at a working pressure between 3-7 mtorr; and depositing the aluminum nitride film on the substrate by applying a high power impulse power supply to the aluminum target and applying a direct current bias power supply to the substrate under the working pressure and a substrate temperature between room temperature (25° C.) to 200° C.; wherein a power of the high power impulse power supply is between 500-600 W and a frequency thereof is between 750-1250 Hz, and a bias of the direct current bias power supply is between ?50-0 V.

Abstract: A dual coating and lift-off method for protecting patterned dielectric-metal coatings using a 2-layer lithography process that is exposed and developed to create an undercut and then, after the wafer is coated with a metal/dielectric filter ending with an incomplete final layer, the top lithography layer is lifted off exposing metal layer edges and leaving the bottom lithography layer intact on the wafer such that the final filter layer(s) can be deposited to complete the coating and passivate the exposed metal layer edges is disclosed.

Abstract: A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles.

Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.

Abstract: In various embodiments, a method for processing a carrier is provided. The method for processing a carrier may include: forming a first catalytic metal layer over a carrier; forming a source layer over the first catalytic metal layer; forming a second catalytic metal layer over the source layer, wherein the thickness of the second catalytic metal layer is larger than the thickness of the first catalytic metal layer; and subsequently performing an anneal to enable diffusion of the material of the source layer forming an interface layer adjacent to the surface of the carrier from the diffused material of the source layer.

Abstract: A heterostructure may include a substrate having a first primary surface, a second primary surface, and a diffusion layer extending a depth into the substrate from the first primary surface; and a deposition layer disposed on the second primary surface of the substrate. The heterostructure may further include an epitaxial layer disposed on the deposition layer.

Abstract: A method for forming fine patterns includes patterning a hard mask layer on an etch target layer to form sacrificial pillars and a first opening disposed between the sacrificial pillars and exposing the etch target layer, forming a block copolymer layer on the etch target layer exposed through the first opening, phase-separating the block copolymer layer to form first block patterns spaced apart from the sacrificial pillars and a second block pattern, forming first holes by etching the etch target layer exposed by removing the first block patterns, and forming second holes in the etch target layer exposed by removing the sacrificial pillars, the second holes being different from the first holes.

Abstract: A method of manufacturing a silicon carbide semiconductor device having a contact formed between a p-type silicon carbide semiconductor body and a metal electrode, includes forming on a surface of the p-type silicon carbide semiconductor body, a graphene layer so as to reduce a potential difference generated in a conjunction interface between the p-type silicon carbide semiconductor body and the metal electrode; forming an insulator layer comprising a hexagonal boron nitride on a surface of the graphene layer; and forming the metal electrode on a surface of the insulation layer.

Abstract: A method for processing a semiconductor wafer is provided. The method includes performing a discharging process over the semiconductor wafer in a discharging chamber which is enclosed. The method further includes processing the semiconductor wafer by use of a first processing module after the discharging process. During the discharging process, charged particles applied on the semiconductor wafer are tuned based on the characteristics of the surface of the semiconductor wafer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The semiconductor device structure includes spacers over opposite sidewalls of the gate stack. The spacers and the gate stack surround a recess over the gate stack. The semiconductor device structure includes a first insulating layer over the gate stack and an inner wall of the recess. The semiconductor device structure includes a second insulating layer over the first insulating layer. Materials of the first insulating layer and the second insulating layer are different, and a first thickness of the first insulating layer is less than a second thickness of the second insulating layer.

Abstract: A plating method includes forming a catalyst layer 118 on a surface of a substrate including an inner surface of a recess 112; drying the substrate having the catalyst layer formed thereon such that an inside of the recess is dried as well; removing the catalyst layer at least on the surface of the substrate at the outside of the recess by supplying a processing liquid, which is configured to dissolve a material of the surface of the substrate, onto the surface of the substrate while rotating the dried substrate and while preventing or suppressing the processing liquid from being introduced into the dried inside of the recess; and forming a plating layer 119 on the inside of the recess, at which the catalyst layer is not removed, by an electroless plating process.

Abstract: Embodiments of the invention are directed to a method of printing lines. A method may include positioning a plurality of print units according to a predefined spacing parameter. A method may include depositing material on a substrate by a plurality of print units to form a respective plurality of parallel lines according to a predefined spacing parameter. A printing unit may be positioned at an angle with respect to a predefined scan direction such that a predefined width of a printed line is achieved. A substrate may be rotated between scans such that a plurality of lines in a respective plurality of directions is printed in a scan direction.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate with a dielectric disposed thereon, wherein the dielectric has a recess formed by a plurality of exposed surfaces; forming a conductive film on the plurality of exposed surfaces; applying a surface agent to the recess so that the surface agent adheres to a portion of the conductive film; immersing the substrate into an electroplating solution comprising metallic ions; and applying a bias to the conductive film in order to fill metallic material in the recess.

Abstract: A method of curing a dielectric layer, such as a dielectric layer that has a relatively small thickness and/or a narrow width or a complicated shape, is provided. The method of curing a dielectric layer for the manufacture of a semiconductor device includes providing the dielectric layer, wherein the dielectric layer is on a semiconductor layer; forming a first metal-containing layer on the dielectric layer; forming a curing atom screening region in an upper portion of the first metal-containing layer by injecting screening atoms onto an upper surface of the first metal-containing layer; injecting curing atoms into the first metal-containing layer through the upper surface of the first metal-containing layer; and flowing the curing atoms into the dielectric layer in an atmosphere at a first temperature.

Abstract: A thin plate is separated from an SiC substrate having a first surface, an opposite second surface, a c-axis extending from the first surface to the second surface, and a c-plane perpendicular to the c-axis. The thin plate is formed by epitaxial growth on the first surface of the SiC substrate. The plate is separated by a separation start point forming step of setting the focal point of a laser beam near the first surface of the SiC substrate from the second surface, and applying the laser beam to the second surface to form a modified layer parallel to the first surface and cracks extending from the modified layer along the c-plane, thus forming a separation start point. An external force is applied to the SiC substrate to separate the thin plate from the SiC substrate at the separation start point.

Abstract: Disclosed are sulfur-containing compounds for plasma etching channel holes, gate trenches, staircase contacts, capacitor holes, contact holes, etc., in Si-containing layers on a substrate and plasma etching methods of using the same. The plasma etching compounds may provide improved selectivity between the Si-containing layers and mask material, less damage to channel region, a straight vertical profile, and reduced bowing in pattern high aspect ratio structures.

Abstract: A dry etching method for isotropically etching each of SiGe layers selectively relative to each of Si layers in a laminated film is provided. The laminated film can include Si layers and SiGe layers alternately and repeatedly laminated. Each of the SiGe layers can be plasma-etched with plasma generated by a pulse-modulated radio frequency power using NF3 gas.

Abstract: A process for depositing doped aluminum nitride (doped AlN) is disclosed. The process comprises subjecting a substrate to temporally separated exposures to an aluminum precursor and a nitrogen precursor to form an aluminum and nitrogen-containing compound on the substrate. The aluminum and nitrogen-containing compound is subsequently exposed to a dopant precursor to form doped AlN. The temporally separated exposures to an aluminum precursor and a nitrogen precursor, and the subsequent exposure to a dopant precursor together constitute a doped AlN deposition cycle. A plurality of doped AlN deposition cycles may be performed to deposit a doped AlN film of a desired thickness. The dopant content of the doped AlN can be tuned by performing a particular ratio of 1) separated exposures to an aluminum precursor and a nitrogen precursor, to 2) subsequent exposures to the dopant. The deposition may be performed in a batch process chamber, which may accommodate batches of 25 or more substrates.

Abstract: A method of forming a semiconductor device includes sequentially forming a hard mask layer and a first sacrificial layer on a substrate, forming a first mandrel on the first sacrificial layer, forming a first spacer on both sidewalls of the first mandrel, removing the first mandrel, forming a second mandrel by etching the first sacrificial layer using the first spacer as an etch mask, forming a second spacer on both sidewalls of the second mandrel, removing the second mandrel, forming a hard mask pattern by patterning the hard mask layer using the second spacer as an etch mask, the hard mask pattern including first to ninth fin-type mask patterns extending to be parallel with each other in a first direction and sequentially spaced apart from each other in a second direction perpendicular to the first direction, removing the third, fifth and seventh fin-type mask patterns, forming first to sixth active patterns by etching the substrate using the hard mask pattern as an etch mask, and forming a first gate elect

Abstract: A first portion of a multiple cycle spacer is formed on a sidewall of a patterned feature over a substrate. A spacer layer is deposited on the first portion using a first plasma process. The spacer layer is etched to form a second portion of the multiple cycle spacer on the first portion using a second plasma process. A cycle comprising depositing and etching of the spacer layer is continuously repeated until the multiple cycle spacer is formed.

Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a workpiece having a material layer disposed on a substrate. A first set of fins is formed on the material layer, and a second set of fins is formed on the material layer interspersed between the first set of fins. The second set of fins have a different etchant sensitivity from the first set of fins. A first etching process is performed on the first set of fins and configured to avoid substantial etching of the second set of fins. A second etching process is performed on the second set of fins and configured to avoid substantial etching of the first set of fins. The material layer is etched to transfer a pattern defined by the first etching process and the second etching process.

Abstract: In the treatment of a semiconductor wafer (8), a treatment medium, in particular an etching or cleaning liquid, is applied to the semiconductor wafer (8) from a nozzle (11). In this process, the temperature, the concentration and/or the amount of medium applied in the unit of time are controlled depending on the location (7) at which the medium is being applied to the semiconductor wafer (8). In this manner, uniform treatment of the semiconductor water (8) is achieved because irregularities in the semiconductor wafer (8) can be compensated.

Abstract: A method of etching silicon nitride on patterned heterogeneous structures is described and includes a gas phase etch using anhydrous vapor-phase HF. The HF may be combined with one or more of several precursors in the substrate processing region and near the substrate to increase the silicon nitride etch rate and/or the silicon nitride selectivity. The silicon nitride etch selectivity is increased most notably when compared with silicon of various forms. No precursors are excited in any plasma either outside or inside the substrate processing region according to embodiments. The HF may be flowed through one set of channels in a dual-channel showerhead while the other precursor is flowed through a second set of channels in the dual-channel showerhead.

Abstract: Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.

Abstract: A substrate having an insulating layer including an oxide is loaded into a chamber, and at least a part of the insulating layer is removed by injecting a process gas including an etching source gas into the chamber. The removal process is performed in a pulse type in which a first period and a second period are repeated a plurality of times. The etching source gas is supplied at a first flow rate during the first period and is supplied at a second flow rate less than the first flow rate during the second period. A temperature of the inside of the chamber remains at 100° C. or more during the removal process.

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract: Disclosed is a method for etching an organic film. Plasma of a processing gas containing hydrogen gas and nitrogen gas is generated within a processing container of a plasma processing apparatus that accommodates a workpiece. A partial region of the organic film that is exposed from a hard mask is changed into a denatured region by the generation of the plasma of the processing gas. Subsequently, plasma of a rare gas is generated within the processing container. The denatured region is removed by the plasma of the rare gas, and a substance released from the denatured region is deposited on the surface of the hard mask. In this method, the generation of the plasma of the processing gas and the generation of the plasma of the rare gas are repeated alternately.

Abstract: It is an object to drive a semiconductor device at high speed or to improve the reliability of the semiconductor device. In a method for manufacturing the semiconductor device, in which a gate electrode is formed over a substrate with an insulating property, a gate insulating film is formed over the gate electrode, and an oxide semiconductor film is formed over the gate insulating film, the gate insulating film is formed by deposition treatment using high-density plasma. Accordingly, dangling bonds in the gate insulating film are reduced and the quality of the interface between the gate insulating film and the oxide semiconductor is improved.

Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.

Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs. The openings surrounding the end-portions of the TPVs of the die package enable solders of the bonding structures formed between another die package to remain in the openings without sliding and consequently increases yield and reliability of the bonding structures. Polymers may also be added to fill the openings surrounding the TPVs or even the space between the die packages to reduce cracking of the bonding structures under stress.

Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.

Abstract: A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.

Abstract: The embodiments herein relate to methods and apparatus for performing ion etching on a semiconductor substrate, as well as methods for forming such apparatus. In some embodiments, an electrode assembly may be fabricated, the electrode assembly including a plurality of electrodes having different purposes, with each electrode secured to the next in a mechanically stable manner. Apertures may be formed in each electrode after the electrodes are secured together, thereby ensuring that the apertures are well-aligned between neighboring electrodes. In some cases, the electrodes are made from degeneratively doped silicon, and the electrode assembly is secured together through electrostatic bonding. Other electrode materials and methods of securing may also be used. The electrode assembly may include a hollow cathode emitter electrode in some cases, which may have a frustoconical or other non-cylindrical aperture shape. A chamber liner and/or reflector may also be present in some cases.

Abstract: Buffer chamber including robots, a carousel and at least one heating module for use with a batch processing chamber are described. Robot configurations for rapid and repeatable movement of wafers into and out of the buffer chamber and cluster tools incorporating the buffer chambers and robots are described.

Abstract: A substrate processing apparatus includes first and second process chambers; a mounting section on which a housing vessel that houses the substrate is mounted; a vacuum transfer chamber that has a vacuum transfer machine to transfer the substrate under a negative pressure; and an atmospheric transfer chamber that has an atmospheric transfer machine that transfers the substrate under an atmospheric pressure. Timing for the atmospheric transfer chamber to take out the substrate from the housing vessel is based on a recipe remaining time, which is a remaining time of substrate processing, and an approach time, which is a time from when the substrate is taken out from the housing vessel till when the substrate is mounted to the vacuum transfer machine.

Abstract: A substrate processing system includes a processing unit having one or more processing chambers each of which includes a mounting table configured to mount thereon a substrate and is configured to perform predetermined processing on the substrate, a loading/unloading unit configured to load/unload a substrate container accommodating a plurality of substrates, one or more transfer units configured to transfer a substrate between the loading/unloading unit and the processing chambers, and a control unit configured to control the processing unit, the loading/unloading unit and the transfer units. The control unit controls a simulated operation, which does not include the predetermined processing in the processing chamber, to be performed on a plurality of dummy substrates in parallel. The simulated operation is a simulated transfer operation of the dummy substrates and includes a operation without transferring the dummy substrates from the loading/unloading unit into the processing chamber.

Abstract: A gas injection device a placement portion on which a first or second container is placed, an ejection portion which is placed on the placement portion and ejects a purge gas, and a sealing portion protruding from the placement portion so as to surround a periphery of the ejection portion. The ejection portion, with the purge gas being injected into an inlet of the second container, does not come in contact with the inlet. The sealing portion, with the purge gas being injected into an inlet of the FOUP, does not impede the contact between the ejection portion and the inlet.

Abstract: An electrostatic clamp having improved temperature uniformity is disclosed. The electrostatic clamp includes an LED array mounted along an annular ring so as to illuminate the outer edge of the workpiece. The LEDs in the LED array may emit light at a wavelength readily absorbed by the workpiece, such as between 0.4 ?m and 1.0 ?m. The center portion of the workpiece is heated using conductive heating provided by the heated electrostatic clamp. The outer portion of the workpiece is heated by light energy from the LED array. The LED array may be disposed on the base of the electrostatic clamp, or may be disposed on a separate ring. The diameter of the upper dielectric layer of the electrostatic clamp may be modified to accommodate the LED array.

Abstract: As viewed in plane, a ceramic heater includes zone heat-generating elements disposed in respective heating zones so as to heat a ceramic substrate independently. In the heating zone having a hole region, the zone heat-generating element is formed of a linear heat-generating conductor which has parallel segments disposed in parallel, and a turning-back segment which connects, while turning back, the parallel segment of the heat-generating conductor extending toward the hole region to the adjacent parallel segment of the heat-generating conductor so as to prevent the parallel segment extending toward the hole region from overlying the hole region.

Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.

Abstract: A workpiece cutting method is provided. The workpiece cutting method includes an attaching step of attaching an adhesive tape to the front side or back side of a workpiece, an applying step of applying a liquid resin to the front side or back side of a support member, a pressing step of superimposing the workpiece on the support member in the condition where the liquid resin and the adhesive tape come into contact with each other, and then pressing the workpiece or the support member, a fixing step of curing the liquid resin to thereby fix the workpiece to the support member, and a cutting step of cutting the workpiece fixed to the support member by using a cutting blade.

Abstract: A pin mechanism and a method for reducing backside particle induced out-of-plane distortions in semiconductor wafers involving such pin mechanisms. Geometric parameters of the pin are optimized so as to maximize the height of a particle trapped between a backside of the wafer and one of the contact lands without exceeding a selected maximum out-of-plane distortion. These geometric parameters are optimized in various designs of the pin mechanism, such as a pin mechanism that includes secondary leaf-type flexures attached to the contact lands and a single stem attached to a base portion of a cross-member of the pin. An alternative pin mechanism includes notch-type flexures, as opposed to secondary leaf-type flexures, connected to the cross-member of the pin. Furthermore, a plurality of stems are attached to the base portion of the cross-member of the pin. Alternatively, such a pin mechanism may utilize a different number of stems (e.g., one stem).

Abstract: A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a layer for a first conductor and a second conductor, plating patterned portions of the layer to form the first conductor and the second conductor, removing patterned material to form an air gap between the first conductor and the second conductor, applying a self-supporting film on top of the first conductor and the second conductor to enclose the air gap, and reacting the self-supporting film causing the self-supporting film to be substantially non-conductive.

Abstract: A method for manufacturing a semiconductor substrate includes providing a first wafer having a first surface and a second surface opposite the first surface, forming cavities in the first wafer at a first distance from the first surface, wherein the cavities, when seen in a cross-section perpendicular to the first surface, are laterally spaced from each other by partition walls formed by the semiconductor material of the first wafer, the cavities forming a separation region, bonding a second wafer on the first surface of the first wafer, breaking the partition walls by applying mechanical impact to the partition walls to split the first wafer along the separation region so that a residual wafer remains attached to the second wafer, and depositing an epitaxial layer on the residual wafer.

Abstract: An embodiment semiconductor device includes a first conductive feature in a dielectric layer and a second conductive feature over the dielectric layer and electrically connected to the first conductive feature. The second conductive feature includes a dual damascene structure and further includes a top portion within both a line portion and a via portion of the second conductive feature and a bottom portion in the via portion of the second conductive feature. The bottom portion comprises a different conductive material than the top portion, and a thickness of the bottom portion is at least about twenty percent of a total thickness of the via portion of the second conductive feature.

Abstract: A technique includes applying a liquid dielectric composition onto a substrate, where the composition includes metal ions, at least partially curing the composition to form a dielectric layer with the metal ions, patterning the dielectric layer to form electron-rich regions at a surface thereof, heating the patterned dielectric layer to drive the metal ions to the electron-rich regions thereof, thereby forming a metal barrier layer on at least a portion of the surface of the dielectric layer, and depositing one or more metal layers onto the metal barrier layer.

Abstract: Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant (low-k) material such as low-k film portions or air. An insulation layer such as SiO2 is etched to form raised structures. The structures are slimmed and a low-k material or sacrificial material is deposited. A further etching removes the material except for portions on sidewalls of the slimmed structures. A metal barrier layer and seed layer are then deposited, followed by a metal filler such as copper. Chemical mechanical polishing (CMP) removes portions of the metal above the raised structures, leaving only portions of the metal between the raised structures as spaced apart conductive lines. The sacrificial material can be removed by a thermal process, leaving air gaps. The raised structures provide strength while the air gap or other low-k material reduces capacitance.

Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.

Abstract: An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.