Patents Issued in October 25, 2016
  • Patent number: 9477538
    Abstract: The approaches described herein provide support for application specific policies for conventional operating systems. In an embodiment, a kernel module representing a kernel subsystem is executed within an operating system's kernel. The kernel subsystem may be configured to respond to particular requests with one or more default actions. Additionally, the kernel subsystem may define a number of sub-modules which represent application specific policies that deviate from the default actions. Each sub-module may define one or more sets of conditions which indicate when the sub-module is applicable to a request and one or more sets of corresponding actions to take when the conditions are met. When an application sends a request to the kernel subsystem, the kernel subsystem determines whether the request meets the conditions of a particular sub-module. If the particular sub-module's conditions are met, the kernel subsystem performs the corresponding actions of the particular sub-module.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: October 25, 2016
    Assignee: Oracle International Corporation
    Inventors: Frederick S. Glover, Diane Lebel, Thomas J. Engle, Angelo Pruscino
  • Patent number: 9477539
    Abstract: Techniques are described for managing interactions between workflows being performed by different applications, such as to enable a combination of multiple workflows in multiple applications of different types to aggregate varying capabilities available from the different types of applications. In some situations, an integrated workflow is created by separating portions of its functionality into multiple constituent workflows that is each performed by a different application and that initiate one or more inter-workflow interactions between the constituent workflows as they are performed (e.g., for one of the constituent workflows to, while it is being performed, invoke another constituent workflow in order to begin its performance).
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: October 25, 2016
    Inventor: Steven L. Buth
  • Patent number: 9477540
    Abstract: A multi-stage codeword detector for detecting codewords from read signals received from a multi-level memory device, includes a first detection stage configured for a coarse detection of a first codeword from a received read signal; a second detection stage configured for a fine detection of a second codeword from the received read signal; and a deciding entity configured to decide on using the second detection stage for the received read signal in dependence on a reliability indicator indicating a certain reliability level of the received read signal.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Theodore Antonakopoulos, Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis
  • Patent number: 9477541
    Abstract: Fault detection within wireless sensor networks can be determined by label propagation training within a wireless network system based on normal and faulty node conditions. The training information is then used to propagate node information to neighboring data vectors, which generates an indication of faulty nodes or an indication of a normal transmission path.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: October 25, 2016
    Assignee: City University of Hong Kong
    Inventors: Wai-shing Tommy Chow, Mingbo Zhao
  • Patent number: 9477542
    Abstract: An ECU having a microcomputer for controlling a control object includes: a detection device that detects an anomalous operation of the microcomputer; a first reset device that outputs a reset signal for the microcomputer when the detection device detects the anomalous operation; a failsafe control device that executes a failsafe control operation for controlling the control object to be safer than the control object before resetting the microcomputer when the microcomputer is reset to a normal state; a counting device that counts a number of times of occurrence of the anomalous operation when the detection device detects the anomalous operation again after the failsafe control device starts to execute the failsafe control operation; and a second reset device that outputs the reset signal and holds an output of the reset signal when the number of times of occurrence reaches a predetermined number of times.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: October 25, 2016
    Assignee: DENSO CORPORATION
    Inventor: Mitsuru Aoki
  • Patent number: 9477543
    Abstract: The disclosure generally describes computer-implemented methods, software, and systems for presenting error information. Logs are received from different locations, the logs associated with a plurality of builds at the different locations and associated with one or more systems. The logs are stored in a centralized location. Build information is generated for a given build, including identifying errors associated with the given build. Information for a current log associated with the given build is analyzed, including accessing information for previous logs associated with previous related builds related to the given build. Based on the analyzing, error diagnostic information that is to be presented is determined, including an analysis of errors that occurred in the given build and previous related builds. Instructions are provided, the instructions operable to present the error diagnostic information to a user, including providing log information, for presentation in a user interface.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: October 25, 2016
    Assignee: Business Objects Software Ltd.
    Inventors: Miles Henley, Dolan Sum, Alfred Fung, Edward Lam, Tao Lin, Randy Uy, Ren Horikiri, Jeff Lavoie
  • Patent number: 9477544
    Abstract: The present invention discloses a method and an apparatus for recommending a suspicious component in problem diagnosis for a cloud application. In the method, firstly a graph data model representing a hierarchical structure of the cloud application is constructed, wherein the graph data model comprises an application node representing the cloud application, a plurality of component nodes representing a plurality of components of the cloud application, and inter-node lines indicating inter-node relationships. Then real-time information of the cloud application is obtained, in response to detecting performance degradation of the cloud application. Impact degrees of the plurality of component nodes on the performance degradation of the cloud application is obtained based on the constructed graph data model and the obtained real-time information, and a suspicious component sequence is generated according to the impact degrees of the plurality of component nodes.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: Hai S. Wu, Meng Ye, Tao Yu
  • Patent number: 9477545
    Abstract: An error correcting system applied to a server, the server comprising a central processing unit, the central processing unit configured to send a warning signal when the central processing unit generates error. The error correcting system includes a programmable logic device, a baseboard management controller coupled to the programmable logic device, and a basic input output system coupled to the baseboard management controller. The programmable logic device is configured to detect the warning signal and send an interrupt signal to the baseboard management controller after the warning signal is detected. The baseboard management controller is configured to send a notification signal to the basic input output system after receiving the interrupt signal. The basic input output system is configured to retrieve the error and correct the error after receiving the notification signal.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: October 25, 2016
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Li-Wen Guo
  • Patent number: 9477546
    Abstract: Systems and methods for optimizing lifespan of a storage device are provided. A request to store data to the storage device is received. The storage device includes a plurality of regions. A determination is made that a first group of regions of the plurality of regions is associated with an error measurement threshold that is lower than a second group of regions of the plurality of regions. A region of the storage device that is in the first group of regions is selected based on the determination. The data is stored to the selected region.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: October 25, 2016
    Assignee: Marvell World Trade Ltd.
    Inventor: Yun Chan Myung
  • Patent number: 9477547
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 25, 2016
    Assignee: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Patent number: 9477548
    Abstract: A method for repairing a memory includes executing an Error Correction Code (ECC) for a page of the memory. The page includes a plurality of bits having an inherent number of failed bits equal to or greater than zero. The ECC is configured to correct a correctable number of failed bits from the plurality of bits. A location of a failure prone bit in the page is determined from a cache in response to the correctable number of failed bits being less than the inherent number of failed bits. A state of the failure prone bit is changed to a new state in response to determining the location of the failure prone bit. The ECC is executed in response to the state of the failure prone bit being changed to the new state.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: October 25, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: George P. Hoekstra, Ravindraraj Ramaraju
  • Patent number: 9477549
    Abstract: Methods, systems, and computer readable media for address and data integrity checking in flash memory operations are disclosed. One method includes, at a storage controller, generating, for an address unit, an address parity unit. The method further includes generating a command sequence including the address unit, the address parity unit, and an operation command specifying an operation to be performed on a flash memory array. The method further includes providing the command sequence to a flash memory device that includes the non-volatile memory array. The method further includes performing, by the flash memory device, an address integrity check on the address unit using the address parity unit. The method further includes determining whether or not to perform an operation specified by the command sequence based at least in part on a result of the address integrity check.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: October 25, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Ashutosh Malshe, Karthik Krishnamoorthy
  • Patent number: 9477550
    Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Benjiman L. Goodman, Luis A. Lastras-Montano, Eric E. Retter, Kenneth L. Wright
  • Patent number: 9477551
    Abstract: The present invention is directed to data migration, and particularly, Parity Group migration, between high performance data generating entities and data storage structure in which distributed NVM arrays are used as a single intermediate logical storage which requires a global registry/addressing capability that facilitates the storage and retrieval of the locality information (metadata) for any given fragment of unstructured data and where Parity Group Identifier and Parity Group Information (PGI) descriptors for the Parity Groups' members tracking, are created and distributed in the intermediate distributed NVM arrays as a part of the non-deterministic data addressing system to ensure coherency and fault tolerance for the data and the metadata. The PGI descriptors act as collection points for state describing the residency and replay status of members of the Parity Groups.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: October 25, 2016
    Assignee: DataDirect Networks, Inc.
    Inventors: Michael J. Piszczek, Jason M. Cope, Paul J. Nowoczynski, Pavan Kumar Uppu
  • Patent number: 9477552
    Abstract: In one embodiment, a tape drive includes a magnetic head having a plurality of read sensors, each read sensor being configured to read data simultaneously. The tape drive also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to receive encoded data read from a plurality of tracks of a magnetic tape medium simultaneously. The logic is also configured to perform priority-based decoding on the encoded data based on erasure coefficients associated with at least one codeword of the encoded data. In another embodiment, a controller-implemented method includes receiving encoded data read from a plurality of tracks of a magnetic tape medium simultaneously and performing priority-based decoding on the encoded data based on erasure coefficients associated with at least one codeword of the encoded data.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Bentley, Roy D. Cideciyan, Simeon Furrer, Keisuke Tanaka
  • Patent number: 9477553
    Abstract: A storage system provides highly flexible data layouts that can be tailored based on reliability considerations. The system allocates reliability values to logical containers at an upper logical level of the system based, for example, on objectives established by reliability SLOs. Based on the reliability value, the system identifies a specific parity group from a lower physical storage level of the system for storing data corresponding to the logical container. After selecting a parity group, the system allocates the data to physical storage blocks within the parity group. In embodiments, the system attaches the reliability value information to the parity group and the physical storage units storing the data. In this manner, the underlying physical layer has a semantic understanding of reliability considerations related to the data stored at the logical level.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: October 25, 2016
    Assignee: NetApp, Inc.
    Inventors: Mark Walter Storer, Jiri Schindler
  • Patent number: 9477554
    Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. The plurality of storage nodes configured to initiate an action based on the redundant copies of the metadata, responsive to achieving a level of redundancy for the redundant copies of the metadata. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: October 25, 2016
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, Igor Ostrovsky, Robert Lee, Shantanu Gupta, Rusty Sears, John Davis, Brian Gold
  • Patent number: 9477555
    Abstract: Methods, computer program products, and systems are presented. The methods include, for instance: enabling a client of a source site protected by a disaster recovery service, to select one or more value-added service to be performed by a data protection service provider in addition to the disaster recovery service. Respective dataset associated with a service is identified and analyzed to minimize the amount of dataset to replicate from the source site to a target site run by the data protection service provider, and a policy dictating when and how to replicate which dataset is configured. Upon being triggered, the data protection service provider performs the service by use of the dataset at the target site, the dataset either replicated according to the policy from the source site or being reconstructed from the transferred dataset when necessary.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 25, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tom Hagan, Robin H Lewis, Jeff N Marinstein, Ramani Ranjan Routray, Yang Song
  • Patent number: 9477556
    Abstract: Embodiments of the present application relate to a method, a system, and a computer program product.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: October 25, 2016
    Assignee: Alibaba Group Holding Limited
    Inventors: Minhui Deng, Kunli Luo
  • Patent number: 9477557
    Abstract: Performing a transaction in the context of a computing system that has one or more persistent systems coupled to one or more processors over a bus. As an example, the persistent system may serve as at least part of the main memory of the computing system. The transaction might implement multi-versioning in which a record is not updated in place. Rather, each record is represented as a sequence of one or more record versions, each version having a valid interval during which the record version is considered to properly represent the record. The transaction processing uses torn write detection so that recovery processes may use such guards to verify that there are no torn writes. For instance, torn write guards may be used to verify the integrity of record versions as well as the log buffers that refer to the record versions.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: October 25, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Per-Ake Larson, Robert Patrick Fitzgerald, Cristian Diaconu, Michael James Zwilling
  • Patent number: 9477558
    Abstract: Logging changes to a physical memory region during a logging time interval includes: detecting a write operation to the physical memory region, wherein the write operation modifies an indirect representation that corresponds to a physical data line in the physical memory region; and recording log information associated with the write operation.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventor: David R. Cheriton
  • Patent number: 9477559
    Abstract: A control device according to an exemplary aspect of the present invention, which is included in a sub-system of a plurality of sub-systems included in a fault tolerant system, includes: a packet reception unit that receives data from a processor unit included in the plurality of sub systems each including: the processor unit; an input-output unit; and a signal transmission path, the control device being connected between the processor unit and the input-output unit; and a first transmission unit that transmits error detection data being generated from the data of accessing from the processor unit to the input-output unit in an own sub-system to an companion sub-system when the processor unit is in the lockstep synchronous state, and transmits the data of accessing from a processor unit to the input-output unit in the own sub-system to the companion sub-system when the processor is in a lockstep asynchronous state.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: October 25, 2016
    Assignee: NEC CORPORATION
    Inventor: Yasuyuki Shirano
  • Patent number: 9477560
    Abstract: A highly efficient and effective method for deciding, in the context of a distributed computer network, how many computers will participate in an initial vote if multiple computers are started in the same general time frame.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: October 25, 2016
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Nathan J. Peterson, Rod D. Waltermann
  • Patent number: 9477561
    Abstract: In one embodiment, the gateway includes a trunk interface module (TI) for coupling the gateway to a trunk of the public network (PSTN), a media Server module (MS) coupled to an enterprise network, a transcoder module (TC), a call control module (CC), and a proxy module (PRO). The proxy module is configured to forward each SIP message received by the gateway, according to the IP address contained in a SIP Request-URI in this message. The SIP message is either sent to the Call Control module (CC) if this IP address is the address of the gateway, or to the data compression module (DC) if the IP address is the address of the main SIP Server (MSS). The proxy module is configured to add, in the latter case, its own IP address in Path header on each Register method; and, for each other SIP method sent to the main SIP Server (MSS), suppress its own IP address in the Route header.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 25, 2016
    Assignee: Alcatel Lucent
    Inventors: Sebastien Brunel, Laurent Barbero
  • Patent number: 9477562
    Abstract: A line of data is read from a line of memory. Intended data is specified by a random location and a random size within the line of memory. The line of data is moved into temporary storage. The line of data and a zero are multiplexed using a control signal to output a line of adjusted data which is automatically aligned to an initial point in an XOR buffer. A starting index of the intended data within the line of adjusted data corresponds to the initial point within an XOR buffer. An XOR operation is performed on the line of adjusted data and a line of data read from the XOR buffer to obtain a modified line of XOR data. The modified line of XOR data is written back to the XOR buffer at the same buffer locations as the line of data read from the XOR buffer.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 25, 2016
    Assignee: Microsemi Storage Solutions (US), Inc.
    Inventors: Mohammad Nikuie, Ihab Jaser
  • Patent number: 9477563
    Abstract: A method for electing a master blade in a virtual application distribution chassis (VADC), includes: sending by each blade a VADC message to each of the other blades; determining by each blade that the VADC message was not received from the master blade within a predetermined period of time; in response, sending a master claim message including a blade priority by each blade to the other blades; determining by each blade whether any of the blade priorities obtained from the received master claim messages is higher than the blade priority of the receiving blade; in response to determining that none of the blade priorities obtained is higher, setting a status of a given receiving blade to a new master blade; and sending by the given receiving blade a second VADC message to the other blades indicating the status of the new master blade of the given receiving blade.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: October 25, 2016
    Assignee: A10 Networks, Inc.
    Inventors: Rajkumar Jalan, Dennis Oshiba
  • Patent number: 9477564
    Abstract: Method and apparatus for dynamic Node healing in a Multi-Node environment. A multi-node platform controller hub (MN-PCH) is configured to support multiple nodes through use of dedicated interfaces and components and shared capabilities. Interfaces and components may be configured to be used by respective nodes, or may be configured to support enhanced resiliency as redundant primary and spare interfaces and components. In response to detecting a failing or failing primary interface or component, the MN-PCH automatically performs failover operations to replace the primary with the spare. Moreover, the failover operation is transparent to the operating systems running on the platform's nodes.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, Robert W. Cone, Malay Trivedi
  • Patent number: 9477565
    Abstract: A method for data access is disclosed. The method includes: receiving a file access request; acquiring one or more node lists corresponding to the file, wherein each node list comprises at least two nodes, and the mutually corresponding disks between the respective nodes store the same contents; accessing data chunks included in the file from the respective nodes selected from each of the node lists; and when an accessing from a certain node fails, selecting another node from the node list that comprises the certain node, and accessing a respective data chunk included in the file from the selected node according to the identifier of the file. A system and a device with tolerance of disk fault are also disclosed.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: October 25, 2016
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventor: Jibing Lou
  • Patent number: 9477566
    Abstract: Power leveling a system under test (SUT). An input signal is provided at an initial power level to the SUT. Multiple iterations are performed, each including measuring, over a specified measuring interval, power of a signal produced by the SUT in response to the input signal, and dynamically adjusting the power of the input signal in response. The measuring interval is increased over the iterations, thereby increasing accuracy of the measuring over the iterations while converging the signal to a specified power level. An initial power leveling operation may be performed for the SUT to establish a specified power level, after which the SUT is tested, during which multiple power leveling operations are performed, each including measuring power of a signal from the SUT over a specified measuring interval, and adjusting the input signal in response, thereby maintaining the specified power level during the testing while correcting for thermal droop.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 25, 2016
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventor: Daniel J. Baker
  • Patent number: 9477567
    Abstract: A high level interface between a remote computer and local computer operator permits the remote computer to be controlled via a sequence of interactions. The remote computer may be monitored for display information which is expected, and also controlled in the event the expected information either is or is not obtained. Command language extensions are provided which extend and complement a basic scripting language. Scripts with embedded command language extensions may be executed through a remote interface, permitting remote testing, operation and evaluation. The development of the scripts, including embedded command language extensions, may be prepared through execution of commands at the local computer on a depiction of the GUI received from the remote computer, and subsequently saved as a script.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: October 25, 2016
    Assignee: TestPlant, Inc.
    Inventors: Douglas P. Simons, Jonathan D. Gillaspie
  • Patent number: 9477568
    Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Jon A. Casey, Sungjun Chun, Alan J. Drake, Charles R. Lefurgy, Karthick Rajamani, Jeonghee Shin, Thomas A. Wassick, Victor Zyuban
  • Patent number: 9477569
    Abstract: A system and method that identifies and effectuates communication between a connectable client and a wireless human interface device. The wireless human interface device utilizes technologies to abstract the complexities of IP based wired and wireless networks to provide mechanisms to easily discover, associate, utilize and diagnose the wireless human interface device. Through the ensuing abstraction the wireless human interface device can be associated with an unlimited number of connectable networked clients or hosts thus eliminating the requirement of analog switch boxes to connect human interface devices to each connectable host or client, and further providing for the control of local and/or Internet based hosts or clients.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: October 25, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Scott Manchester, Takeshi Nagao, Keiichi Kishi, Takeshi Misu, Yasuhiro Odagiri, Yusuke Jinnai, David A. Roberts
  • Patent number: 9477570
    Abstract: A provisioning server can actively monitor the software provisioning processes being performed on a target machine to determine the status and integrity of the provisioning processes and notify an administrator or user of the status and integrity. The provisioning server can be configured to include a monitoring module and a message module. The monitoring module can be configured to monitor software provisioning processes being performed on a target machine and determine the status and integrity of the provisioning processes. The message module can be configured send notification to the administrator or user of the status and integrity of the provisioning processes.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: October 25, 2016
    Assignee: Red Hat, Inc.
    Inventor: Michael Paul DeHaan
  • Patent number: 9477571
    Abstract: One or more operators in a flow graph of a streaming application may include one or more triggers that indicate when action needs to be taken for the operator. A streams manager monitors performance of a streaming application and receives a notification when a trigger in an operator fires. In response to a trigger firing, the streams manager determines an appropriate action corresponding to the trigger. When the trigger indicates an adjustment of cloud resources are needed, the streams manager formulates a cloud resource request to a cloud manager. In response, the cloud manager adjusts the cloud resources for the operator to improve performance of the streaming application. A trigger may specify a trigger action for an operator, and may additionally specify a trigger action for one or more other affected operators. The firing of a trigger in one operator can therefore result in adjusting resources to multiple operators.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bin Cao, Jessica R. Eidem, Brian R. Muras, Jingdong Sun
  • Patent number: 9477572
    Abstract: An exemplary method may include collecting performance data of present operating conditions of network components operating in an enterprise network, extracting ontological component data of the network components from the collected performance data, comparing the collected performance data with predefined service tier threshold parameters, and determining if the ontological component data represents operational relationships between the network components, and establishing direct and indirect relationships between the network components based on the determined operational relationships and establishing a business application service group based on the ontological component data.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: October 25, 2016
    Assignee: Red Hat, Inc.
    Inventor: John M. Suit
  • Patent number: 9477573
    Abstract: A method of monitoring the level of performance of a software application running on a network-attached computing device, comprises monitoring information exchange at least one station on the network; measuring at least two performance indicator metrics, such as delay, jitter, loss, response time, throughput, goodput, and object size; and deriving an indicator parameter from a non-linear combination of the indicator metrics. A transformation may be applied to each indicator metric to obtaining a corresponding derived value, and the derived values then additively combined, to obtain the said indicator parameter. The transformation has a first region in which the derived value depends relatively weakly on the corresponding metric, and a second region, in which the derived value depends relatively strongly on the corresponding metric. A score value may be entered by a user, indicative of the user's perception of the performance of the software application, and compared with the derived indicator parameter.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: October 25, 2016
    Assignee: ACTUAL EXPERIENCE PLC
    Inventors: David John Page, Rupert Lawrence Grantham Ogilvie, Jonathan Michael Pitts
  • Patent number: 9477574
    Abstract: Systems, methods and computer program products for facilitating the collection of data within a computer network (especially an intranet) while complying with applicable privacy laws and regulations, as well as individual organizations' rules addressing intranet users' privacy are disclosed. Such systems, methods and computer program products allow for the collecting of activity information related to computer-based activities performed by users while logged into an organization's intranet. Such activity includes navigating to URLs, opening and editing documents, writing, opening and reading email and instant messages, and the like. The collecting, consolidating, storing and exposing of such activity information—while ensuring privacy requirements—serves as a basis for high-value services (e.g., augmenting documents with extra information, improving search results, automatic news feeds, social networking announcements, etc.) to be offered and provisioned to such users.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: October 25, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Ilya Tumanov, John Wana, George Perantatos, Brian R. Meyers, Gary Caldwell
  • Patent number: 9477575
    Abstract: A method for debugging and includes receiving a request for capturing a frame generated by a graphics application implementing application threads executing function calls. The function calls are associated with one or more thread specific resources used at the beginning of the capturing process. For each application thread, a corresponding state is determined for each thread specific resource utilized, and a corresponding capture stream is established. For each application thread, executed function calls are captured into the corresponding capture stream. A plurality of captured function calls is arranged in the order they were executed by the graphics application. For each capture stream, a corresponding replay thread is established. Application threads, capture streams, and replay threads exist in a one-to-one-to-one relationship.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: October 25, 2016
    Assignee: NVIDIA CORPORATION
    Inventor: Michael C. Strauss
  • Patent number: 9477576
    Abstract: A computer captures a thread state data of a first program. The computer generates a second program by applying a first program patch to the first program. The computer inserts additional code into a source code of the second program. The computer executes a first performance test using the second program and the inserted additional code. The computer monitors a first status of the second program and the inserted additional code that are under the first performance test. The computer determines a degree that a first deadlock state was prevented during the first performance test. The computer generates a first message based, at least in part, on the determined degree that the first deadlock state was prevented during the first performance test.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: David Granshaw, Samuel T. Massey, Daniel J. McGinnes, Martin A. Ross, Richard G. Schofield, Craig H. Stirling
  • Patent number: 9477577
    Abstract: A method of enabling an executed control flow path through computer program code to be determined. The method comprising modelling cumulative instruction counts for control flow paths through the computer program code, and inserting at least one probe within the computer program code to enable a cumulative instruction count value for at least one control flow path of the computer program code to be accessed.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: October 25, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventor: David Baca
  • Patent number: 9477578
    Abstract: A sequence-program-debugging supporting apparatus includes a configuration editing unit that receives a disabling unit from a PLC, a variable retaining unit that retains variables used by units on a sequence program, a program editing unit that can edit the sequence program, a converting unit that converts the sequence program into an execution code, a searching unit that acquires variables used by the disabling unit from the variable retaining unit and searches for places where the acquired variables are used in the sequence program, and a disabling setting unit that writes a section of the execution code corresponding to the places in a disabling section setting file as a disabling section not to be executed, and an execution control unit that controls, based on the disabling section setting file, an executing unit not to execute the disabling section.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: October 25, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takayuki Yamaoka
  • Patent number: 9477579
    Abstract: An embedded software debug system with partial hardware acceleration includes a computer that executes a debug software stack. The debug software stack includes high level operations. The system also includes a remote microcontroller electronically connected to the computer. The system further includes an embedded processor electronically connected to the remote microcontroller. The remote microcontroller receives an applet from the computer and executes the applet in conjunction with the computer executing the debug software stack to debug the embedded processor. The applet includes low level protocol operations including performance critical tight-loops precompiled into machine code. The debug software stack may include a stub that replaces the tight-loops of the applet. The computer may send the applet to the remote microcontroller in response to executing the stub.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: October 25, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kenneth E. Cecka, James T. Woodward
  • Patent number: 9477580
    Abstract: A computer-implemented method, computer program product, and system is provided for determining test coverage. In an implementation, a method may include identifying at least one change in source code. The method may also include instrumenting object code of at least one class file associated with a source file of the source code associated with the identified at least one change. The method may further include testing the instrumented object code with at least one test case. The method may further include generating a coverage report associated with the instrumented object code, wherein the coverage report includes a proportion of the at least one change in the source code covered by the at least one test case.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: Philip S. P. Chan, Laurence A. Hey, William J. Izard, Matthew J. Ponsford
  • Patent number: 9477581
    Abstract: The system and method presented provides a multi-phase, end-to-end integrated process for testing application software using a standard software testing tool. The system and method involve integrating the functional, automated regression and performance phases of software application testing by leveraging deliverables at each phase so that the deliverables may be efficiently reused in subsequent test phases. Deliverables such as functional and technical test conditions and manual test scripts are used as inputs for each phase of the integrated tests. The use of leveraged requirements-based deliverables between test phases significantly reduces much of the repetitive testing typically associated with functionality and performance testing and minimizes repetition of testing errors discovered in earlier test phases.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: October 25, 2016
    Assignee: JPMorgan Chase Bank, N.A.
    Inventors: Morrisha Hudgons, Michael E. Frank, Judit Lukashevich, Alex Rheingans
  • Patent number: 9477582
    Abstract: Executable software specification generation can include recording interactions with a user-interface (UI) mockup for a particular program and generating a number of executable software specification for the particular program based on the interactions with the UI mockup.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: October 25, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ithai Levi, Yair Horovitz, Zohar Adler
  • Patent number: 9477583
    Abstract: A computer implemented method and system including techniques for developing and executing automated test cases are described herein. In one embodiment, a test case automation tool provides functionality for defining an automated test set and associated test cases within a testing user interface without the use of scripting languages or compiled programming. The definition of each test case may occur within a testing user interface, including displaying and receiving user selection of available methods for testing; displaying user parameter fields and receiving user parameter values in response for testing; abstracting parameter types in the user parameter values; and generating XML-format definitions of the test case. The test case automation tool may then execute the selected methods of the software application using parameters provided in the XML-format definitions, and return testing results of the test case execution.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: October 25, 2016
    Assignee: CA, Inc.
    Inventor: Hari Kiran Maddela
  • Patent number: 9477584
    Abstract: This document discusses, among other things, a method of testing an Application Programming Interface (API) call that includes receiving data identifying a schema associated with web services together with an API call. Various example embodiments may relate to accessing a data repository associated with the schema to identify an API response corresponding to the API call. In some example embodiments, a message is returned that is based on a determination of whether the API call is valid. The example message may simulate an API response from web services.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: October 25, 2016
    Assignee: PAYPAL, INC.
    Inventor: Lei Hong
  • Patent number: 9477585
    Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: October 25, 2016
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
  • Patent number: 9477586
    Abstract: Memory controller circuitry may process the memory access requests by reordering the sequence of requests. Reordering the sequence of requests may decrease the power consumption of the memory controller and system memory associated with the memory controller. The memory controller may operate in at least an unconstrained power mode, a priority mode, and a constrained power mode. In the unconstrained power mode, the memory controller may process memory access requests at elevated and power consumption levels. In the priority mode, the memory controller may process memory access requests from select sources with reduced power consumption. In the constrained power mode, the memory controller may process all memory access requests at reduced power consumption levels. Capacitive-model based power monitoring circuitry may be used to monitor the interactions between the memory controller and the system memory to dynamically adjust the operating mode of the memory controller.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: October 25, 2016
    Assignee: Altera Corporation
    Inventors: Sam Hedinger, Philip Clarke
  • Patent number: 9477587
    Abstract: Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time. In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: October 25, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Wanmo Wong