Abstract: Discrete electronic modules, such as display tiles, designed and configured to be mosaicked and operatively connected with one another and/or to one or more differing types of discrete electronic modules. In some embodiments, the electronic modules include one or more recessed receptacles along their edges that receive corresponding connector biscuits that operatively connect abutting or confronting electronic modules with one another and/or to a controller. In some embodiments, the sizes of the recessed receptacles and connector biscuits are precisely matched so that the biscuits participate in aligning the abutting or confronting display tiles with one another. In some embodiments, the recessed receptacles are provided in recesses in the backsides of the display tiles, which allows each tile to be easily installed and removed from a display mosaic of which the tile is part.

Abstract: The present invention relates to a device and a method for terminating music reproduction in a wireless terminal. The device includes a key input unit including at least one specific key for terminating reproduced music; and a controller for controlling termination of the reproduced music when an input of the specific key is maintained for at least a predetermined amount of time.

Abstract: An example embodiment includes a playback device that includes a capacitive proximity sensor; one or more speakers; a conductive speaker grille; and a control system that decouples a grounding plane of the capacitive proximity sensor from the conductive speaker grille while the one or more speakers are rendering audio and couples the grounding plane of the capacitive proximity sensor to the conductive speaker grille while the one or more speakers are not rendering audio.

Abstract: Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier.

Abstract: A processor includes: an exponent generating unit that generates an exponent part of a coefficient represented by a floating point number format based on a first part of received input data, the coefficient being obtained when an exponential function is decomposed into a series operation and the coefficient for the series operation; a storage unit that stores a mantissa part of the coefficient; a constant generating unit that reads constant data corresponding to a second part of the input data from the storage unit; and a selecting unit that selects and outputs the constant data from the constant generating unit when an instruction to be executed is a coefficient calculation instruction for calculation of the coefficient of the exponential function.

Abstract: A random number generating apparatus and method for generating on-demand random values using multiple hardware random noise sources; multiple analog-to-digital converters (ADC) for converting analog electrical signals into random digital values; a unit for selecting the random digital values and producing low bias random bytes; a unit for reducing bias and producing true random bytes; a continuous self-diagnostic logic (CSDL) for monitoring the health of the random noise sources and the quality of the generated random numbers.

Abstract: A control server receives information from detector agents associated with an application program being executed by a processor. The information, which is collected by the detector agents at runtime of the application, includes data with which the control server can generate a representation of the software architecture for the application. The control server compares the generated representation to representations of a set of known acceptable architectures. Based on the results of that comparison, the control server indicates whether the architecture of the application is a valid architecture. Recommendations for modifying the architecture of the application may be made in cases where the architecture is not deemed valid by the control server.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generated aggregated dependencies between software elements in a code base. One of the methods includes receiving a request to generate implicit dependencies introduced by remote procedure calls in a project. A registration of a remote procedure call is identified, wherein the registration of the remote procedure call specifies a target function and a name for the remote procedure call. An invocation of the remote procedure call using the name for the remote procedure call is identified, wherein the invocation occurs in a source software element of the project. A definition of the target function of the remote procedure call is identified, wherein the target function is defined in a target software element of the project. A new dependency is generated, the new dependency being a dependency from the source software element to the target software element.

Abstract: The disclosure includes a system and method for building an integrated system using a formal language. The method may include designing one or more models for one or more software components to be included in the integrated system. The one or more models may describe one or more requirements for the one or more software components. The method may include assigning one or more contracts written in the formal language to the one or more models. The method may include integrating the one or more models based on the composition of the one or more contracts to form an integrated model. The integrated model may include each requirement for the one or more software components. The method may include analyzing the one or more contracts and the integrated model to determine whether the one or more contracts include each requirement described by the integrated model.

Abstract: Software extensions for applications of an enterprise system may be developed in a test system. An adaptation transport module displays, in a test system, a plurality of semantic representations of software extension components for an application of an enterprise system. A semantic representation of a software extension for the application is generated based on a user selection of a combination of the semantic representations of software extension components. An adaptation object comprising the semantic representation of the software extension and at least one associated software object is generated by identifying the associated software object(s) based on an adaptation type of the adaptation object.

Abstract: Techniques for refactoring a screen-oriented computing program are described herein. The techniques include a method that identifies screens of the computing program, and determines a starting point of the computing program based on the identified screens. The techniques include refactoring the computing program based on the starting point and the identified screens.

Abstract: The technology disclosed relates to a self-service customization protocol for a single page website that implements a support component add-in to the CRM website. The self-service customization protocol includes a plurality of page elements that can be easily edited by the customers without any coding.

Abstract: While a runtime specializer may always be able to generate an automated specialized version of a generic class, in some cases an alternate form of user control over specialization may allow the use of automated specialization while also adding (or overriding) specialization-specific method implementations. In general, the set of members of a generic class may not change when the class is specialized. In other words, the same members may exist in the auto-specialized version as in the generic version. However, manual refinement of specialized classes may allow a developer to hand specialize a particular (possibly a better) representation and/or implementation of one or more methods of the specialized class.

Abstract: Techniques are described for improving compilation and optimization of application code based on generated metadata based on one or more dynamic measurements of the application code. In one example, a method comprises generating metadata based on one or more dynamic measurements of a code portion. The method further comprises associating the metadata with one or more selected segments of the code portion. The method further comprises deploying the one or more selected segments of the code portion with the associated metadata to a target unit for compilation and optimization.

Abstract: A software engine for decomposing work to be done into tasks, and distributing the tasks to multiple, independent CPUs for execution is described. The engine utilizes dynamic code generation, with run-time specialization of variables, to achieve high performance. Problems are decomposed according to methods that enhance parallel CPU operation, and provide better opportunities for specialization and optimization of dynamically generated code. A specific application of this engine, a software three dimensional (3D) graphical image renderer, is described.

Abstract: Technologies for shadow stack management include a computing device that, when executing a translated call routine in a translated binary, pushes a native return address on to a native stack of the computing device, adds a constant offset to a stack pointer of the computing device, executes a native call instruction to a translated call target, and, after executing the native call instruction, subtracts the constant offset from the stack pointer. Executing the native call instruction pushes a translated return address onto a shadow stack of the computing device. The computing device may map two or more virtual memory pages of the shadow stack onto a single physical memory page. The computing device may execute a translated return routine that pops the native return address from the native stack, adds the constant offset to the stack pointer, and executes a native return instruction. Other embodiments are described and claimed.

Abstract: Particular deployment logic is selected that describes a plurality of steps in a type of software deployment. Release data is identified that defines a selection of a set of software artifacts to be deployed in a particular deployment. Further, environmental data is selected that describes configuration of a target system for the particular deployment. First associations are determined, using data processing apparatus, between steps in the plurality of steps and software artifacts in the set of software artifacts. Second associations are determined between steps in the plurality of steps and configuration information of the target system used in the respective steps. The artifacts are automatically deployed on the target system, using one or more data processing apparatus, based on the first and second associations.

Abstract: A set of artifacts is identified for deployment on a target device in a deployment. The set of artifacts are from a source computing system remote from the target device. A cache device can be determined as corresponding to the target device, the cache device separate from the target device. The set of artifacts are pre-distributed on the cache device in advance of the deployment. The set of artifacts are sent to the cache device from the source computing system to be held at the cache device prior to the artifacts being distributed to the target device. The deployment follows distribution of the set of artifacts on the target device.

Abstract: A method for installing operating system software on a machine computer for controlling machines includes transmitting further operating system software, in addition to old operating system software already running on the machine computer, while the machine is operating. The method also includes installing the further operating system software on the machine computer while the machine is operating, transferring user data from the old operating system software to the further operating system software while the machine is operating, and switching off the machine computer and choosing between starting the old operating system software and starting the newly installed further operating system software when switching on the machine again.

Abstract: A device may receive an instruction to automatically install a program using a click area prediction model. The click area prediction model may be associated with predicting a click area of a user interface that, when selected, causes a program installation procedure to proceed. The device may identify an installation user interface associated with installing the program. The device may determine a group of regions included in the installation user interface. The device may identify sets of features associated with the group of regions. The device may determine, based on the sets of features and the click area prediction model, a group of scores associated with the group of regions. The device may identify a particular region as a predicted click area based on the group of scores. The device may select the predicted click area to attempt to cause the program installation procedure to proceed.

Abstract: Embodiments of the invention provide a method, system and computer program product for dynamic time out determination during a microcontroller driven firmware update. In an embodiment, the method includes selecting by a processor of a server a firmware update to be applied by a microcontroller to firmware of the server and computing a timeout value according to a function based upon a date of production of the server. The method also includes transmitting a request to the microcontroller to apply the selected firmware update to the firmware. Finally, the method includes determining a failure state responsive to detecting a lapse in time from the request beyond the timeout value without response by the microcontroller.

Abstract: A server, terminal device, and a non-transitory data storage medium for supporting wireless terminal devices of a cellular network for implementing program updates are described. The server includes a memory, a processor which receives instructions from the memory for execution, programs utilized in the wireless terminal devices, a receiver, and a transmitter. The receiver is configured to receive a message from a wireless terminal device requesting installation of a program to the wireless terminal device. The installation is caused by a change of an activated use profile of the wireless terminal device to another use profile, when the wireless terminal device is in an operating state with power on. The activated use profile and the another use profile include dissimilar lists of programs required in certain use situations of a user. The transmitter is configured to send the program to the wireless terminal device as an over-the-air message.

Abstract: A storage unit stores load information indicating the load of an information processing apparatus by applying each of a plurality of update programs to each virtual machine. An operation unit obtains the load information from the storage unit, and determines, for each virtual machine, an order of applying the plurality update programs to the virtual machine within a predetermined time period on the basis of the load information and an upper load limit allowable for the information processing apparatus.

Abstract: Method for generation of a live update including compiling original source code into a first intermediate representation (IR) code; compiling modified source code into second IR code; analyzing and comparing the first and second IR codes to identify variables and functions that were changed generating a part of final IR code with all the original variables and functions; generating an additional part of final IR code with new code for modified portions of the changed original functions, added functions and variables, and marking it for compilation into special code/data sections; and compiling a new object code and a final executable binary based on the final IR. The final executable object code includes the original code and data from original application binary, and a live update code and data from additional part of final IR generated. The live update code and data refer to original code and data where needed via standard object code relocation information.

Abstract: A system and method for software product versioning, packaging, distribution, and patching. The system provides for convergence of registry models, adding critical information to a home registry and simplifying processing algorithms in the install framework. In accordance with an embodiment, a product alias element is added to a Product Provisioning model, referencing one or more products. This provides a loose coupling between the external market-oriented product name and version, and the internal product names and versions. The internal product names and versions are captured in the registry and used for all code-based decisions during installation and other provisioning related activities. In accordance with an embodiment, a Feature Model is also added to the Product Provisioning model, and modules are grouped under features.

Abstract: Systems and methods are provided for an online programming community. A user may be able to view pre-existing code, modify the code, and save it as a spin-off program. Spin-offs of programs may be tracked. A social aspect may be provided where users can vote on community programs. Users may also be able to earn points or awards for various coding or programming community activities.

Abstract: A method for aggregating and reporting data from a plurality of data sources in a contact center is provided. The method includes: maintaining by a computer device aggregated data for a sliding interval including N+1 contiguous panes ordered from 0 to N, where N is greater or equal to 1; updating by the computer device the aggregated data for the sliding interval based on updates for the sliding interval received from one or more of the data sources; monitoring for expiration of one of the panes; and in response to determining that the one of the panes has expired, reporting the aggregated data for the sliding interval to a client.

Abstract: An arithmetic processing apparatus includes a plurality of arithmetic cores configured to execute threads in parallel, and a control unit configured to cause the arithmetic core to execute a reduction operation for data of the threads having the same storage area to which data is written per a predetermined number of threads in order to add data obtained by the reduction operation to data within a corresponding storage area by an atomic process.

Abstract: In general, according to one embodiment, an information processing apparatus includes an issuer and a communicator. The issuer issues an offload instruction corresponding to a first process executed in company with a first identifier capable of uniquely specifying a resource of a first arithmetic operation device. The communicator transmits the offload instruction to a second arithmetic operation device and receives a result of execution of the offload instruction from the second arithmetic operation device. In the second arithmetic operation device, the first identifier contained in the offload instruction is converted into a second identifier capable of uniquely specifying a resource of the second arithmetic operation device, and processing specified by the offload instruction is executed.

Abstract: A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand, and indicating a wider destination operand that is wider than and includes the narrower destination operand. A packed data operation mask is generated that includes a mask element for each corresponding result data element of a packed data result to be stored by the masked packed data operation. All mask elements that correspond to result data elements to be stored by the masked operation that would not be stored by the packed data instruction are masking out. The masked operation is performed using the packed data operation mask. The packed data result is stored in the wider destination operand.

Abstract: Multiple sets of character data having termination characters are compared using parallel processing and without causing unwarranted exceptions. Each set of character data to be compared is loaded within one or more vector registers. In particular, in one embodiment, for each set of character data to be compared, an instruction is used that loads data in a vector register to a specified boundary, and provides a way to determine the number of characters loaded. Further, an instruction is used to find the index of the first delimiter character, i.e., the first zero or null character, or the index of unequal characters. Using these instructions, a location of the end of one of the sets of data or a location of an unequal character is efficiently provided.

Abstract: Branch prediction is suppressed for specific branch instructions executing in a transaction of a transactional memory (TM) environment, when the specific branch instruction was previously executed in the transaction, in one embodiment the specific branch instruction is suppressed after a predetermined number of executions of the specific instruction in a transaction.

Abstract: A method and system are provided for deriving a resultant software program from an originating software program having overlapping branches, wherein the resultant software project has either no overlapping branches or fewer overlapping branches than the originating software program. A preferred embodiment of the invented method generates a resultant software program that has no overlapping branches. The resultant software is more easily converted into programming reconfigurable logic than the originating software program. Separate and individually applicable aspects of the invented method are used to eliminate all four possible states of two overlapping branches, i.e., forward branch overlapping forward branch, back branch overlapping back branch, and each of the two possible and distinguishable states of forward branch and back branch overlap. One or more elements of each aspect of the invention may be performed by one or more computers or processors, or by means of a computer or a communications network.

Abstract: A first and second thread-local counter is allocated to a first and second thread respectively, where the first thread-local counter is updatable only by or on behalf of the first thread and the second thread-local counter is updatable only by or on behalf of the second thread. The first and second thread-local counter are updated and the updated values are communicated to a central process. The central process updates a single counter in a central database by a value equal to the sum of the updated counter values.

Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.

Abstract: This document discusses, among other things, systems and methods to receive an instruction to selectively update a value of one or more selected bits of a first register, to receive the one or more selected bits of the first register to be updated and one or more selected bits of the first register to remain unchanged, and to selectively update the value of the one or more selected bits of the first register using a first write port without receiving the value of the one or more selected bits of the first register. In an example, the value of the one or more selected bits of the first register can be updated without receiving the value of the first register, in certain applications, reducing the number of read ports required to update the value of the first register.

Abstract: Instructions grouped into instruction groups are optimized across group boundaries. Instruction sequences spanning multiple groups are optimized by retaining information relating to an instruction at the end of one instruction group to be co-optimized with an instruction at the beginning of a subsequent instruction group. This retained information is then used in optimization of one or more instructions of the subsequent group. Optimization may be performed across n group boundaries, where n is equal to two or greater. Additionally, optimization of instructions within a group may be performed, in addition to the optimizations across group boundaries.

Abstract: According to embodiments disclosed herein, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer. In one embodiment, the computer processor includes: (1) a decode unit for decoding instruction packets fetched from a memory holding the instruction packets, (2) a control processing channel capable of performing control operations and (3) a data processing channel capable of performing data processing operations, wherein, in use the decode unit causes instructions of instruction packets comprising a plurality of only control instructions to be executed sequentially on the control processing channel, and wherein, in use the decode unit causes instructions of instruction packets comprising a plurality of instructions comprising at least one data processing instruction to be executed simultaneously on the data processing channel.

Abstract: Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction indicating an operation writing an immediate value to a register is detected by an instruction processing circuit. The circuit also detects at least one subsequent instruction indicating an operation that overwrites at least one first portion of the register while maintaining a value of a second portion of the register. The at least one subsequent instruction is converted (or replaced) with a fused instruction(s), which indicates an operation writing the at least one first portion and the second portion of the register.

Abstract: A system, method, and computer program product are provided for executing casting-arithmetic instructions. The method comprises receiving a casting-arithmetic instruction that specifies an arithmetic operation to be performed on input data and at least one casting operation of an input casting operation and an output casting operation. Upon determining that the casting-arithmetic instruction specifies the input casting operation, the input casting operation is performed on identified terms comprising the input data. Then the arithmetic operation is performed on the input data to generate an arithmetic result. Upon determining that the casting-arithmetic instruction specifies the output casting operation, the output casting operation is performed on the arithmetic result.

Abstract: The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor.

Abstract: A sequence of buffered instructions includes branch instructions. Branch prediction circuitry predicts if each branch instruction will result in a taken branch when executed. Normally, the fetch circuitry retrieves speculative instructions between the time that a source branch instruction is retrieved and the prediction if that source branch instruction will result in the taken branch. If the source branch instruction is predicted as taken, then the speculative instructions are discarded, and a count value indicates a number of instructions in the sequence between that source branch instruction and a subsequent branch instruction in the sequence that is also predicted as taken. Responsive to a subsequent occurrence of the source branch instruction predicted as taken, a throttled mode limits the number of instructions subsequently retrieved dependent on the count value, and then any further instructions are not retrieved for a number of clock cycles.

Abstract: A system, method, and computer program product are provided for scheduling interruptible hatches of instructions for execution by one or more functional units of a processor. The method includes the steps of receiving a batch of instructions that includes a plurality of instructions and dispatching at least one instruction from the batch of instructions to one or more functional units for execution. The method further includes the step of receiving an interrupt request that causes an interrupt routine to be dispatched to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units. When the interrupt request is received, the method further includes the step of storing batch-level resources in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution.

Abstract: Improving the tracking of read sets and write sets associated with cache lines of a transaction in a pipelined processor executing memory instructions having the read sets and write sets associated with the cache lines is provided. Included is active read set and write set cache indicators associated with the memory operation of executing memory instructions and associated with a recovery pool based on memory instructions being not-speculative are updated when the memory instruction is not-newer in program order than an un-resolved branch instruction. Based on encountering a speculative branch instruction in the processor pipeline, a representation of the active read sets and write sets is copied to the recovery pool. Based on completing the speculative branch instruction, updating the active read sets and write sets from the representations copied to the recovery pool associated with the branch instruction upon a detection of a misprediction.

Abstract: A system, method, and computer program product are provided for implementing a multi-cycle register file bypass mechanism. The method includes the steps of receiving a set of control bits, combining the set of control bits with a set of valid bits associated with previously issued instructions, and enabling a bypass path for each thread based on the set of control bits and the set of valid bits. Each valid bit in the set of valid bits indicates whether execution of an instruction of the previously issued instructions was enabled for a thread in a thread block.

Abstract: In an embodiment, a data processing method comprises receiving, at a mobile computing device, a request comprising a protocol identifier, a label value, and a data value, wherein the protocol identifier is associated with a protocol implemented in a first mobile app; using a protocol handler in the mobile computing device associated with the protocol, initiating processing of the request; using a native code element in the mobile computing device: intercepting the request when the label value matches a particular expression, and in response to the intercepting, providing the data value to other than the first mobile app, the protocol handler or the native code element; wherein the method is performed by one or more computing devices.

Abstract: A system and method to reduce the boot time of a data processing system by informing a memory device to send data prior to the boot time. The data processing system includes: a host system having a host processor and host memory; and (2) the memory device. The memory device is preconfigured in advance prior to the boot time with one or more Read commands with one or more corresponding physical addresses of host memory. This preconfiguration can be done at the time of system integration or before every boot operation. Once the system power-on occurs, the memory device sends the data in packets to the host memory. Whenever the host processor needs data it will be available in host memory which significantly reduces the boot time.

Abstract: Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, performance characteristics associated with each available CPU, the performance characteristics associated with each available CPU including information describing computing devices such as memory devices, input/output (‘I/O) devices, and other downstream devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the performance characteristics associated with each available CPU and a predetermined performance policy, a target CPU to utilize as a boot CPU.

Abstract: In a cloud computing environment, a production server virtualization stack is minimized to present fewer security vulnerabilities to malicious software running within a guest virtual machine. The minimal virtualization stack includes support for those virtual devices necessary for the operation of a guest operating system, with the code base of those virtual devices further reduced. Further, a dedicated, isolated boot server provides functionality to securely boot a guest operating system. The boot server is isolated through use of an attestation protocol, by which the boot server presents a secret to a network switch to attest that the boot server is operating in a clean mode. The attestation protocol may further employ a secure co-processor to seal the secret, so that it is only accessible when the boot server is operating in the clean mode.

Abstract: A file system independent virtualized boot block with discovery volume and cover files renders a volume visible when accessed by an accessing system which differs from a source system. For example, a downlevel operating system recognizes that data is present on a volume created in an uplevel operating system, even where the uplevel data itself may not be accessible.