Patents Issued in November 15, 2016
  • Patent number: 9494617
    Abstract: A probe card for use in testing a wafer and a method of making the probe card include a printed circuit board (PCB) formed with a conductor pattern and a probe head in proximity to the PCB, the probe head defining at least one hole through the probe head, and the probe head being made of an electrically insulating material. At least one conductive pogo pin is disposed respectively in the at least one hole, the pogo pin having a first end electrically connected to the conductor pattern on the PCB. At least one conductive probe pin includes a cantilever portion and a tip portion. The cantilever portion is in contact with and electrically connected to a second end of the pogo pin, and the tip portion is electrically connectable to the wafer to electrically connect the wafer to the conductor pattern on the PCB. The cantilever portion of the probe pin is fixedly attached to the probe head.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: November 15, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Shih-Duen Lin, Wen-Jen Ho, Chih-Pin Jen, Wei-Feng Lin, Yi-Chang Hsieh
  • Patent number: 9494618
    Abstract: Nanospike contactors suitable for semiconductor device test, and associated systems and methods are disclosed. A representative apparatus includes a package having a wafer side positioned to face toward a device under test and an inquiry side facing away from the wafer side. A plurality of wafer side sites are carried at the wafer side of the package. The nanospikes can be attached to nanospike sites on a wafer side of the package. Because of their small size, multiple nanospikes make contact with a single pad/solderball on the semiconductor device. In some embodiments, after detecting that the device under test passes the test, the device under the test can be packaged to create a known good die in a package.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 15, 2016
    Assignee: Translarity, Inc.
    Inventors: Douglas A. Preston, Morgan T. Johnson
  • Patent number: 9494619
    Abstract: A closed-loop current transducer comprising a magnetic circuit, a magnetic field detector, and a compensation coil assembly configured to generate a magnetic field opposing a magnetic field created by an electrical current to be measured flowing in one or more primary conductors extending through a central opening of the magnetic circuit. The magnetic circuit comprises a first branch, a second branch, and first and second end branches, interconnecting the first and second branches such that the branches surround a central passage through which the one or more primary conductors may extend, the second branch forming a receptacle that defines a cavity extending in an axial direction A for receiving a sensing portion of the magnetic field detector, the second branch comprising two second branch portions separated by an interface resulting from the bringing together of opposed ends of a single piece magnetic circuit.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: November 15, 2016
    Assignee: LEM Intellectual Property SA
    Inventors: Wolfram Teppan, Stéphane Claeys
  • Patent number: 9494620
    Abstract: A flexible current sensor arrangement comprises a plurality of discrete current sensing elements distributed along an elongate flexible carrier. An elongate flexible member for a current sensor arrangement comprises a plurality of carrying portions linked to one another by hinge portions, each carrying portion being configured for receiving a discrete current sensing element. A method of manufacturing a flexible current sensor arrangement comprises providing an elongate flexible carrier, and distributing a plurality of discrete sensing elements along the elongate flexible carrier.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 15, 2016
    Assignee: Sentec Ltd
    Inventors: Andrew Nicholas Dames, Mathew Price, Robert Davidson
  • Patent number: 9494621
    Abstract: A single point detecting current sensor includes a plurality of magnetic sensor modules, wherein a magnetic sensor module is installed onto each busbars with an insulation displacement contact or is installed adjacent to each busbar, and outputs the current through a busbars measured by a magnetic sensor; a signal collection module collecting measured signals output by the plurality of magnetic sensor modules; and a signal interference compensation module deriving a corrected current value for which interference has been removed, by calculating the mutual interference between said busbars using the signals collected by said signal collection module.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: November 15, 2016
    Assignee: RETIGRID CO., LTD.
    Inventors: Jong Chan Yoon, Young Ho Ahn
  • Patent number: 9494622
    Abstract: A current measurement device measures current flowing in a composite material M containing conductive fibers. The current measurement device includes a temperature measuring unit that measures the temperature of a surface of the composite material, upon flow of current in the composite material; a storage unit that stores conversion data that is acquired as a result of a conversion data acquisition test performed beforehand and that results from converting the temperature of the surface of the composite material to the value of the current flowing in the composite material; and a current calculator that, on the basis of the conversion data stored in the storage unit, converts the temperature of the surface of the composite material M as measured by the temperature measuring unit to a value of the current flowing in the composite material.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: November 15, 2016
    Assignee: FUJI JUKOGYO KABUSHIKI KAISHA
    Inventor: Hiroyuki Tsubata
  • Patent number: 9494623
    Abstract: A mechanism for providing monitoring of electric field detectors. In accordance with instructions on a machine-readable medium, a computing system receives from a device data corresponding to a user identifier. Further, the computing device identifies from a plurality of electric field detectors one or more electric field detectors associated with the user identifier and identifies status data for each of the identified one or more electric field detectors. The status data for each electric field detector in the plurality of electric field detectors comprises data indicative of at least (i) a location of the electric field detector and (ii) an alarm state of the electric field detector. Additionally, the computing system causes a display component of the device to display a graphical user interface that presents indicia of the status data for each of the identified one or more electric field detectors.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: November 15, 2016
    Assignee: HD Electric Company
    Inventor: William J. McNulty
  • Patent number: 9494624
    Abstract: A method of real-time monitoring of the operation of a wind turbine in an operational region of theoretically constant power coefficient is disclosed. The method comprises measuring the electrical power generated by the wind turbine, a representative wind speed, and an ambient temperature. The wind power available to the wind turbine for a given moment in time may be calculated based on the measured ambient temperature and measured representative wind speed. The aerodynamic power captured by the wind turbine at the same moment in time may be determined based on the measured electrical power generated. And the practical power coefficient may be calculated by dividing the aerodynamic power captured by the calculated available wind power.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: November 15, 2016
    Assignee: ALSTOM RENOVABLES ESPANA, S.L.
    Inventor: Josep Prats Mustarós
  • Patent number: 9494625
    Abstract: A management system for managing measurement information on power consumption in at least one electrical appliance which is associated with at least one meter includes a first storage module configured to store measurement information transmitted from each of the at least one meter associated with the at least one electrical appliance, on power consumption in the at least one electrical appliance, in correspondence with the at least one meter. The management system also includes a second storage module configured to store history information on association between each of the at least one meter and the at least one electrical appliance.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: November 15, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Misuzu Doi, Yohhei Iwami, Yumiko Kawazoe, Satoshi Kishi, You Ka, Hirosuke Miki, Hiroyoshi Toda
  • Patent number: 9494626
    Abstract: A constant period signal monitoring circuit for monitoring a constant period signal that is output periodically when a control processor operating according to a program is normal, includes a signal input terminal that receives the constant period signal, an edge detection section that detects a change of the constant period signal appearing at the signal input terminal from a low level to a high level or from a high level to a low level as an edge of the constant period signal, and a time measuring section that measures a length of the time during which a state of not detecting the edge continues on the basis of an output of the edge detection section and outputs an abnormality detection signal in a case that the measured time exceeds a threshold value.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: November 15, 2016
    Assignee: YAZAKI CORPORATION
    Inventor: Kazuhisa Wataru
  • Patent number: 9494627
    Abstract: A technique for recognizing and rejecting false activation events related to a capacitance sense interface includes measuring a capacitance value of a capacitance sense element. The measured capacitance value is analyzed to determine a baseline capacitance value for the capacitance sensor. The capacitance sense interface monitors a rate of change of the measured capacitance values and rejects an activation of the capacitance sense element as a non-touch event when the rate of change of the measured capacitance values have a magnitude greater than a threshold level, indicative of a maximum rate of change of a touch event.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: November 15, 2016
    Assignee: MONTEREY RESEARCH, LLC
    Inventors: Louis W. Bokma, Andrew C. Page, Dennis R. Seguine
  • Patent number: 9494628
    Abstract: An embodiment of a capacitance measurement circuit may include multiple switches, a first node coupled with a first electrode and coupled with at least a first switch of the multiple switches, and a second node coupled with a second electrode and coupled with at least a second switch of the multiple switches, where the multiple switches are configured to reduce an influence of a self-capacitance of the first electrode and a self-capacitance of the second electrode on an output signal during measurement of a mutual capacitance between the first electrode and the second electrode, and where the multiple switches are configured to reduce an influence of the mutual capacitance on the output signal during measurement of at least one of the self-capacitance of the first electrode and the self-capacitance of the second electrode.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: November 15, 2016
    Assignee: PARADE TECHNOLOGIES, LTD.
    Inventor: Andriy Maharyta
  • Patent number: 9494629
    Abstract: The invention relates to a method and an apparatus for capacitive seat-occupancy recognition for vehicle seats. The apparatus which is based on the method comprises a reference capacitor that possesses a capacitance with respect to a first reference potential of a vehicle, an electrode integrated into a seat sensor that possess a capacitance with respect to a first reference potential, an at least parasitically-present capacitance of the sensor electrode with respect to a second reference potential or the vehicle ground, a first switch that connects the reference capacitor and a reference-voltage source of known voltage connected with the reference potential, a second switch that connects the sensor electrode with reference capacitor, and a third switch that connects the sensor electrode with the reference potential and the at least parasitically-present capacitance with the vehicle ground.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: November 15, 2016
    Assignee: I.G. BAUERHIN GMBH
    Inventors: Axel Farr, Jochen Michelmann
  • Patent number: 9494630
    Abstract: The present application provides a method for adjusting an electric field intensity, comprising: when detecting that a probe capacitance threshold generated by a capacitor plate group reaches a preset critical value, changing relative positions of or a connection relationship between capacitor plates in the capacitor plate group, and adjusting an electric field intensity generated by the capacitor plate group. By using the method for adjusting an electric field intensity of the present application, when an electric field intensity generated by a capacitor plate group cannot cover an object to be detected, the electric field intensity generated by the capacitor plate group is increased by changing relative positions of or a connection relationship between capacitor plates, so that the electric field intensity generated by the capacitor plate group can continue to cover the object to be detected.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: November 15, 2016
    Assignees: Beijing Lenovo Software Ltd., Lenovo (Beijing) Co., Ltd.
    Inventors: Guang Yang, Qi Li
  • Patent number: 9494631
    Abstract: A new method of extracting information from a current waveform for the purpose of controlling a resonant converter is presented. The method comprises the step of sampling the converter waveform exactly three times in half a period of the converter waveform or sampling the converter waveform exactly at three different positions in a sequence on different periods of the converter waveform and the step of extracting waveform information to produce a fundamental component and a triangular component of the converter waveform. The information could also be used for the purpose of predicting the inductance and load of a circuit to indicate alignment in a inductive charging system.
    Type: Grant
    Filed: May 5, 2013
    Date of Patent: November 15, 2016
    Assignee: DET International Holding Limited
    Inventor: Marco Antonio Davila
  • Patent number: 9494632
    Abstract: A mechanism for providing monitoring of electric field detectors. In accordance with instructions on a machine-readable medium, a computing system receives from a device data corresponding to a user identifier. Further, the computing device identifies from a plurality of electric field detectors one or more electric field detectors associated with the user identifier and identifies status data for each of the identified one or more electric field detectors. The status data for each electric field detector in the plurality of electric field detectors comprises data indicative of at least (i) a location of the electric field detector and (ii) an alarm state of the electric field detector. Additionally, the computing system causes a display component of the device to display a graphical user interface that presents indicia of the status data for each of the identified one or more electric field detectors.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: November 15, 2016
    Assignee: HD Electric Company
    Inventor: William J. McNulty
  • Patent number: 9494633
    Abstract: Provided is an electromagnetic interference (EMI) measuring device. The EMI measuring device according to the present invention includes an electromagnetic wave eliminating unit eliminating remaining electromagnetic waves from a DUT in response to an eliminating control signal of the control unit. The control unit may calculate EMI of the DUT on the basis of a measured result measured before the elimination of remaining electromagnetic waves. The EMI measuring device according to the present invention may compensate for an error due to remaining electromagnetic waves and measure EMI at high accuracy.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: November 15, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Soon Il Yeo
  • Patent number: 9494634
    Abstract: A current tester includes: a probe, a computing device for converting a voltage drop across a component to a current, and an output device for signaling a presence or non-presence of current. The computing device stores a pre-determined voltage drop/current relationship for the component. A method for detecting current in a circuit includes: connecting a current tester to the component, measuring a voltage drop across the component, converting the voltage drop to a current via the current tester, and producing a signal by the current tester indicating a presence or non-presence of current in the circuit. A method for detecting current in a circuit may also comprises: connecting probes of a testing device to a component in the circuit; determining via whether the probes are properly connected to the component; and determining a voltage drop across the component to determine the presence or non-presence of current.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: November 15, 2016
    Inventor: Kevin M. Curtis
  • Patent number: 9494635
    Abstract: A device is disclosed for detecting an islanding condition in an electricity distribution network, by receiving a signal of the electricity distribution network, and determining an islanding condition based on the received signal. The device determines a voltage total harmonic distortion change parameter for each phase component in the received signal, determines a voltage unbalance change parameter in the received signal, compares each of the voltage total harmonic distortion change parameters and the voltage unbalance change parameter to respective triggering conditions, and concludes an islanding condition to have been detected when the voltage total harmonic distortion change parameter for each phase component of the signal and the voltage unbalance change parameter fulfill their respective triggering conditions.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: November 15, 2016
    Assignee: ABB Schweiz AG
    Inventor: Hannu Laaksonen
  • Patent number: 9494636
    Abstract: In one example, a method includes outputting, during a first phase, a first current level at a connector, and outputting, during a second phase, a second current level at the connector, wherein the second current level is complementary to the first current level. In this example, the method also includes determining whether or not a voltage level of the connector satisfies a threshold, and responsive to determining that the voltage level of the connector satisfies the threshold, determining that the connector is floating.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: November 15, 2016
    Assignee: Infineon Technologies AG
    Inventors: Chin Yeong Koh, Martin Krueger
  • Patent number: 9494637
    Abstract: A method and an arrangement are disclosed for detecting islanding operation of a distributed power generator. The method can include determining a frequency of a grid to which the distributed power generator is connected, measuring a rate of change of the frequency of the grid at an output of the distributed power generator, determining a threshold value for an alteration speed, comparing the rate of change of the frequency of the grid with the threshold value, and detecting islanding operation when the measured rate of change of the frequency exceeds the threshold value for a certain time period.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: November 15, 2016
    Assignee: ABB Oy
    Inventors: Janne Hellberg, Kimmo Heinonen, Jari Uusimäki
  • Patent number: 9494638
    Abstract: The device for checking electronic cards includes a base in which conductive nails are arranged pointing upwards, and a cover, also fitted with nails pointing downwards in the closed cover position. The cover is mobile in horizontal translation between an open position and an intermediate position. The device can also include a vertical translation mechanism capable of bringing the nails arranged in the cover closer to the nails arranged in the base so as to allow contact of the nails on the two faces of an electronic card. The invention also relates to a method of opening and a method of closing such a device.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: November 15, 2016
    Assignee: Larisys Industries
    Inventors: Morad Mahdjoub, Marjorie Charrier, Celine Constant
  • Patent number: 9494639
    Abstract: An inspection apparatus includes a first tester and a second tester each of which tests a substrate loaded therein, a first stage on which the first tester is mounted, the first stage being movable to a first loading and unloading position and a first test position, the first test position being provided above the first loading and unloading position, a second stage on which the second tester is mounted, the second stage being provided below the first stage and being movable to a second loading and unloading position and a second test position, the second test position being provided below the second loading and unloading position, and a lift mechanism that moves the first stage up and down to the first loading and unloading position and the first test position and moves the second stage up and down to the second loading and unloading position and the second test position.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: November 15, 2016
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Hiroyasu Watanabe
  • Patent number: 9494640
    Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: November 15, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9494641
    Abstract: A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: November 15, 2016
    Assignee: Nvidia Corporation
    Inventors: Brian Smith, Stephen Felix, Tezaswi Raja, Roman Surgutchik
  • Patent number: 9494642
    Abstract: A test pusher assembly, useful in association with a thermal control unit used to maintain a set point temperature on an integrated circuit device under test, is provided with ejection mechanisms configured to facilitate the disengagement of the DUT at the end of the test. One example of the ejection mechanisms is to provide the substrate pusher assembly with spring-loaded pins that can push the substrate of the DUT away from the pedestal at the end of the test. Another example of the ejection mechanisms is to use a pressurized fluid that can push the substrate of the DUT away from the pedestal at the end of the test.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: November 15, 2016
    Assignee: Essai, Inc.
    Inventors: Nasser Barabi, Chee Wah Ho, Joven R. Tienzo, Oksana Kryachek, Elena V. Nazarov
  • Patent number: 9494643
    Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 15, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9494644
    Abstract: A semiconductor device in which the area of a circuit that is unnecessary during normal operation is small. The semiconductor device includes a first circuit and a second circuit. The first circuit includes a third circuit storing at least one pair of first data including a history of a branch instruction and a first address corresponding to the branch instruction; a fourth circuit comparing a second address of an instruction and the first address; and a fifth circuit selecting the first data of one pair among the at least one pair in accordance with a comparison result. The second circuit includes a plurality of sixth circuits having a function of generating a signal for testing operation of the first circuit in accordance with second data, and a function of storing the at least one pair together with the second circuit after the operation is tested.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 9494645
    Abstract: The present invention relates to a method for testing cryptography circuits. It also relates to a secure cryptography circuit capable of being tested. The cryptography circuit includes registers and logic gates, and a test thereof performs a differential power analysis on the registers of the circuit. A cryptography circuit being secure and including a first half-circuit associated with a second half-circuit operating in complementary logic, the electric power supply of the first half-circuit is separated from the electric power supply of the second half-circuit, the differential power analysis being carried out in parallel on each half-circuit, the two power supplies being combined into one and the same electric power supply after the test.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: November 15, 2016
    Assignee: INSTITUT TELECOM-TELECOM PARIS TECH
    Inventors: Sylvain Guilley, Jean-Luc Danger
  • Patent number: 9494646
    Abstract: An integrated circuit, such as for example an application specific integrated circuit, as well as a method of testing such a circuit, are disclosed herein. In one example embodiment, the integrated circuit includes a plurality of pins including a power pin, a ground pin, and a first communication pin, a test mode circuit, and a communication circuit. The integrated circuit additionally includes a first switch connected to the first communication pin, where the first switch is configured to couple the first communication pin to either the test mode circuit or the communication circuit. The integrated circuit further includes a control circuit coupled to the first switch and configured to control whether the first switch is operated to couple the first communication pin to the test mode circuit or to the communication circuit based upon or in response to an operating mode.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: November 15, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Divya Pratap, Sung Jin Jo
  • Patent number: 9494647
    Abstract: Systems and methods of data inversion, circuitry, detection and/or schemes are disclosed. According to illustrative implementations, exemplary circuitry may include static detection or detection circuitry such as those involving static current sources to detect a threshold for data inversion, pre-conditioning of detection circuitry, and/or active detection circuitry or schemes. In some implementations, exemplary memory or data inversion circuitry may comprise a transistor array, a bias generator, and a sense amplifier, wherein the transistor array may comprise at least one pair of transistor circuits arranged so that an output of the transistor array is provided as a sum or function of signal/current outputs of at least some of the transistor circuits in the array. As set forth, various systems, methods and circuitry herein may posses only a 3 static gate delay, such that very high speed and/or fast flow-through is achieved.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: November 15, 2016
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Patrick T. Chuang, Mu-Hsiang Huang, Jae Hyeong Kim
  • Patent number: 9494648
    Abstract: This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined number of least significant bits overlapping a predetermined number of most significant bits. Each client receives the least significant bits. Each client associates captured data with a corresponding set of the least significant bits in a message. A central scheduling unit associates most significant bits of the time stamp value with the least significant bits of the message. This associating compares overlap bits of the most significant bits and least significant bits. The most significant bits are decremented until the overlap bits are equal.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 15, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 9494649
    Abstract: An integrated circuit (IC) measures uncertainties in a first signal. The IC comprises a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal. The IC further comprises a digital delay line (DDL) comprising a first delay chain of delay elements having input to receive the first delayed signal. The DDL further comprises a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading. The DDL additionally comprises a decoder to generate a digital signature from the digital reading and a controller to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: November 15, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arun S. Iyer, Prashanth Vallur, Shraddha Padiyar, Amit Govil
  • Patent number: 9494650
    Abstract: Efficient production testing of integrated circuits. A first production test is implemented on a group of integrated circuits and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that integrated circuits having a recoverable fail and integrated circuits having a non-recoverable fail are differentiated. The integrated circuits are integrated based on the analyzed results and a second production test is implemented. The second production test tests the integrated circuits responsive to the segregation, such that the second production test is limited only to integrated circuits with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having integrated circuits not to be re-tested.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Teck Seng Eng, Michael Russell Uy Gonzales, Louie Que Hermosura
  • Patent number: 9494651
    Abstract: Functional diagnostic testing of an electronic circuit board assembly with one or more embedded channels to be tested includes steps of: (a) connecting a channel under test; (b) imposing a known digital or analog voltage, as appropriate for a channel under test, that is generated by a digital or analog output of the electronic circuit board assembly; and (c) comparing data read by the channel under test with the stored value of the imposed voltage and required tolerance to determine whether the channel under test is within specifications. Diagnostic test implemented by digital logic and software residing onboard the electronic circuit board assembly. Execution of software or firmware code segment controls the diagnostic test sequence. Signal switching is facilitated by digital and analog multiplexers.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: November 15, 2016
    Assignee: Honeywell Limited
    Inventor: Andrzej Wlodzimierz Nawrocki
  • Patent number: 9494652
    Abstract: The embodiments described herein include a system and a method. One embodiment provides a sensing apparatus for a battery system having a plurality of cells. The sensing apparatus includes an elongated substrate configured to extend along one side of the plurality of cells and a plurality of sensors, each corresponding to a respective one of the plurality of cells, and each configured to contact its respective cell.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: November 15, 2016
    Assignee: Johnson Controls Technology Company
    Inventor: Gary P. Houchin-Miller
  • Patent number: 9494653
    Abstract: A battery pack monitoring apparatus detects line breakage of detection lines on a highest potential side and a lowest potential side of a battery pack. In the apparatus, a battery cell voltage detection section detects a voltage of each of battery cells through detection lines connected to both electrodes of the battery cells. A battery pack voltage detection section detects a voltage of the battery pack through the highest potential side detection line and the lowest potential side detection line of the battery pack. Diodes are connected in parallel to respective battery cells on the highest and lowest potential sides in a forward direction from a negative electrode toward a positive electrode. A control section determines that one of the lines is broken when a sum of the voltage of each of the battery cells detected and the voltage of the battery pack detected are not equal to each other.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: November 15, 2016
    Assignee: OMRON AUTOMOTIVE ELECTRONICS CO., LTD.
    Inventors: Masakazu Okaniwa, Naoki Kitahara
  • Patent number: 9494654
    Abstract: A semiconductor device has a first and a second external terminals coupled to power supply wiring that couples one end of a current detecting resistance and a power supply terminal of a battery, a third external terminal coupled to an other end of the current detecting resistance, and a control circuit for controlling an output of a second measurement current destined to the third external terminal, and measures a voltage difference between the first external terminal and the second external terminal.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: November 15, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideki Kiuchi
  • Patent number: 9494655
    Abstract: Disclosed are an apparatus and a method for diagnosing a state of a fuel cell stack with high accuracy by reducing the deviation of a harmonic component although the voltage variation of the fuel cell stack is substantial. According to the present invention, a harmonic component is detected by converting the difference between the voltage of the fuel cell stack and a moving average voltage to a frequency and the state of the fuel cell stack is diagnosed based on the size of the detected harmonic component.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: November 15, 2016
    Assignee: Hyundai Motor Company
    Inventors: Kwi Seong Jeong, Sang Bok Won, Young Bum Kum, Jae Jun Ko
  • Patent number: 9494656
    Abstract: Systems (50, 200) and methods for determining a state of charge of a battery (52, 102, 150, 202) are provided. The system (50, 200) includes a power source (56, 206) configured to provide a charging current to a battery (52, 102, 150, 202). A controller (54, 104, 204) is included and configured to determine a state of charge of the battery (52, 102, 150, 202) based on impedance of a battery (52, 102, 150, 202) during a discharge time period based on an impedance and a state of charge relationship of a battery (52, 102, 150, 202) during a charge time period.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: November 15, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Chidong Yao
  • Patent number: 9494657
    Abstract: Systems, methods and devices which utilize Spread Spectrum Time Domain Reflectometry (SSTDR) techniques to measure degradation of electronic components are provided. Such measurements may be implemented while the components “live” or otherwise functioning within an overall system. In one embodiment, monitoring a power converter in a high power system is accomplished. In this embodiment, degradation of components within the power converter (e.g. metal-oxide-semiconductor field-effect transistors (MOSFETs), capacitors, insulated-gate bipolar transistors (IGBTs), and the like) may be monitored by processing data from reflections of an SSTDR signal to determine changes in impedance, capacitance, or any other changes that may be characteristic of components degrading. For example, an aging MOSFET may experience an increase of drain to source resistance which adds additional resistance to a current path within a power converter.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: November 15, 2016
    Assignee: University of Utah Research Foundation
    Inventors: Faisal Khan, Most. Sultana Nasrin
  • Patent number: 9494658
    Abstract: A method of optimally generating a power failure warning (PFW) signal has been disclosed here in such a manner that adjusts timing of PFW signal generation according to load conditions in case of input AC voltage loss. A PFW voltage threshold value can be set at a lower value under light load conditions and at a higher value under heavy load conditions. PFW signal generation can also be triggered by a timing mechanism that is set when a bus voltage drops to a voltage threshold value. A countdown time of the timing mechanism is set according to a determined bus voltage drop rate. In this manner, issuance of the PFW signal is delayed for lighter load conditions and the power supply unit is capable of extending normal operation under lighter load conditions before the PFW signal is issued.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 15, 2016
    Assignee: Flextronics AP, LLC
    Inventors: Zhen Z. Ye, Xiangping Xu
  • Patent number: 9494659
    Abstract: The invention relates to a method for checking a photovoltaic inverter separator (14) between the photovoltaic inverter (1) and a power supply network (7), comprising multiple phases (L1, L2, L3) and a neutral conductor (N), wherein multiple switching contacts of the separator (14) are controlled by the photovoltaic inverter (1), and the invention also relates to a photovoltaic inverter (1). The aim of the invention is to allow a simple and quick check of the functionality of the separator (14). This is achieved in that the switching contacts of the separator (14) are connected and checked in steps according to a switching pattern. In each step, each voltage (30, 31, 32 and 33, 34, 35) is measured at at least one phase (L1, L2, L3) upstream and downstream of the separator (14) in relation to the neutral conductor (N), and the voltages are compared to one another.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: November 15, 2016
    Assignee: Fronius International GmbH
    Inventors: Joachim Danmayr, Stefan Bloechl
  • Patent number: 9494660
    Abstract: A magnetic field sensor includes a lead frame having a plurality of leads, at least two of which have a connection portion and a die attach portion. A semiconductor die is attached to the die attach portion of the at least two leads. In some embodiments, at least one passive component is attached to the die attach portion of at least two leads.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 15, 2016
    Assignee: Allegro Microsystems, LLC
    Inventors: Paul David, William P. Taylor, P. Karl Scheller, Ravi Vig, Andreas P. Friedrich
  • Patent number: 9494661
    Abstract: A three-dimensional Hall sensor can be used for detecting a spatial magnetic field. A method for measuring a spatial magnetic field can be performed using this Hall sensor. The Hall sensor comprises an electrically conducting base body and at least three electrode pairs, wherein each electrode pair has a first terminal and a second terminal, which are arranged such on the base body, that a current can flow from the first terminal to the second terminal through the base body. At least three first terminals are arranged on a first surface of the base body and at least three second terminals are arranged on the second surface, different from the first surface of the base body, wherein the first and the second surfaces oppose each other.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: November 15, 2016
    Assignee: Micronas GmbH
    Inventors: Oliver Paul, Patrick Ruther, Aftab Taimur
  • Patent number: 9494662
    Abstract: In a method and magnetic resonance apparatus for automatic calculation of a maximum pulse length of a non-selective excitation pulse for a magnetic resonance data acquisition pulse sequence in which gradients are switched during the radiation of at least one non-selective excitation pulse, a first parameter, which indicates the field of view (FOV) desired in the measurement for which the pulse length of the excitation pulse should be maximized, is loaded into a processor, and a second parameter, which indicates the maximum gradient strength (Gmax) which corresponds to the highest gradient strength applied in the entire measurement, is also loaded into the processor. The processor then calculates the maximum pulse length of the excitation pulse on the basis of the first and second parameter. By the maximization of the pulse length, the SAR exposure is reduced for the examination subject from whom the magnetic resonance data are acquired with the pulse sequence.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 15, 2016
    Assignee: Siemens Aktiengesellschaft
    Inventor: David Grodzki
  • Patent number: 9494663
    Abstract: An NMR spectrometer and method in the following three steps are performed. (1) An external magnetic field is set to H0+?H (where 4H>0). When the detection coil made of the superconducting material is still in a normal state, a magnetic field stronger than the ultimate target static magnetic field strength H0 by ?H is applied to the detection coil. (2) The detection coil made of the superconducting material is cooled down to T0 lower than its critical temperature Tc to bring the coil into a superconducting state while the external magnetic field H0+?H is applied to the detection coil. (3) The external magnetic field is lowered from H0+?H to H0 such that the applied external magnetic field is decreased by ?H while the detection coil is kept in the superconducting state.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: November 15, 2016
    Assignee: JEOL Ltd.
    Inventors: Shigenori Tsuji, Fumio Hobo, Ryoji Tanaka, Hiroto Suematsu
  • Patent number: 9494664
    Abstract: Systems and methods for coil arrangements in Magnetic Resonance Imaging (MRI) are provided. One arrangement includes a magnet bore, a radio-frequency (RF) transmit coil coupled to the magnet bore and at least one RF neck coil coupled to the magnet bore. The RF neck coil is movable within the magnet bore under and separate from a table within the magnet bore.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: November 15, 2016
    Assignee: General Electric Company
    Inventors: Victor Taracila, Fraser Robb, Miguel Angel Navarro, Darren Charles Gregan
  • Patent number: 9494665
    Abstract: A magnetic resonance method is disclosed. The method comprises applying to the sample a plurality of pairs of bipolar gradient pulse subsequences, acquiring a magnetic resonance signal from the sample, analyzing the signal, and issuing a report regarding the analysis.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: November 15, 2016
    Assignee: Ramot at Tel-Aviv University Ltd.
    Inventors: Yoram Cohen, Noam Shemesh
  • Patent number: 9494666
    Abstract: Methods, computer program products, NMR assays and automated/semi-automated systems measure concentrations of ionized calcium and/or magnesium or other metabolites in clinical biosamples using NMR data obtained from an NMR spectrometer, such as a clinical NMR Analyzer.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: November 15, 2016
    Assignee: LIPSCIENCE, INC.
    Inventors: Elias Jeyarajah, John Contois, Lili Duan, Qun Zhou, Steve Markham, Dennis Bennett, James D. Otvos