Patents Issued in November 15, 2016
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Patent number: 9495217Abstract: A method, apparatus and program product utilize an empirical approach to determine the locations of one or more IO adapters in an HPC environment. Performance tests may be run using a plurality of candidate mappings that map IO adapters to various locations in the HPC environment, and based upon the results of such testing, speculative adapter affinity information may be generated that assigns one or more IO adapters to one or more locations to optimize adapter affinity performance for subsequently-executed tasks.Type: GrantFiled: July 29, 2014Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Wen C. Chen, Tsai-Yang Jea, Wiliam P. LePera, Hung Q. Thai, Hanhong Xue, Zhi Zhang
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Patent number: 9495218Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.Type: GrantFiled: February 17, 2016Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Ronald D. Rose
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Patent number: 9495219Abstract: Techniques are described for providing capabilities to dynamically migrate computing nodes between two or more computer networks while the computer networks are in use, such as to dynamically and incrementally migrate an entire originating first computer network to a destination second computer network at a remote location. For example, the first computer network may include one or more physically connected computer networks, while the second computer network may be a virtual computer network at a remote geographical location (e.g., under control of a network-accessible service available to remote users). The provided capabilities may further include facilitating the ongoing operations of the originating first computer network while a subset of the first computer network computing nodes have been migrated to the remote destination second computer network, such as by forwarding communications between the first and second computer networks in a manner that is transparent to the various computing nodes.Type: GrantFiled: July 6, 2012Date of Patent: November 15, 2016Assignee: Amazon Technologies, Inc.Inventor: Daniel T. Cohn
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Patent number: 9495220Abstract: Methods, systems, and computer-readable storage media for configuring a request-centric system. Implementations include actions of monitoring operation of the request-centric system to determine a workload of the request-centric system, wherein the workload includes a plurality of requests, determining a mapping function based on a utility function, the workload and a configuration, the mapping function mapping the workload and the configuration into the utility function, determining an optimal configuration based on the mapping function, the optimal configuration allocating resources of the request-centric system to achieve one or more predefined goals, and applying the optimal configuration to the request-centric system.Type: GrantFiled: September 28, 2012Date of Patent: November 15, 2016Assignee: SAP SEInventor: Roman Talyansky
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Patent number: 9495221Abstract: A method and system for configuring information for a distributed computing environment is provided. The method and system comprises providing a job containing a list of tasks to a controller, the tasks including a bootstrap tool and configuration information related to the computer network. The method and system also comprises providing a task to each of a plurality of agents on the distributed computer network, each task being based on one of the tasks of the job. The method and system further comprises executing code by each of the plurality of agents based upon the tasks process, wherein the code provides configuration information for a master process and a plurality of slave processes within the distributed computer network. The present invention allows processes run on a distributed set of computers to be provided with appropriate configuration files without requiring the master node to pre-generate those files ahead of time.Type: GrantFiled: October 23, 2009Date of Patent: November 15, 2016Assignee: Apple Inc.Inventor: David A. Kramer
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Patent number: 9495222Abstract: Systems and methods relate to indexing of performance and cost of workloads in a computing environment. The computing environment may include a virtualized computing environment. According to some embodiments, a performance index relating to a plurality of workloads executing in the computing environment may be generated, where the performance index is based at least in part on performance and cost of use of one or more resources in the computing environment by the plurality of workloads. The index may be normalized. If the performance or cost of a particular workload departs from an expected performance or cost determined from the average performance and/or cost in the computing environment, resources may be reallocated to the workloads such that the performance or cost of the workload is closer to its expected performance or cost based on the performance index.Type: GrantFiled: August 24, 2012Date of Patent: November 15, 2016Assignee: Dell Software Inc.Inventor: Philip Eric Jackson
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Patent number: 9495223Abstract: The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.Type: GrantFiled: December 23, 2014Date of Patent: November 15, 2016Assignee: Global Supercomputing CorporationInventors: Kemal Ebcioglu, Emre Kultursay
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Patent number: 9495224Abstract: A mechanism is provided for switching a locking mode of an object in a multi-thread program. The mechanism acquires, during execution of the program, access information related to accesses to the object by a plurality of threads. The object supports a single-level locking mode and a multi-level locking mode. The single-level locking mode is a mode capable of locking the object. The multi-level locking mode is a mode capable of locking the object and fields in the object respectively. The mechanism switches the locking mode of the object between the single-level locking mode and the multi-level locking mode based on the access information.Type: GrantFiled: September 11, 2013Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Rui Bo Han, Wei Liu, Xue Fu Sha, Bin Sun
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Patent number: 9495225Abstract: A thread priority control mechanism is provided which uses the completion event of the preceding transaction to raise the priority of the next transaction in the order of execution when the transaction status has been changed from speculative to non-speculative. In one aspect of the present invention, a thread-level speculation mechanism is provided which has content-addressable memory, an address register and a comparator for recording transaction footprints, and a control logic circuit for supporting memory synchronization instructions. This supports hardware transaction memory in detecting transaction conflicts. This thread-level speculation mechanism includes a priority up bit for recording an attribute operand in a memory synchronization instruction, a means for generating a priority up event when a thread wake-up event has occurred and the priority up bit is 1, and a means for preventing the CAM from storing the load/store address when the instruction is a non-transaction instruction.Type: GrantFiled: October 24, 2013Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Jacobi, Marcel Mitran, Moriyoshi Ohara
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Patent number: 9495226Abstract: Techniques to integrate client side applications into a fantasy open platform environment include a server processor component operating within the fantasy open platform environment and operative to provide application programming interface (API) data of the client side application code to the fantasy open platform environment. The client side application may be independent from the fantasy open platform environment. Hooks may be created to allow embedding of the client side application code on the fantasy open platform environment web pages wherein the client side application code identifies on which of the fantasy open platform environment web pages the client side application code runs. A client side application executing on a client browser may be allowed to access resources of the fantasy open platform environment over a network connection.Type: GrantFiled: November 30, 2012Date of Patent: November 15, 2016Assignee: CBS Interactive Inc.Inventor: Antonio L. Fernandez
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Patent number: 9495227Abstract: A system and method that includes receiving an API request to a type of API resource; retrieving an API concurrency value for the API request; determining a comparison status associated with a comparison of the API concurrency value to a concurrency threshold; if the comparison status is within the concurrency threshold, transmitting the API request to an API processing resource; if the comparison status indicates the concurrency threshold is not satisfied, impeding processing of the API request; accounting for an increase in the API concurrency value if the API request is transmitted to an API processing resource; and accounting for a decrease in the API concurrency value at a time associated with the API processing resource completing processing of the API request.Type: GrantFiled: February 11, 2013Date of Patent: November 15, 2016Assignee: Twilio, Inc.Inventors: Evan Cooke, Frank Stratton, Kyle Conroy
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Patent number: 9495228Abstract: A multi-process interactive system is described. The system includes numerous processes running on a processing device. The processes include separable program execution contexts of application programs, such that each application program comprises at least one process. The system translates events of each process into data capsules. A data capsule includes an application-independent representation of event data of an event and state information of the process originating the content of the data capsule. The system transfers the data messages into pools or repositories. Each process operates as a recognizing process, where the recognizing process recognizes in the pools data capsules comprising content that corresponds to an interactive function of the recognizing process and/or an identification of the recognizing process. The recognizing process retrieves recognized data capsules from the pools and executes processing appropriate to contents of the recognized data capsules.Type: GrantFiled: February 5, 2013Date of Patent: November 15, 2016Assignee: Oblong Industries, Inc.Inventors: Kwindla Hultman Kramer, John S. Underkoffler
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Patent number: 9495229Abstract: Described are methods, apparatus and computer programs for managing persistence within a data processing system such as a messaging system, database system or file system. The method for managing persistence includes a deferred evaluation (230,330,430) of at least one criterion associated with costs and/or benefits of saving to persistent storage, instead of persistence behavior being fully predefined. The evaluation may be performed when a disk write is about to be performed (240,340,440), or at various times during processing of a data update and at various points within a data processing network. In a messaging solution, the method for managing persistence includes a dynamic evaluation (230,330,430) of costs and/or benefits of saving to persistent storage, with the evaluation being performed at various points in the messaging network after the message has been created and sent by the originating entity.Type: GrantFiled: June 26, 2007Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventor: Stephen J. Todd
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Patent number: 9495230Abstract: A testing method used to check if an application executed in an operating system is crashed. The operating system is provided with a first value corresponding to the application, and the first value is stored in a storage unit. The testing method includes the following steps: send a message in a predetermined time period to the application to request a feedback from the application, and adjust the first value stored in the storage unit to another value by proceeding a predetermined algorithm; reboot the operating system if the said another value is equal to a second value; reset the said another value stored in the storage unit to the first value if the application gives the feedback.Type: GrantFiled: March 5, 2013Date of Patent: November 15, 2016Assignee: ACCTON TECHNOLOGY CORPORATIONInventor: Keng-Shao Liu
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Patent number: 9495231Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.Type: GrantFiled: March 17, 2016Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn D. Gilda, Patrick J. Meaney, Vesselina K. Papazova, John S. Dodson
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Patent number: 9495232Abstract: Host device platforms developed based on older ECC (Error Correcting Code) designs may not be equipped to handle the enhanced error correction capabilities in the newer NAND memories. Error correcting memory employing an error threshold representative of the additional capability of the ECC memory allows determining when a fetch has exceeded a safe level of errors to correct. ECC processing compares an error count to the threshold, and if the error count exceeds the threshold of maximum allowable errors, the ECC status module induces an error in the fetched data to alert the host.Type: GrantFiled: March 28, 2014Date of Patent: November 15, 2016Assignee: Intel IP CorporationInventor: Karsten Gjorup
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Patent number: 9495233Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing an error framework for a microprocessor and for a system having such a microprocessor. The error framework may alternatively be implemented by a hardware component, such as a peripheral device for integration into a system. In one embodiment, an error framework of a microprocessor or a hardware component includes an error detection unit to capture an error within the hardware component; a state detection unit to capture error context information when the error is detected within the hardware component; an error event definition unit to define a unique error event representing a combination of the error and the error context information; and a configuration unit to define an error event response based on the unique error event.Type: GrantFiled: December 21, 2011Date of Patent: November 15, 2016Assignee: Intel CorporationInventors: Cameron McNairy, David Heckman, Jenna Mayfield, Scott Hoyt
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Patent number: 9495234Abstract: Systems and methods for detecting anomalies within a multi-tenant environment are described. Diagnostic tests are performed on one or more components, such as host computing devices. The one or more components send resulting diagnostic information to an electronic device such as a monitoring component that processes the diagnostic information. The electronic device determines whether one or more properties, such as errors, are comprised within the one or more components. Based at least in part on properties that may be found, a correlation may be made between at least two properties.Type: GrantFiled: June 14, 2013Date of Patent: November 15, 2016Assignee: Amazon Technologies, Inc.Inventors: Richard Alan Hamman, Matthew James Eddey
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Patent number: 9495235Abstract: Each transfer route includes an FE I/F out of a plurality of FE I/Fs, a BE I/F out of a plurality of BE I/Fs, at least one memory out of one or more memories, and at least one processor out of one or more processors. I/O target data is transferred via a target transfer route including an FE I/F that has received an I/O request out of a plurality of transfer routes. A processor in the target transfer route generates routing information representing a physical device included in the target transfer route, and transmits a transfer indication including the routing information to at least one of the FE I/F and BE I/F in the target transfer route. In response to the transfer indication, at least one of the FE I/F and BE I/F in the target transfer route adds, to the I/O target data, a guarantee code.Type: GrantFiled: November 18, 2013Date of Patent: November 15, 2016Assignee: HITACHI, LTD.Inventors: Tomoaki Kurihara, Tsutomu Koga, Hideyuki Ihara
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Patent number: 9495236Abstract: Among other things, an augmented reality device that is configured and/or arranged to present particular device operational health information as a function of the distance between the augmented reality device and the particular device.Type: GrantFiled: April 7, 2015Date of Patent: November 15, 2016Assignee: Cubic CorporationInventor: Paul Monk
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Patent number: 9495237Abstract: Corruption of call stacks is detected by using guard words placed in the call stacks. A called function executing on a processor of a computing environment checks a guard word in a stack frame of a calling function. The checking determines whether the guard word has an expected value. Based on determining the guard word has an unexpected value, an indication of corruption of the stack frame is provided.Type: GrantFiled: January 6, 2016Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael K. Gschwind, Ronald I. McIntosh
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Patent number: 9495238Abstract: An approach is provided to provide a high availability (HA) cloud environment. In the approach, an active cloud environment is established in one cloud computing environment using a primary set of resources and a passive cloud environment is established in another cloud computing environment, with the passive cloud environment using fewer resources than are used by the active cloud environment. A workload is serviced by the active cloud environment. While servicing the workload, cloud commands are processed that alter the primary set of resources and the commands are stored in a queue. When a failure of the active cloud environment occurs, the workload is serviced by the passive cloud environment in the second cloud computing environment and the cloud commands stored in the queue are used to alter the resources used by the passive cloud environment.Type: GrantFiled: December 13, 2013Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Jason L. Anderson, Nimesh Bhatia, Gregory J. Boss, Animesh Singh
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Patent number: 9495239Abstract: A method for operating a programmable IC is disclosed. A set of circuits specified by a set of configuration data is operated in a set of programmable resources. In response to one of a set of status signals indicating an error, a value indicative of an error is stored in a respective one of a plurality of error status registers. The values stored in the plurality of error status registers are provided to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources. At least one error handling process is performed by the error handling circuit as a function of values stored in the plurality of error status registers.Type: GrantFiled: August 22, 2014Date of Patent: November 15, 2016Assignee: XILINX, INC.Inventors: Sagheer Ahmad, Bradley L. Taylor, Ahmad R. Ansari, Tomai Knopp
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Patent number: 9495240Abstract: A method begins by a dispersed storage (DS) processing module encrypting a plurality of data segments of the data using a plurality of encryption keys to produce a plurality of encrypted data segments and generating a plurality of deterministic values from the plurality of encrypted data segments. The method continues with the DS processing module establishing a data intermingling pattern and generating a plurality of masked keys by selecting one or more of the plurality of deterministic values in accordance with the data intermingling pattern and performing a masking function on the plurality of encryption keys and the selected one or more of the plurality of deterministic values. The method continues with the DS processing module appending the plurality of masked keys to the plurality of encrypted data segments to produce a plurality of secure data packages and outputting the plurality of secure data packages.Type: GrantFiled: September 29, 2014Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary W. Grube, Timothy W. Markison
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Patent number: 9495241Abstract: A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising two or more solid-state storage elements. The data segments may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The data arrangement may determine input/output performance characteristics. An optimal adaptive data storage configuration may be based on read and/or write patterns of storage clients, read time, stream time, and so on. Data of failed storage elements may be reconstructed by use of parity data and/or other ECC codewords stored within the array.Type: GrantFiled: March 4, 2013Date of Patent: November 15, 2016Assignee: LONGITUDE ENTERPRISE FLASH S.A.R.L.Inventors: David Flynn, John Strasser, Bill Inskeep
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Patent number: 9495242Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.Type: GrantFiled: July 30, 2014Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John K. DeBrosse, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Rona Yaari
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Patent number: 9495243Abstract: Embodiments of ECC encoders supporting multiple code rates and throughput speeds for data storage systems are disclosed. In one embodiment, an encoder can provide for flexible and scalable encoding, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) encoding is used. The encoder can be scaled in size based on, for example, the desired encoding throughput and/or computational cycle duration. The encoder can thus be used to support multiple code rates and throughput speeds. Accordingly, encoding speed and efficiency and system performance is improved.Type: GrantFiled: August 31, 2015Date of Patent: November 15, 2016Assignee: Western Digital Technologies, Inc.Inventors: Guangming Lu, Leader Ho
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Patent number: 9495244Abstract: An apparatus includes one or more error-correction decoders, a buffer, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one processor is generally enabled to send messages to the one or more error-correction decoders. The messages may contain datapath control information corresponding to data in the buffer to be decoded by the one or more error-correction decoders. The one or more error-correction decoders are generally enabled to decode the data read from the buffer according to the corresponding datapath control information.Type: GrantFiled: December 14, 2015Date of Patent: November 15, 2016Assignee: Seagate Technology LLCInventors: Earl T. Cohen, Yunxiang Wu, Alexander Hubris, Christopher Brewer
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Patent number: 9495245Abstract: A high speed USB memory controller includes a microprocessor, flash memory, memory buffers directly accessible to the microprocessor and flash memory, and a USB interface for writing data directly into the memory buffers. This allows devices with multiple flash die to operate at full bus speed.Type: GrantFiled: August 20, 2015Date of Patent: November 15, 2016Inventor: Charles I. Peddle
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Patent number: 9495246Abstract: The disclosure presents examples of a RAID storage system, method and computer program product where a stripe is logically partitioned into two or more sub-stripes and at least one RAID erasure code is applied to each sub-stripe independently of any other of the sub-stripe(s). Consequently, in some of these examples, a larger packet size may be used than if the stripe had not been partitioned. A larger packet size may in some cases allow for accelerated encoding and/or decoding.Type: GrantFiled: January 21, 2013Date of Patent: November 15, 2016Assignee: KAMINARIO TECHNOLOGIES LTD.Inventor: Eyal Gordon
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Patent number: 9495247Abstract: Embodiments relate to a computer system for storing data on a time multiplexed redundant array of independent tapes. An aspect includes a memory device that buffers data received by the computer system to be written to a set of tape data storage devices. The data is written to the set of tape data storage devices in blocks that form parity stripes across the set of tape data storage device. Aspects further includes a tape drive that writes data to one of the set of tape data storage devices at a time in a tape-sequential manner and a processor that computes a parity value for each of the parity stripes. The tape drive writes the parity values for each of the parity stripes to a last subset of tapes of the set of tape data storage devices.Type: GrantFiled: October 27, 2014Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mario Blaum, Veera W. Deenadhayalan, Steven R. Hetzler, Wayne C. Hineman, Robert M. Rees, Pin Zhou
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Patent number: 9495248Abstract: An SSD has a plurality of dies, with each die having a storage capacity. The storage capacity of each die is divided into a primary capacity and a spare capacity. A primary die has a maximum primary capacity, and a sum of the spare capacities of the remaining dies is greater than the maximum primary capacity. Data stored on the SSD is distributed among the primary capacities of the dies. When a failure of a first die is detected, data stored on the failed first die is migrated to the spare capacity of at least one of the remaining dies.Type: GrantFiled: August 20, 2014Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, David M. Daly, Gary A. Tressler
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Patent number: 9495249Abstract: Techniques described and suggested herein include systems and methods for precomputing regeneration information for data archives (“archives”) that have been processed and stored using redundancy coding techniques. For example, regeneration information, such as redundancy code-related matrices (such as inverted matrices based on, e.g., a generator matrix for the selected redundancy code) corresponding to subsets of the shards, is computed for each subset and, in some embodiments, stored for use in the event that one or more shards becomes unavailable, e.g., so as to more efficiently and/or quickly regenerate a replacement shard.Type: GrantFiled: March 31, 2015Date of Patent: November 15, 2016Assignee: Amazon Technolgies, Inc.Inventors: Paul David Franklin, Bryan James Donlan, Colin Laird Lazier, Claire Elizabeth Suver
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Patent number: 9495250Abstract: According to one embodiment, providing a bitstream to one or more programmable devices of a service unit card includes receiving the bitstream at a snooper of the service unit card. The snooper determines whether the bitstream is current. If the bitstream is current, the bitstream is loaded onto the programmable devices. If the bitstream is not current, the received bitstream is discarded, and a substitute bitstream is identified. The substitute bitstream is loaded onto the programmable devices.Type: GrantFiled: June 9, 2009Date of Patent: November 15, 2016Assignee: Fujitsu LimitedInventors: Roy C. McNeil, Jr., David W. Terwilliger
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Patent number: 9495251Abstract: An information management system according to certain aspects may determine whether snapshot operations will work prior to executing them. The system may check various factors or parameters relating to a snapshot storage policy to verify whether the storage policy will work at runtime without actually executing the policy. Some examples of factors can include: availability of primary storage devices for which a snapshot should be obtained, availability of secondary storage devices, license availability for snapshot software, user credentials for connecting to primary and/or second storage devices, available storage capacity, connectivity to storage devices, etc. The system may also check whether a particular system configuration is supported in connection with snapshot operations. The result of the determination can be provided in the form of a report summarizing any problems found with the snapshot storage policy.Type: GrantFiled: January 24, 2014Date of Patent: November 15, 2016Assignee: Commvault Systems, Inc.Inventors: Rajiv Kottomtharayil, Manoj Kumar Vijayan, Vimal Kumar Nallathambi, Unmil Vinay Tambe
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Patent number: 9495252Abstract: A continuous data backup using real time delta storage has been presented. A backup appliance receives a backup request from a backup agent running on a computing machine to backup data on the computing machine. The computing machine is communicatively coupled to the backup appliance. Then the backup appliance performs block-based real-time backup of the data on the computing machine. The backup appliance stores backup data of the computing machine in a computer-readable storage device in the backup appliance.Type: GrantFiled: March 14, 2014Date of Patent: November 15, 2016Assignee: DELL SOFTWARE INC.Inventors: Shunhui Zhu, Boris Yanovsky, William Dunn, Matthew W. Cotton
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Patent number: 9495253Abstract: The present disclosure relates generally to a method and system for creating, replicating, and providing access to virtual snapshots of a disk storage block of a disk storage system or subsystem. In one embodiment, the present disclosure relates to a virtual snapshot accessible to local users of a local data storage device. The virtual snapshot may direct local users to a snapshot stored on computer-readable storage medium at a remote data storage site, but give the appearance as if data of the corresponding snapshot is stored locally. The virtual snapshot is replaced by replication of the snapshot from the remote data storage site to the local data storage device. Each snapshot may relate to data of a logical data volume, the logical data volume being an abstraction of data blocks from one or more physical storage devices.Type: GrantFiled: March 13, 2015Date of Patent: November 15, 2016Assignee: Dell International L.L.C.Inventors: Michael H. Pittelko, Mark David Olson
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Patent number: 9495254Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.Type: GrantFiled: March 18, 2016Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Patrick J. Meaney, Glenn D. Gilda, Eric E. Retter, John S. Dodson, Gary A. Van Huben, Brad W. Michael, Stephen J. Powell
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Patent number: 9495255Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.Type: GrantFiled: August 7, 2014Date of Patent: November 15, 2016Assignee: Pure Storage, Inc.Inventors: John D. Davis, John Hayes, Zhangxi Tan, Hari Kannan, Nenad Miladinovic
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Patent number: 9495256Abstract: An apparatus includes a first switch circuit in an active mode and a second switch circuit in a standby mode. The apparatus receives high-priority packets and low-priority packets. Each switch circuit stores the high-priority packets and the low-priority packets into first and second buffers, respectively. The each switch circuit performs packet-readout processing reading out a packet from the first and second buffers where the packet-readout processing is performed on the first buffer on a priority basis. The apparatus controls the first switch circuit so that a back-pressure time for the high-priority packets becomes longer with increasing amount of data transmitted by the high-priority packets, when a low-priority packet outputted from the first switch circuit is determined to be a packet that has been received at a first time that is later than a second time at which another low-priority packet outputted from the second switch circuit has been received.Type: GrantFiled: August 27, 2012Date of Patent: November 15, 2016Assignee: FUJITSU LIMITEDInventors: Kazuto Nishimura, Hideo Abe, Satoshi Nemoto
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Patent number: 9495257Abstract: An aspect of the present invention provides a corresponding exclusive communication stack (e.g., TCP/IP stack) for each zone entity of a server system. In an embodiment, multiple server systems together implement a zone cluster containing such zone entities provided on corresponding server systems. As a result, when an application executing on a first zone entity of a first server is moved to a second zone entity of a zone cluster on a second server, the application continues to communicate using exclusive communication stack provided for the second zone entity. In view of the dedicated resources for network communication, applications executing in any zone entity of such a zone cluster, may have a desired level of predictable throughput performance and security for the communicated data packets.Type: GrantFiled: February 27, 2013Date of Patent: November 15, 2016Assignee: Oracle International CorporationInventors: Tirthankar Das, Thejaswini Singarajipura, Sambit Nayak, Honsing Cheng
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Patent number: 9495258Abstract: Techniques are described for dynamically generating a disaster recovery plan. In an embodiment, a set of topology metadata is determined for a first site on which a multi-tier application is deployed and a second site where the multi-tier application will be activated in the event of switchover/failover. The topology metadata may include metadata that identifies a set of targets associated with a plurality of tiers on the first site on which the multi-tier application is deployed and also on the second site where the multi-tier application would be activated in the event of disaster recovery operation like switchover or failover. Based, at least in part, on the topology metadata for the first site and second site, a disaster recovery plan is generated. The disaster recovery plan includes an ordered set of instructions for deactivating the multi-tier application at the first site and activating the multi-tier application at a second site.Type: GrantFiled: April 30, 2014Date of Patent: November 15, 2016Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Praveen Sampath, Rama Vijjapurapu, Mahesh Desai, Shekhar Borde
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Patent number: 9495259Abstract: Techniques are disclosed for orchestrating high availability (HA) failover for virtual machines (VMs) running on host systems of a host cluster, where the host cluster aggregates locally-attached storage resources of the host systems to provide an object store, and where persistent data for one or more of the VMs is stored as per-VM storage objects across the locally-attached storage resources comprising the object store. In one embodiment, a host system in the host cluster executing a HA module determines a VM to be restarted on an active host system in the host cluster. The host system further determines if the VM's persistent data is stored in the object store. If so, the host system adds the VM to a list of VMs to be immediately restarted. Otherwise, the host system checks whether the VM is accessible to the host system by querying a storage layer of the host system configured to manage the object store.Type: GrantFiled: June 27, 2014Date of Patent: November 15, 2016Assignee: VMware, Inc.Inventors: Marc Sevigny, Keith Farkas, Christos Karamanolis
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Patent number: 9495260Abstract: Apparatuses, systems and methods are disclosed for tolerating fault in a communications grid. Specifically, various techniques and systems are provided for detecting a fault or failure by a node in a network of computer nodes in a communications grid, adjusting the grid to avoid grid failure, and taking action based on the failure. In an example, a system may include receiving grid status information at a backup control node, the grid status information including a project status, storing the grid status information within the backup control node, receiving a failure communication including an indication that a primary control node has failed, designating the backup control node as a new primary control node, receiving updated grid status information based on the indication that the primary control node has failed, and transmitting a set of instructions based on the updated grid status information.Type: GrantFiled: June 23, 2015Date of Patent: November 15, 2016Assignee: SAS Institute Inc.Inventor: Richard Knight
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Patent number: 9495261Abstract: Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.Type: GrantFiled: August 12, 2014Date of Patent: November 15, 2016Assignee: QUALCOMM IncorporatedInventors: Jung Pill Kim, Dexter Tamio Chun, Deepti Vijayalakshmi Sriramagiri, Mosaddiq Saifuddin, Xiangyu Dong, Sungryul Kim, Yanru Li, Jungwon Suh
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Patent number: 9495262Abstract: Provided are a computer program product, system, and method for migrating high activity volumes in a mirror copy relationship to lower activity volume groups. A determination is made of usage rates of multiple volume groups, wherein each volume group is comprised of source volumes at a primary site whose data is copied to volumes at a secondary site. A first selected volume group and a second selected volume group are selected based on the determined usage rates of the volume groups. A first volume in the first selected volume group is migrated to a second volume in the second selected volume group. Updates to the first volume, received while migrating the first volume to the second volume, are copied to a mirror first volume mirroring the first volume at the secondary site.Type: GrantFiled: January 2, 2014Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dash D. Miller, David C. Reed, Max D. Smith, Herbert Yee
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Patent number: 9495263Abstract: A redundant external storage virtualization computer system. The redundant storage virtualization computer system includes a host entity for issuing an IO request, a redundant external SAS storage virtualization controller pair coupled to the host entity for performing an IO operation in response to the IO request issued by the host entity, and a plurality of physical storage devices for providing storage to the computer system. Each of the physical storage devices is coupled to the redundant storage virtualization controller pair through a SAS interconnect. The redundant storage virtualization controller pair includes a first and a second SAS storage virtualization controller both coupled to the host entity. In the redundant SAS storage virtualization controller pair, when the second storage virtualization controller is not on line, the first storage virtualization controller will take over the functionality originally performed by the second storage virtualization controller.Type: GrantFiled: October 11, 2005Date of Patent: November 15, 2016Assignee: Infortrend Technology, Inc.Inventors: Ching-Te Pang, Michael Gordon Schnapp, Shiann-Wen Sue, Cheng-Yu Lee
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Patent number: 9495264Abstract: Incremental checkpoint, for use in data replication, track the changes made to a file system after a point in time at which the incremental checkpoint is created. Data replication techniques using the incremental checkpoints may include taking a regular checkpoint of the file system and creating the first time full copy on remote node using the regular checkpoint. Changes made to the file system are then tracked in an incremental checkpoint that are stored on the remote node. The processes of taking the incremental checkpoint and storing the incremental checkpoint are iteratively performed. The first time fully copy and the incremental checkpoints may then be used for data replication, backup, continuous data protection (CDP), or the like.Type: GrantFiled: August 9, 2010Date of Patent: November 15, 2016Assignee: Veritas Technologies LLCInventors: Samir Desai, Niranjan Pendharkar
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Patent number: 9495265Abstract: Test executive system and method of use. The system includes a test executive engine, configured to execute at least one test executive sequence to test at least one unit under test (UUT), a process model that specifies one or more function sequences for pre-test or post-test functionality for the test executive sequences, and a plug-in framework, configured to selectively incorporate one or more process model plug-in instances in the process model. Each process model plug-in instance specifies at least one respective function sequence for pre-test or post-test functionality for the test executive sequences.Type: GrantFiled: August 13, 2013Date of Patent: November 15, 2016Assignee: National Instruments CorporationInventor: James A. Grey
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Patent number: 9495266Abstract: System and method of systems and methods of controlling an IC test equipment in response to verbal commands issued by test equipment users. A control apparatus according to the present disclosure includes a speech detection device operable to detect verbal commands and test control software configured to control operations of the test equipment. The control software is added with verbal command recognition capabilities. Program action commands defined in the test control software are associated with respective recognizable verbal commands. Upon a recognizable verbal command is detected, it is interpreted into the corresponding program action command which triggers the intended test program actions. The control apparatus may also have a gesture detection device, through which user gesture commands can be detected and interpreted into corresponding program actions commands.Type: GrantFiled: May 15, 2014Date of Patent: November 15, 2016Assignee: ADVANTEST CORPORATIONInventors: Keith Schaub, Hui Yu, Minh Diep