Abstract: A system and method for providing assisted manual testing of computer related devices. Test commands are routed from a user system through a proxy module to a device under test. The responses of the device are routed through the proxy module to a user system. A user interface is run on the user system that allows the user to view the responses of the device in a log with the issued test commands. The user interface includes annotation dialog boxes and fields, highlighting elements and flagging elements through which a user can annotate and create notes for the test log as the test is being run on the device. Through the proxy module, a third party can act as a user and view the test log and user created annotations and notes as the test is being run on the device. The test log, annotation and notes can also be stored by the proxy module so that a third party can view them at a later time.

Abstract: A method for error simulation in a data storage subsystem providing abstractions of one or more storage devices. The method includes dividing the data storage subsystem into two or more hierarchically organized subsystems, wherein the subsystems interact using IO Request Packets (IORPs), such that relatively higher level subsystems create and populate IORPs and pass them to relatively lower level subsystems for corresponding processing. The method further includes defining an IORP modifier configured to attach to matching IORPs based on one or more attributes of the IORP modifier and to modify at least one of the processing and one or more attributes of the IORP in order to simulate errors in the data storage subsystem.

Abstract: An approach is provided for migrating a live instance of a virtual machine from a source computer system to a target computer system. The approach operates by creating a consistent snap shot image of an operating system environment that is running the live instance of the virtual machine on the source computer system. A test virtual machine container is created based on an actual virtual machine container that corresponds to the live instance of the virtual machine. Based on the snap shot image of the operating system environment, a test virtual machine is created in the test virtual machine container. The generated test virtual machine is tested with a migration of the live instance of the virtual machine being performed in response to a successful test of the test virtual machine. The migration is aborted in response to an unsuccessful test of the test virtual machine.

Abstract: A graphical user interface for monitoring a status of objects included in a virtualized computing environment including a plurality of host computers, each having one or more virtual machines running therein, includes a first second and a second section. The first section displays a first graph depicting utilization during a first period of time of a first computing resource associated with a first object included in the virtualized computing environment. The second section displays a listing of one or more objects included in the virtualized computing environment that are related to the first object, where, in response to receiving a selection of a second object from the listing of one or more objects, the first section displays a second graph depicting utilization during the first period of time of the first computing resource associated with the second object.

Abstract: A statistical power indication monitor including a random pattern generator that generates random sample assertions of a sample signal, a total counter that counts a total number of the random sample assertions within a sample time interval, detect logic that provides a detection signal for each power indication signal that is asserted coincident with the sample signal, and counter logic that counts a number of assertions of each detection signal during the sample time interval. The assertion count of each power indication signal divided by the total count provides a statistical indication of power consumption of a corresponding system. A user may use the statistical monitoring information to adjust system or application operation. The random pattern generator may be a pseudo-random pattern generator including a linear feedback shift register and may have programmable seed and sample rate.

Abstract: A system for generating a power consumption model of at least one server includes one or more computers configured to obtain n time series telemetry signals indicative of operating parameters of the at least one server, obtain a time series power signal indicative of power consumed by the at least one server, and correlate each of the n time series telemetry signals with the time series power signal. The one or more computers are further configured to select a set of the n time series telemetry signals having an overall correlation with the time series power signal greater than a predetermined threshold, and generate a power consumption model of the at least one server based on at least the set of the n time series telemetry signals.

Abstract: Systems and methods for displaying blade chassis data are provided. One system includes a memory for storing computer code comprising a blade chassis information module and a processor capable of being in communication with a blade chassis. The processor, when executing the computer code comprising the blade chassis information module, is configured to receive the blade chassis data, create a user interface for the blade chassis data, and display the blade chassis data on the user interface. One method includes receiving blade chassis data, creating a user interface for the blade chassis data, and displaying the blade chassis data on the user interface. Also provided are physical computer storage mediums including a computer program product for performing the above method.

Abstract: A computer-implemented method includes selecting a runtime for executing a program. The runtime includes a first combination of feature implementations, where each feature implementation implements a feature of an application programming interface (API). Execution of the program is monitored, and the execution uses the runtime. Monitor data is generated based on the monitoring. A second combination of feature implementations are selected, by a computer processor, where the selection is based at least in part on the monitor data. The runtime is modified by activating the second combination of feature implementations to replace the first combination of feature implementations.

Abstract: Techniques for segregating one or more logs of at least one multitasking user to derive at least one behavioral pattern of the at least one multitasking user are provided. The techniques include obtaining at least one of at least one action log, configuration information, domain knowledge, at least one task history and open task repository information, correlating the at least one of at least one action log, configuration information, domain knowledge, at least one task history and open task repository information to determine a task associated with each of one or more actions and segregate the one or more logs based on the one or more actions, and using the one or more logs that have been segregated to derive at least one behavioral pattern of the at least one multitasking user. Techniques are also provided for deriving intelligence from at least one activity log of at least one multitasking user to provide information to the at least one user.

Abstract: In an embodiment, a model is analyzed and a metric is generated based on the analysis. An indication of the metric is displayed on a Human Machine Interface (HMI) associated with a model. The analysis may involve executing one or more tests of one or more functions in the model. The metric may be generated based on the executing. The one or more functions may be associated with a widget implemented by the HMI and the indication of the metric may be displayed on the widget. The widget may be coded to indicate the metric.

Abstract: An approach for dynamic test topology visualization is provided. The approach retrieves test data from one or more databases. The approach retrieves test data from an application under test. The approach creates a visual diagram, wherein the visual diagram includes one or more topological elements, one or more topological relationships between the one or more topological elements, the test data, and a screen snapshot of an application under test. The approach overlays the visual diagram with user interaction information. The approach associates the visual diagram to the test execution performed on the application under test.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to code instrumentation and provide a method, system and computer program product for dynamic discovery of data segments within instrumented code. In an embodiment of the invention, a method for dynamic data segment discovery for instrumented code can be provided. The method can include statically instrumenting program code, recording potential data segments during the instrumentation of the program code, executing the instrumented program code, determining whether or not each of the recorded potential data segments can be resolved, and noting resolved ones of the recorded potential data segments.

Abstract: Efficient statistical profiling in embedded computing devices, such as video games, uses a hybrid random distribution of sampling points for more accurate reconstruction of executing code. Transmission of only function start addresses and corresponding representation of the call graph data reduces the memory overhead and increases communication speed.

Abstract: An operation verifying apparatus of a first embodiment acquires a log indicating the content of a sequence of operations performed on a predetermined device, identifies corresponding functions from the log, and automatically generates a program based on the identified functions. Input data, which is to serve as an argument of each of these functions, is set. Execution sets as well as test scenarios are each structured by combining a program and input data. Then each execution set is continuously executed. As a result, an operation test using a test program is executed.

Abstract: Systems, machine readable media, and methods are provided. An example method can include populating cells of a matrix with a plurality of user interface (UI) configuration parameters to determine a total number of testable UI configurations, reducing a number of the cells of the matrix by combining at least two UI configuration parameters to determine a reduced number of UI configurations to test, executing a number of predetermined tests, where test results depend on input of the reduced number of UI configurations, and determining the UI coverage based upon the test results.

Abstract: Testing a dashboard framework includes creating a model that captures the states of a GUI application and validates the states of the application by comparing it with benchmarks. The testing can include user interaction between the captured states of the GUI application. The ability to provide testing based upon recorded states of a web application can enable the test system to adapt to changes to the GUI software during product development or modification. Testing a dashboard framework is more efficient and flexible testing methods for GUI software.

Abstract: A system and method for managing the migration of software components among test servers that form a distributed software test environment to ensure that the software components in each of the test servers represent a production environment except for software components being tested. The system further ensures that component changes rolled out into production are not overridden when multiple update requests are made for the same component.

Abstract: A method for transferring data utilizing direct memory access. The method includes a computer processor establishing a networking connection, using a proxy, between at least a first computing entity and a second computing entity. The method further includes determining a shared memory space for the established networking connection between at least the first computing entity and the second computing entity. The method further includes allocating the shared memory space from heap memory. The method further includes transmitting data over the established networking connection between at least the first computing entity and the second computing entity utilizing a direct memory access protocol and the allocated shared memory space.

Abstract: The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the SRAM, a first input coupled to the ROM and a second input coupled to the OTP NVM. The selection logic is operable to receive input indicating whether SRAM is to be loaded from the ROM or the OTP NVM, and operable to load either the first timing device configuration from the ROM or the second timing device configuration from the OTP NVM based on the input.

Abstract: The invention relates to a method and arrangement for processing transactions in a flash type memory device, wherein the transaction is a data update and/or changing operation consisting of one or more suboperations, all of which must be successfully executed in order to regard the discussed transaction as having been successfully completed in its entirety. In the solution according to the invention, memory-block specific status information (131) of a memory block present in a flash type memory device is utilized not only for managing payload data (141) present in the memory block but also for the management of an entire transaction. Consequently, there is no need for a separate status bookkeeping of transactions, thus reducing the number of reading and writing operations required in transactions.

Abstract: Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition.

Abstract: A method for using a variable-size flash translation layer is disclosed. Step (A) receives a read request to read data corresponding to a logical block address from a nonvolatile memory. Step (B) reads a particular entry of a map to obtain (i) a physical address of a particular page of the nonvolatile memory, (ii) an offset in the particular page to compressed data previously stored and (iii) a length of the compressed data. The particular entry is associated with the logical block address. Step (C) converts the offset and the length to (i) an address of a given read unit in the particular page and (ii) a number of the read units to be read. Step (D) reads from the particular page at most the number of the read units starting from the given read unit. An offset and length granularity are finer than one read unit.

Abstract: Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition.

Abstract: A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.

Abstract: A method of interleaving a memory by mapping address bits of the memory to a number N of memory channels iteratively in successive rounds, wherein in each round except the last round: selecting a unique subset of address bits, determining a maximum number (L) of unique combinations possible based on the selected subset of address bits, mapping combinations to the N memory channels a maximum number of times (F) possible where each of the N memory channels gets mapped to an equal number of combinations, and if and when a number of combinations remain (K, which is less than N) that cannot be mapped, one to each of the N memory channels, entering a next round. In the last round, mapping remaining most significant address bits, not used in the subsets in prior rounds, to each of the N memory channels.

Abstract: A computer-executable method, system, and computer program product of managing a hierarchical data storage system, wherein the data storage system includes a first level of one or more hosts, a second level of one or more storage appliances, and a data storage array, the computer-executable method, system, and computer program product comprising receiving an I/O request from a first host of the one or more hosts, wherein the I/O request relates to a portion of data on the data storage array, analyzing the I/O request to determine a status of the portion of data on the data storage system, based on the determination, providing an update to a second host of the one or more hosts based on the I/O request, wherein the portion of data is cached on the second host of the one or more hosts, and processing I/O request by sending I/O request to data storage array.

Abstract: A computer implemented method, system, and computer program product for enabling consistency between zones comprising creating a lease agreement between a first zone and at least a second zone; wherein the lease indicates that the first zone is the owner of an object; wherein the lease agreement dictates that a notification is to be sent before a cached object in the first zone is updated if the lease is still valid; wherein the lease indicates the first zone is to send a heartbeat to the second zone within the predetermined period of time if the object has not been changed and the lease is still valid; and setting up heartbeats from the first zone to at least a second zone within a predetermined amount of time; wherein the heartbeat indicates that the lease is still valid and the object has not been changed.

Abstract: Various embodiments for improving hash index key lookup caching performance in a computing environment are provided. In one embodiment, for a cached fingerprint map having a plurality of entries corresponding to a plurality of data fingerprints, reference count information is used to determine a length of time to retain the plurality of entries in cache. Those of the plurality of entries having a higher reference counts are retained longer than those having lower reference counts.

Abstract: A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m3. A density of the processor chips may be greater than 1,000 chips per cubic meter.

Abstract: Handling memory pressure in an in-database sharded queue is described. Messages from a plurality of enqueuers are stored in a plurality of shards of a sharded queue. Messages from a first enqueuer are stored in a first shard. A queue table corresponding to the sharded queue is maintained. In volatile memory, a plurality of message caches is maintained, each message cache corresponding to a shard of the plurality of shards. Memory pressure is detected based on memory usage of the volatile memory. To store a specific message from the enqueuer, the specific message is stored in rows of the queue table that are assigned to the first shard. When memory pressure is not detected, the specific message is stored in a first message cache corresponding to the first shard. Subscribers of the sharded queue are caused to dequeue messages from the plurality of shards.

Abstract: A technique for handling an unaligned load operation includes detecting a cache line crossing load operation that is associated with a first cache line and a second cache line. In response to an cache including the first cache line but not including the second cache line, the second cache line is reloaded into the cache in a same set as the first cache line. In response to reloading the second cache line in the cache, a cache line crossing link indicator associated with the first cache line is asserted to indicate that both the first and second cache lines include portions of a desired data element.

Abstract: A technique for handling an unaligned load operation includes detecting a cache line crossing load operation that is associated with a first cache line and a second cache line. In response to an cache including the first cache line but not including the second cache line, the second cache line is reloaded into the cache in a same set as the first cache line. In response to reloading the second cache line in the cache, a cache line crossing link indicator associated with the first cache line is asserted to indicate that both the first and second cache lines include portions of a desired data element.

Abstract: Part of a plurality of ways are selected from among the ways according to a value of select data created based on tag address information which is part of address information, and cache tags are read. Further, when performing cache fill, the cache memory performs the cache fill on a cache entry selected from part of the ways according to the value of the select data. For select data used for selecting a way, e.g. parity data in connection with tag address information is used. A way to read a cache tag from is selected based on a value of parity data and further, the way of a cache entry to perform cache fill on is selected.

Abstract: A computer-implemented method includes generating a vector that is a random number. Two or more residue functions are applied to the vector to produce a state signal including a different number of states. A set status of a set-associative storage container in a computer system is determined. The set status identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.

Abstract: In one embodiment, a computing system includes a cache having one or more memories, a cache journal operable to store data associated with one or more portions of the cache, and a configuration manager operable to access the cache and the cache journal. The configuration manager is operable to determine whether the cache journal includes data associated with a first portion of the cache, and to create, in the cache journal, data associated with the first portion of the cache if the cache journal does not yet comprise data associated with the first portion of the cache. The configuration manager is also operable to determine whether the first portion of the cache is valid for use, and to communicate with a memory manager associated with the first portion of the cache regarding whether the first portion of the cache is valid for use.

Abstract: A processing sub-system is configured to execute a program using a set of virtual memory addresses to reference memory locations for storage of variables of the program. A programmable logic sub-system is configured to implement a set of I/O circuits specified in a configuration data stream, each of the I/O circuits having a respective ID and configured to access one of the variables. A memory management circuit is configured to map the virtual memory addresses to physical memory addresses of a memory and map IDs to the physical address used to store the corresponding variables. A TLB is configured to receive a memory access request, from the I/O circuits, each request indicating an ID and provide, to the memory, a memory access request indicating the physical memory address that is mapped to the ID.

Abstract: Address remapping technologies are described. A method can include receiving, at a paging device of a system memory, a first physical address of an input/output (IO) device from a sub-page translator, where a sub-page location indicator may be associated with the first physical address. The method can further include identifying a virtual address in a sub-page translation table based on the physical address when the sub-page location indicator may be set to a sub-page lookup mode. The method can further include determining when to look-up the physical address in a sub-page translation table based on the sub-page location indicator. The method can further include communicating, to a virtual machine, the virtual address.

Abstract: An address compression method, an address decompression method, a compressor, and a decompressor are disclosed, wherein the address compression method includes after a compressor receives multiple operation request messages that are sent by a first processor, determining, according to an address feature formed by address information carried in all operation request messages that have a same stream number, a compression algorithm corresponding to the operation request messages that have a same stream number; and then compressing, according to the determined compression algorithm, addresses carried in the operation request messages that have a same stream number. The present invention is applicable to the computer field.

Abstract: A method, a processing system, and a non-transitory computer-readable medium configured with instructions to carry out a method of determining access permission for or during dereferencing a memory address in an allocated portion of memory of a processing system. The method comprises: providing a pointer that has a tag field and a control-structure-pointer field; and entering content in the control-structure-pointer field to point to a control structure for the allocated portion of memory. The control structure's location or content indicates the portion of memory. The method assigning a tag value for the portion in the tag fields of the pointer and of the control structure. Determining access permission including ascertaining whether the contents of the tag fields of the pointer and of the control structure match.

Abstract: According to some embodiments, a method for controlling a processor state with transient cache memory is described. The method may include identifying, via a processor, a memory section having a memory address, retrieving, via the processor, memory control information, and controlling the processor state by allowing a memory access to the transient cache memory based on the memory control information.

Abstract: A method for operating a portable electronic device includes receiving an identifier associated with an accessory connected to the portable electronic device. The portable electronic device then determines a set of actions to be performed for that accessory based on the received identifier. The portable electronic device then performs the determined actions.

Abstract: A method is disclosed that includes writing data to predetermined physical addresses of a system memory, the data including metadata that identifies a processing type; configuring a processor module to include the predetermined physical addresses, the processor module being physically connected to the memory bus by a memory module connection; and processing the write data according to the processing type with an offload processor mounted on the processor module.

Abstract: A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface. The replication device is configured to transmit two or more copies of substantially replicated control information to a device control interface. A data interface is configured to provide differential, point-to-point communication of data with the device controller interface.

Abstract: A method of operation of a computing system includes: reconfigurable hardware devices having first application fragment and second application fragment; configuring virtual bus module having virtual bus for electrically coupling the reconfigurable hardware devices; allocating a physical port in the virtual bus, based on availability, for coupling the first application fragment and the second application fragment through the virtual bus; implementing an application through the virtual bus including transferring application data between the first application fragment and the second application fragment; activating a signal buffer interface by the virtual bus module: activating a pin buffer dispatch module for storing the application data from application input buffer, and activating memory request port by roll-back table module, storing the application data, in response to the pin buffer dispatch module; and alerting a roll-back detector including dismissing the application data exceeds a roll-back threshold or

Abstract: A method includes for each processed interrupt: determining whether the interrupt is a user mode interrupt; upon determining that the interrupt is a user mode interrupt, determining a stack location to insert an entry corresponding to the user mode interrupt, the stack location being calculated by adjusting a current stack pointer by a red zone offset; and inserting the entry corresponding to the user mode interrupt into the stack at the stack location.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.

Abstract: A disclosed example apparatus includes a termination panel, a shared bus on the termination panel, and a plurality of bases on the termination panel along the shared bus. Each of the bases is to removably receive modules that are to communicate with field devices. Each of the bases includes first and second physical interfaces. The first physical interface is to be communicatively coupled to different types of the field devices and to exchange communications with one or more of the field devices via a plurality of different communication protocols. The second physical interface is to communicatively couple the removably receivable modules to the shared bus to communicate with a controller via the shared bus.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.

Abstract: An information processing device may include a master device and at least one slave device, which may be connected each other by using two types of signal lines comprising a serial clock line and a serial data line. A datum may be transmitted between the master device and the slave device according to a predetermined communication method by using the two types of signal lines. If either the master device resets the slave device, or a power supply to the master device and the slave device is turned on, the slave device may commence a starting operation. A notification of a starting condition may be provided to the master device by way of at least one of the serial clock line and the serial data line.

Abstract: Embodiments are provided for an asynchronous processor with a Hierarchical Token System. The asynchronous processor includes a set of primary processing units configured to gate and pass a set of tokens in a predefined order of a primary token system. The asynchronous processor further includes a set of secondary units configured to gate and pass a second set of tokens in a second predefined order of a secondary token system. The set of tokens of the primary token system includes a token consumed in the set of primary processing units and designated for triggering the secondary token system in the set of secondary units.