Patents Issued in December 13, 2016
-
Patent number: 9519533Abstract: Methods and devices for tracking data flows in a computing device include monitoring memory in a hardware component of the computing device to identify a read operation that reads information from a tainted memory address, using heuristics to identify a first, second, and third number of operations performed after the identified read operation, marking memory addresses of write operations performed after first number of operations and before the second number of operations as tainted, and marking memory addresses of write operations performed after the third number of operations and before the second number of operations as untainted.Type: GrantFiled: January 28, 2015Date of Patent: December 13, 2016Assignee: QUALCOMM IncorporatedInventors: Man Ki Yoon, Mastooreh Salajegheh, Mihai Christodorescu, Yin Chen, Vinay Sridhara, Rajarshi Gupta
-
Patent number: 9519534Abstract: An information processing apparatus includes a processor, a first memory, and a second memory, wherein the second memory includes a first data storage region having a first data capacity and a second data storage region having a second data capacity smaller than the first data capacity, and the processor is configured to, in a case of executing first processing, select the first data storage region as a storage region for data to be written into the second memory by the first processing, and select the second data storage region as a storage region for data to be written into the second memory by second processing, and in a case of not executing the first processing, select the first data storage region as a storage region for data to be written from the first memory to the second memory by the second processing.Type: GrantFiled: September 11, 2014Date of Patent: December 13, 2016Assignee: FUJITSU LIMITEDInventor: Masatoshi Sugino
-
Patent number: 9519535Abstract: An approach for two stage log normalization is provided. The approach retrieves a message format and a plurality of parameters from one or more log files. The approach determines a classification for one or more first sequence files, wherein the one or more first sequence files includes the message format from the one or more log files. The approach determines a classification of error for the one or more first sequence files. The approach determines whether there is a high confidence in the classification of error for the one or more first sequence files. The approach determines whether there is an improvement in confidence in the classification of error from one or more second sequence files, wherein the one or more second sequence files includes the message format and the plurality of parameters from the one or more log files.Type: GrantFiled: July 17, 2015Date of Patent: December 13, 2016Assignee: International Business Machines CorporationInventors: Phillip A. J. Cooper, Jevon J. C. Hill, Fiona L. Lam, Kalvinder P. Singh
-
Patent number: 9519536Abstract: Systems and methods for generating a visual indicator based on receiving a report of a transaction processing error, the error comprising an informality in a software instruction code executed during a first attempt to process a transaction. The systems may be configured to determine a preconfigured time period for correcting the software instruction code causing the transaction processing error and compare it to the actual time it took to correct the software instruction code to determine whether the processing error was corrected within the preconfigured time period. The system and method may then generate and communicate a visual indicator based on determining whether the error was corrected within preconfigured time period.Type: GrantFiled: January 1, 2015Date of Patent: December 13, 2016Assignee: Bank of America CorporationInventor: Piyush Arora
-
Patent number: 9519537Abstract: The present disclosure relates to a log data processing apparatus and a method for controlling the same. A log data processing apparatus according to an embodiment includes a communication unit configured to receive information on log data corresponding to an application from a device for generating the log data, a control unit configured to generate a log message on a basis of the log data information, and a storage unit configured to store the log message and generation history information of the log message generated, wherein the log data information includes a log message parameter, message code information, and identifier information of the application.Type: GrantFiled: April 8, 2015Date of Patent: December 13, 2016Assignee: LSIS CO., LTD.Inventors: Tae Ho Kim, Yong Ik Lee, Jong Ho Park
-
Patent number: 9519538Abstract: An instruction processing pipeline having error detection and error recovery circuitry associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need be flushed from the instruction pipeline. The instruction pipeline may additionally/alternatively be provided with more than one main storage element associated with each signal value with these main storage elements used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element to properly capture the signal value corresponding to the following program instruction.Type: GrantFiled: June 6, 2011Date of Patent: December 13, 2016Assignee: ARM LimitedInventors: Emre Özer, Shidhartha Das, David Michael Bull
-
Patent number: 9519539Abstract: A method for outputting data error status of a memory device includes generating data status indication codes indicating error status of data chunks transmitted by a memory controller, and combining the data status indication codes with corresponding data chunks to generate an output signal, and outputting the output signal to a data bus pin.Type: GrantFiled: February 3, 2015Date of Patent: December 13, 2016Assignee: Macronix International Co., Ltd.Inventors: Kuen Long Chang, Ken Hui Chen, Su Chueh Lo, Chia-Feng Cheng
-
Patent number: 9519540Abstract: An apparatus, system, and method are disclosed for satisfying storage requests while destaging cached data. A monitor module samples a destage rate for a nonvolatile solid-state cache, a total cache write rate for the cache, and a dirtied data rate. The dirtied data rate comprises a rate at which write operations increase an amount of dirty data in the cache. A target module determines a target cache write rate for the cache based on the destage rate, the total cache write rate, and the dirtied data rate to target a destage write ratio. The destage write ratio comprises a predetermined ratio between the dirtied data rate and the destage rate. A rate enforcement module enforces the target cache write rate such that the total cache write rate satisfies the target cache write rate.Type: GrantFiled: January 24, 2012Date of Patent: December 13, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: David Atkisson, Jonathan Ludwig
-
Patent number: 9519541Abstract: Data checking and correction for a volatile memory of a data storage device, the data storage device further including a non-volatile memory and a controller. The controller operates the non-volatile memory in accordance with requests issued from a host. The controller uses the volatile memory for temporary storage of temporary data required for operations of the non-volatile memory. The controller generates error checking and correction content for the temporary data and writes the temporary data and the error checking and correction content into the volatile memory in at least one burst length for temporary storage of the temporary data. In this manner, it is not necessary to manufacture any additional pin on the volatile memory for data checking and correction.Type: GrantFiled: May 7, 2014Date of Patent: December 13, 2016Assignee: VIA TECHNOLOGIES, INC.Inventor: Lei Feng
-
Patent number: 9519542Abstract: A storage control apparatus includes a controller to, when more storage devices, among a plurality of storage devices across which a plurality of information areas storing information representing redundant data and one or more spare areas are distributed, than the number of the spare areas fail, perform a rebuild process of information stored in a plurality of information areas of a failed first storage device included in the plurality of combinations of the plurality of information areas and the one or more spare areas, the rebuild process including restoring information corresponding to one information area of the failed first storage device included in one combination among the plurality of combinations, and determining a write destination storage device to which the restored information is to be written in accordance with the number of times information is read from a non-failed second storage device.Type: GrantFiled: July 7, 2015Date of Patent: December 13, 2016Assignee: FUJITSU LIMITEDInventors: Guangyu Zhou, Takeshi Watanabe, Kazuhiko Ikeuchi, Chikashi Maeda, Yukari Tsuchiyama, Kazuhiro Urata
-
Patent number: 9519543Abstract: A method and an apparatus search an image using a feature point. The image search method extracts at least one feature point from an image and describes the extracted at least one feature point in stages, thereby generating a hierarchical feature point descriptor. In addition, the method may search for information matching the feature point descriptor from a local database (DB) included in a terminal or a remote DB included in a server.Type: GrantFiled: February 23, 2015Date of Patent: December 13, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Wook Kim, Seon Min Rhee, Yong Beom Lee
-
Patent number: 9519544Abstract: A memory module includes an emergency power supply block, a volatile memory, a nonvolatile memory, and a control block configured to control data of the volatile memory to be backed up in the nonvolatile memory, by using a power supplied from the emergency power supply block, upon a power failure, and control the data of the volatile memory to be recovered, by using data backed up in the nonvolatile memory, upon a power recovery, wherein the control block controls the data of the volatile memory not to be backed up while controlling the data of the volatile memory to be recovered, even upon the power failure.Type: GrantFiled: September 17, 2014Date of Patent: December 13, 2016Assignee: SK Hynix Inc.Inventor: Choung-Ki Song
-
Patent number: 9519545Abstract: Techniques, systems, and devices are disclosed for remediating a failed drive in a set of drives, such as a RAID system, without having to physically replace the failed drive. After receiving a signal of an error indicating a specific physical portion on a storage drive in the set of storage drives has caused the drive to fail, the system can unmount the drive from the filesystem while other drives continue to operate. Next, the system can identify one or more files in the filesystem that have associations with the specific physical portion on the failed drive. Next, the system can remount the drive onto the filesystem and subsequently delete the identified files from the filesystem. The system can then perform a direct I/O write to the specific physical portion on the failed drive to force reallocation of the specific physical portion to a different area on the failed drive. The system can also power-cycle the drive before this remediation, e.g., to determine if this remediation can be avoided.Type: GrantFiled: November 11, 2014Date of Patent: December 13, 2016Assignee: Facebook, Inc.Inventor: Mateusz Marek Niewczas
-
Patent number: 9519546Abstract: A method for information handling systems includes receiving a storage operation to be applied to a cache block in a location in a distributed storage system. The location is defined by a logical block address (LBA). The method further includes swapping a first portion of the LBA with a second portion of the LBA, resulting in a modified LBA, and performing the storage operation with the modified LBA. The first portion and the second portion are both x bits wide.Type: GrantFiled: March 17, 2014Date of Patent: December 13, 2016Assignee: Dell Products L.P.Inventors: Scott Peterson, Phillip Krueger
-
Patent number: 9519547Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses including, for supporting transactional message handling in an on-demand service environment including, for example: enqueuing a message specifying a transaction to be processed via a host organization; inserting a row into a database of the host organization associating the message with a status of pending, wherein the row is autocommitted to the database upon insertion; updating the status for the row to ready if a commit operation for the transaction is initiated; requesting a lock on the row; and performing final processing for the transaction based on the status for the message and based further on whether the lock is obtained for the row. Final processing may include, for example, a transaction roll back, a transaction commit, a transaction requeue, a termination of transaction processing, or an orphaned transaction clean up.Type: GrantFiled: September 16, 2014Date of Patent: December 13, 2016Assignee: salesforce.com, inc.Inventor: Vijayanth Devadhar
-
Patent number: 9519548Abstract: One or more unused bits of a virtual address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2M)-th of a memory page.Type: GrantFiled: January 2, 2015Date of Patent: December 13, 2016Assignee: VMware, Inc.Inventors: Benjamin C. Serebrin, Bhavesh Mehta
-
Patent number: 9519549Abstract: Control of the discard of data from cache during backup of the data. In a computer-implemented system comprising primary data storage; cache; backup data storage; and at least one processor, the processor is configured to identify data stored in the primary data storage for backup to the backup data storage, where the identified data is placed in the cache in the form of portions of the data, and where the portions of data are to be backed up from the cache to the backup storage. Upon backup of each portion of the identified data from the cache to the backup storage, the processor marks the backed up portion of the identified data for discard from the cache. Thus, the backed up data is discarded from the cache right away, lessening cache pollution.Type: GrantFiled: January 11, 2012Date of Patent: December 13, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence Carter Blount, Rahul Fiske, Carl Evan Jones, Subhojit Roy
-
Patent number: 9519550Abstract: In one aspect, a method includes generating a secure connection with a replication system using credentials, receiving a user-initiated command to control the replication system, generating a connection object, determining if the connection to the replication system has been initiated, sending the command to the replication system if the connection is initiated, obtaining input from a character stream to process and processing data for use by a backup system.Type: GrantFiled: September 29, 2014Date of Patent: December 13, 2016Assignee: EMC CORPORATIONInventor: Angel Luis Caban
-
Patent number: 9519551Abstract: The recovery of one or more transactions in a computing system in which one or more persistent systems are coupled via a bus to one or more processors. As an example, the persistent system may serve as at least part of the main memory of the computing system. The transaction might implement multi-versioning in which a record is not updated in place. Rather, each record is represented as a sequence of one or more record versions, each version having a valid interval during which the record version is considered to properly represent the record.Type: GrantFiled: May 10, 2013Date of Patent: December 13, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Per-Ake Larson, Robert Patrick Fitzgerald, Cristian Diaconu, Michael James Zwilling
-
Patent number: 9519552Abstract: An image forming apparatus comprises a first and a second HDDs (Hard Disk Drives), a RAID (Redundant Arrays of Inexpensive Disks) controller to execute rebuilding processes in which data stored in the first HDD is copied to the second HDD restored, and a CPU (Central Processing Unit). When there arises the necessity for accessing from the CPU to at least of the first and the second HDDs, and the priority of data which is the object for access by the CPU is higher than the priority of data which is being processed under the rebuilding processes, the image forming apparatus stops the rebuilding processes. The image forming apparatus restarts the rebuilding processes, when the access from the CPU is finished.Type: GrantFiled: January 25, 2016Date of Patent: December 13, 2016Assignee: KONICA MINOLTA, INC.Inventor: Takehisa Nakao
-
Patent number: 9519553Abstract: A failure resistant distributed computing system includes primary and secondary datacenters each comprising a plurality of computerized servers. A control center selects orchestrations from a predefined list and transmits the orchestrations to the datacenters. Transmitted orchestrations include less than all machine-readable actions necessary to execute the orchestrations. The datacenters execute each received orchestration by referencing a full set of actions corresponding to the received orchestration as previously stored or programmed into the computerized server and executing the referenced full set of actions. At least one of the orchestrations comprises a failover operation from the primary datacenter to the secondary datacenter.Type: GrantFiled: December 31, 2015Date of Patent: December 13, 2016Assignee: ServiceNow, Inc.Inventors: Sridhar Chandrashekar, Swapnesh Patel, Viral Shah, Anurag Garg, Anjali Chablani
-
Patent number: 9519554Abstract: In a storage system which supports a redundant disk configuration, while securing fault tolerance, a longer drive access time as well as a drop in I/O throughput are prevented when a redundant data update, generated due to a data update, is mirrored in the drive. A controller for controlling data I/O to and from the drive updates first redundant data and block data of a corresponding data stripe in the disk drive in correspondence with an update of block data of the logical volume, and the controller updates second redundant data on the basis of a predetermined number of block data which belong to the same data stripe as the updated block data with different timing from the update of the block data.Type: GrantFiled: April 4, 2014Date of Patent: December 13, 2016Assignee: Hitachi, Ltd.Inventor: Hiroaki Akutsu
-
Patent number: 9519555Abstract: Embodiments of the present invention relate to synchronously replicating data in a distributed computing environment. To achieve synchronous replication both an eventual consistency approach and a strong consistency approach are contemplated. Received data may be written to a log of a primary data store for eventual committal. The data may then be annotated with a record, such as a unique identifier, which facilitates the replay of the data at a secondary data store. Upon receiving an acknowledgment that the secondary data store has written the data to a log, the primary data store may commit the data and communicate an acknowledgment of success back to the client. In a strong consistency approach, the primary data store may wait to send an acknowledgement of success to the client until it receives an acknowledgment that the secondary has not only written, but also committed, the data.Type: GrantFiled: May 23, 2011Date of Patent: December 13, 2016Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Bradley Gene Calder, Niranjan Nilakantan, Shashwat Srivastav, Jiesheng Wu, Abdul Rafay Abbasi, Shane Mainali, Padmanabha Chakravarthy Uddaraju
-
Patent number: 9519556Abstract: An information handling system includes a method for detecting a predictive failure indication for a predictive failure indicated physical disk of a disk group, determining an amount of used storage capacity of a lowest capacity physical disk of the disk group, and comparing a replacement physical disk storage capacity of a replacement physical disk to the used storage capacity. When the replacement physical disk capacity is greater than or equal to the used storage capacity even if the replacement physical disk capacity is less than a lowest storage capacity of the lowest capacity physical disk of the disk group, replacing the predictive failure indicated physical disk with the replacement physical disk.Type: GrantFiled: September 9, 2014Date of Patent: December 13, 2016Assignee: DELL PRODUCTS, LPInventors: Neeraj Joshi, Vishnu M. Karrotu, Kavi K. Chakkravarthy
-
Patent number: 9519557Abstract: A compliance user or auditor is enabled to inject failures into a sandbox environment, which may be similar to a production service. The sandbox environment may be monitored by the same automation that watches compliance controls in the production service. As the user injects compliance failures into the sandbox, they may detect the appropriate alerts fire in the monitoring system, thereby gaining trust that the monitoring works as it should. A rich report resulting from the test activities may allow the user or auditor to see how a failure of a compliance control leads to the expected monitoring alert.Type: GrantFiled: July 11, 2014Date of Patent: December 13, 2016Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: David Nunez Tejerina, Arthur James Schwab, III
-
Patent number: 9519558Abstract: A method for identifying a device comprising generating, by a control device, an identification identifier of a multimedia device according to device description information of the multimedia device, sending the identification identifier to the multimedia device, so that the multimedia device displays the identification identifier, acquiring, by the control device, the identification identifier displayed by the multimedia device and an appearance image of the multimedia device, and acquiring the device description information according to the identification identifier displayed by the multimedia device, and associating, by the control device, the device description information with the appearance image of the multimedia device, so that a user equipment identifies the multimedia device according to the appearance image.Type: GrantFiled: September 8, 2015Date of Patent: December 13, 2016Assignee: Huawei Device Co., Ltd.Inventors: Yajun Zhang, Yu Zhu
-
Patent number: 9519559Abstract: A demand management monitoring system including a remote measurement device including a microprocessor for calculating RMS voltage data from digital samples and a wireless communications device, and a server system including a database configured to store the RMS voltage data from the remote measurement device.Type: GrantFiled: May 23, 2014Date of Patent: December 13, 2016Assignee: Power Monitors, Inc.Inventors: Walter Curt, Christopher Mullins
-
Patent number: 9519560Abstract: A system is disclosed for detecting if a remote device is associated with a power supply. The system may have a controller having machine readable, non-transitory executable code running thereon for varying a characteristic of a signal being applied to the power supply. The controller further may be configured to compare a measurement obtained from a measurement subsystem relating to a measured signal present at the remote device. The controller may also be configured to make a comparison between the signal being applied to the power supply and the measured signal obtained at the remote device, and to determine whether the remote device is electrically associated with the power supply.Type: GrantFiled: January 27, 2014Date of Patent: December 13, 2016Assignee: Liebert CorporationInventor: Richard J. Zajkowski
-
Patent number: 9519561Abstract: Embodiments of the present invention provide tools and facilities for instrumentation of application programs, including application programs that execute on mobile-electronics devices, including web browsers. The application-program and mobile-electronics-device environment is a superset of the web-analytics problem domain and provides many new opportunities and challenges for instrumentation-based data collection and data analysis. Certain embodiments of the present invention provide configuration-controlled embedded instrumentation that allows fine-granularity control of instrumentation operation by remote data-collection servers.Type: GrantFiled: April 15, 2011Date of Patent: December 13, 2016Assignee: Webtrends Inc.Inventor: Paul Claudell Lawbaugh
-
Patent number: 9519562Abstract: Methods and systems for allocating resources in a virtual desktop resource environment are provided. A method includes making a prediction on the future demand for processes running on a distributed environment with several hosts. The prediction is based on the process demand history and includes the removal of historic process demand glitches. Further, the prediction is used to perform a cost and benefit analysis for moving a candidate process from one host to another, and the candidate process is moved to a different host when the cost and benefit analysis recommends such move. In another embodiment, the predictions on future process demand are used for distributed power management by putting hosts in stand-by mode when the overall demand decreases or by adding hosts to the distributed environment when the load increases.Type: GrantFiled: October 25, 2011Date of Patent: December 13, 2016Assignee: VMware, Inc.Inventors: Canturk Isci, Chengwei Wang, Chirag Bhatt, Ganesha Shanmuganathan, Anne Marie Holler
-
Patent number: 9519563Abstract: A method for providing network performance monitoring using a performance database manager (PDM) is disclosed. A PDM has a PDM state manager, a communications server (COM server), a communications client (COM client), and an application database (AppDB). The PDM is configured to communicate with a network controller and a switch running a service monitoring (SERMON) client. A list of one or more switches, one or more hosted services, and one or more applications is determined. A request for service monitoring (SERMON) data is received from one or more applications running on a network controller. The request is sent to a SERMON client. A response is received from the SERMON client.Type: GrantFiled: May 9, 2013Date of Patent: December 13, 2016Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Ravi Manghirmalani, Ramesh Mishra, Ramesh Subrahmaniam
-
Patent number: 9519564Abstract: In one embodiment, a method comprises defining a temporal interval. The method further comprises saving a set of selected traces to a memory. The set of selected traces may be generated during the defined temporal interval. A starting point of the temporal interval may be defined upon a generated trace and an ending point of the temporal interval may be a length of time after the starting point. The set of selected traces may include at least one of a first trace, a highest priority trace, and a last trace. The set of selected traces may include a set of first traces, a set of high priority traces, and a set of last traces. The set of selected traces may include a set of traces over a priority threshold.Type: GrantFiled: September 28, 2012Date of Patent: December 13, 2016Assignee: EMC IP Holding Company LLCInventor: Marshall L. Merrill
-
Patent number: 9519565Abstract: A method for automatic monitoring of at least one component of a physical system, includes checking data of a data record for errors caused by a preceding data processing, checking the data in the physical context of the at least one sensor for errors resulting from infringements of assumptions of physical and/or system-related factors in elements of the measurement chain, the context of the component for errors resulting from infringements of the physical and/or system-related factors of the component, and—checking the individually asserted errors against one another and then either rejecting the error or outputting the error as an error message with reference to the error source.Type: GrantFiled: November 21, 2011Date of Patent: December 13, 2016Assignee: Rolls-Royce Deutschland Ltd & Co KGInventor: Stefan Hainzl
-
Patent number: 9519566Abstract: A method includes receiving a program code at a processor. The method also includes generating, via the processor, a heap model corresponding to the program code. The method further includes detecting, via the processor, a linearizable data structure in the program code. The method also further includes modifying, via the processor, the heap model based on the detected linearizable data structure. The method also further includes analyzing, via the processor, the program code using the modified heap model.Type: GrantFiled: June 9, 2015Date of Patent: December 13, 2016Assignee: International Business Machines CorporationInventors: Roee Hay, Omer Tripp
-
Patent number: 9519567Abstract: A device for generating a performance evaluation program includes: a memory; and a processor coupled to the memory. The processor is configured to: analyze a source code of a target program that is subject to performance evaluation, translate the source code into a binary code based on an analysis result of the source code while generating execution binary that has an evaluation area to be used in the performance evaluation at a target location corresponding to a candidate location of the target program, and write an evaluation code in the evaluation area of the execution binary to evaluate performance of the target program based on an evaluation item and the target location of the target program.Type: GrantFiled: July 23, 2014Date of Patent: December 13, 2016Assignee: FUJITSU LIMITEDInventors: Yuta Mukai, Hideki Miwa
-
Patent number: 9519568Abstract: A system and method for debugging an executing program. The method includes executing a general-purpose computing on graphics processing units (GPGPU) program. The GPGPU program comprises a first portion operable to execute on a central processing unit (CPU) and a second portion operable to execute on a graphics processing unit (GPU). The method further includes attaching a debugging program to the first portion of the GPGPU program and modifying the first portion of the GPGPU program. The attaching of the debugging program to the first portion of the GPGPU program pauses execution of the first portion of the GPGPU program. The method further includes resuming execution of the first portion of the GPGPU program and accessing a first state information corresponding to the first portion of the GPGPU program. Execution of the first portion of the GPGPU program may then be paused.Type: GrantFiled: December 31, 2012Date of Patent: December 13, 2016Assignee: NVIDIA CORPORATIONInventors: Mayank Kaushik, Alban Douillet, Geoffrey Gerfin, Vyas Venkataraman, Mark Hairgrove, Riley Andrews
-
Patent number: 9519569Abstract: A method for constructing data structures and a method for describing running states of a computer and state transitions thereof are provided. The method for constructing the data structure, which describes the execution processes of computer codes, includes: when the computer is running, constructs the data structure using the code segment wherein lies a calling instruction as a node and using the calling relationship between the code segment initiating the calling instruction and the called code segment, which are both constructed by the calling instruction, as a calling path. The data structure includes every node and the calling path between every calling and called nodes. When a certain calling instruction is executed, it is possible to describe the running state of the computer when the calling instruction is executed with the data structure consisting of all nodes and calling paths before the calling instruction by constructing the above data structure.Type: GrantFiled: September 26, 2010Date of Patent: December 13, 2016Assignee: Antaios (Beijing) Information Technology Co., Ltd.Inventors: Jiaxiang Wang, Lidong Qu
-
Patent number: 9519570Abstract: Embodiments of the present invention disclose a method, computer program product, and system for recording and displaying graphical user interface snapshots during automated testing. A computer captures a first snapshot of a complete graphical user interface, wherein the graphical user interface has at least one graphical user interface control. The computer determines a location of the at least one graphical user interface control. The computer determines that a first test step has altered the at least one graphical user interface control. The computer captures a second snapshot of the altered graphical user interface control. The computer stores the second snapshot and the location of the graphical user interface control in association with the test step.Type: GrantFiled: March 19, 2014Date of Patent: December 13, 2016Assignee: International Business Machines CorporationInventors: Balaji Srinivasan, Madhu Tadiparthi
-
Patent number: 9519571Abstract: Techniques are provided for analyzing testing coverage of one or more software modules to provide process coverage statistics. The techniques include obtaining one or more coverage measures from a test specification document, performing a trace on each of the one or more coverage measures during a test, analyzing each trace to generate a run-time service choreography model for a process, wherein the model includes each of one or more service choreography patterns occurring in the process, and using the model to provide statistical data on test coverage according to a process definition.Type: GrantFiled: July 13, 2007Date of Patent: December 13, 2016Assignee: International Business Machines CorporationInventors: Zhong Jie Li, He Hui Liu, Naomi M. Mitsumori, Krishna Ratakonda, Hua Fang Tan, Jun Zhu
-
Patent number: 9519572Abstract: The present invention relates to a virtual machine, and specifically discloses a method and apparatus for creating a software performance testing environment based on a virtual machine, wherein the method comprises: in response to obtaining a hard disk read/write request triggered by a virtual CPU of the virtual machine, notifying a virtual CPU scheduler to record a CPU time quota t1 already consumed by the virtual CPU in a current CPU schedule period; in response to detecting completion of hard disk read/write processing corresponding to the hard disk read/write request, predicting a hard disk read/write latency t corresponding to the hard disk read/write request in a target environment; notifying the virtual CPU scheduler to determine a CPU time quota already consumed by the virtual CPU in the current CPU schedule period based on the recorded CPU time quota t1 and the hard disk read/write latency t; and adjusting a system clock of the virtual machine based on the determined CPU time quota already consumed bType: GrantFiled: March 31, 2015Date of Patent: December 13, 2016Assignee: International Business Machines CorporationInventors: Xin Hao Cheng, Guo Qiang Hu, Jun Chi Yan, Jun Zhu
-
Patent number: 9519573Abstract: A method for creating a software performance testing environment based on a virtual machine, wherein the method comprises: in response to obtaining a hard disk read/write request triggered by a virtual CPU of the virtual machine, notifying a virtual CPU scheduler to record a CPU time quota t1 already consumed by the virtual CPU in a current CPU schedule period; in response to detecting completion of hard disk read/write processing corresponding to the hard disk read/write request, predicting a hard disk read/write latency t corresponding to the hard disk read/write request in a target environment; notifying the virtual CPU scheduler to determine a CPU time quota already consumed by the virtual CPU in the current CPU schedule period based on the recorded CPU time quota t1 and the hard disk read/write latency t; and adjusting a system clock of the virtual machine based on the determined CPU time quota already consumed by the virtual CPU in the current CPU schedule period.Type: GrantFiled: June 23, 2015Date of Patent: December 13, 2016Assignee: International Business Machines CorporationInventors: Xin Hao Cheng, Guo Qiang Hu, Jun Chi Yan, Jun Zhu
-
Patent number: 9519574Abstract: A computing device includes a primary content storage machine configured to selectively store one or more content portions of a digital content item, such as game portions of a video game. The computing device is configured to determine a size of a dynamically changing content access window including one or more content portions usable to provide an above-threshold user experience, such as uninterrupted game play, based on a current access position of the digital content item or video game and historical user-specific play patterns or game play consumption rates of different users. The computing device is configured to dynamically load the primary content storage machine with the content portions or game portions corresponding to the content access window and dynamically unload the content or game portions outside of the content access window from the primary content storage machine.Type: GrantFiled: November 28, 2012Date of Patent: December 13, 2016Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Frank R. Morrison, III, Brandon Hunt, Alexander Burba
-
Patent number: 9519575Abstract: Apparatuses, systems, methods, and computer program products are disclosed for conditional iteration. A method includes receiving a request comprising a condition. A method includes checking an address mapping structure for entries satisfying a condition for a request. A method includes providing a result for a request based on one or more entries satisfying a condition for a request.Type: GrantFiled: July 18, 2013Date of Patent: December 13, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Bharath Ramsundar, Nisha Talagala, Swaminathan Sundararaman
-
Patent number: 9519576Abstract: A memory controller controlling a nonvolatile memory device having a plurality of memory blocks as a data storage space includes an error detection and correction circuit and a reclaim control unit. The error detection and correction circuit receives data from a memory block and calculates a comparison result by comparing a bit error rate of the received data and a predetermined value. The reclaim control unit determines whether or not to perform a read reclaim operation depending on the comparison result and a read voltage used to read the data. The read reclaim operation copies the data to a memory block different from a memory block having stored the data.Type: GrantFiled: November 15, 2013Date of Patent: December 13, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Youngil Seo, Jungho Yun, Wonchul Lee, Dawoon Jung
-
Patent number: 9519577Abstract: The embodiments described herein include systems, methods and/or devices that may enhance the endurance of a storage system including a storage medium. The method includes: dividing a plurality of flash memory devices into logical chunks each logical chunk including one or more flash memory blocks; and detecting a trigger condition with respect to a respective flash memory device of the plurality of flash memory devices. In response to detecting the trigger condition, the method includes: selecting one of the logical chunks of the respective flash memory device for migration in accordance with predefined selection criteria; and storing a replicated logical chunk, comprising a copy of the selected logical chunk, at a second flash memory device. The method includes: remapping an address of the selected logical chunk to a physical location of the replicated logical chunk; and decreasing a number of logical chunks associated with the respective flash memory device.Type: GrantFiled: August 27, 2014Date of Patent: December 13, 2016Assignee: SANDISK TECHNOLOGIES LLCInventor: Warren Fritz Kruger
-
Patent number: 9519578Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.Type: GrantFiled: November 25, 2015Date of Patent: December 13, 2016Assignee: Radian Memory Systems, Inc.Inventors: Andrey V. Kuzmin, James G. Wayda
-
Patent number: 9519579Abstract: Technique for analyzing memory areas based on local copies of a global counter by: (i) determining a plurality of currently-executing fast threads and a plurality of currently executed slow threads; (ii) intermittently incrementing a global counter variable to have a current global counter value; (iii) intermittently setting the local counter of the data set for each fast thread of the plurality of fast threads to be equal to the current global counter value; (iv) determining that no slow threads of the plurality of slow threads reference the first memory region; (v) assigning a free-after value to the first memory region; (vi) determining whether the free-after value of the first memory region is less than or equal to all of the local counters of the fast thread data sets of the plurality of fast threads; and (vii) de-allocating the first memory region.Type: GrantFiled: March 31, 2015Date of Patent: December 13, 2016Assignee: International Business Machines CorporationInventors: Ian C. Edwards, Jonathan Levell, Andrew J. Schofield
-
Patent number: 9519580Abstract: An approach is provided in which a storage system includes a first storage controller, a second storage controller, and multiple logical units. The storage system determines that a controller traffic load ratio between the first storage controller and the second storage controller has reached a threshold. In turn, the storage system selects one of the logical units and changes a preferred controller ownership of the selected logical unit from the first storage controller to the second storage controller to balance the controller traffic load ratio.Type: GrantFiled: November 11, 2013Date of Patent: December 13, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Michael S. Anderson, Malahal R. Naineni, Chandra Seetharaman
-
Patent number: 9519581Abstract: Techniques for enabling integration between a storage system and a host system that performs write-back caching are provided. In one embodiment, the host system can transmit to the storage system a command indicating that the host system intends to cache, in a write-back cache, writes directed to a range of logical block addresses (LBAs). The host system can further receive from the storage system a response indicating whether the command is accepted or rejected. If the command is accepted, the host system can initiate the caching of writes in the write-back cache.Type: GrantFiled: September 16, 2013Date of Patent: December 13, 2016Assignee: VMware, Inc.Inventors: Andrew Banta, Erik Cota-Robles
-
Patent number: 9519582Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.Type: GrantFiled: August 24, 2015Date of Patent: December 13, 2016Assignee: Micron Technology, Inc.Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler