Abstract: A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.

Abstract: A memory system may include a plurality of chips configured to have an operation speed of a predetermined target speed or less. The memory system may include an error correction code (ECC) circuit configured to correct an error of each chip having an operation speed of higher than the target speed from among the plurality of chips.

Abstract: Memory systems may include a memory portion, and a controller suitable for receiving information data, generating first stage data, generating a first portion parity information, generating a second portion parity information based at least in part on the first portion parity information and the first stage data, and outputting the second portion parity information.

Abstract: Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.

Abstract: Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and to the memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. When additional unique pillar combinations of at least read threshold number of encoded data slices (EDSs) supported by EDSs may be needed, the computing device dispersed error encodes each data segment in accordance to generate additional pluralities of EDSs and distributedly stores the additional pluralities of EDSs associated respectively with the data object across the plurality of SUs within the DSN to support the additional unique pillar combinations of the at least read threshold number of EDSs.

Abstract: Services associated with first and second nodes are managed. As part of the management, the first node receives a request to modify the services. A synchronization policy is identified. The synchronization policy requires that modifications attempted on the set of services on the first node also be attempted on the second node. In response to the request, an attempt is made to modify the set of services on the first node. Further, in response to the request and pursuant to the synchronization policy, the second node is caused to attempt to modify the set of services. The synchronization policy is identified as a relaxed synchronization policy. A determination is made that the attempt to modify the set of services on the second node failed. Based on identifying that the synchronization policy is a relaxed synchronization policy, the attempt to modify the set of services on the first node continues.

Abstract: A failure to load a primary operating system at a data processing device is identified. A partition in a volatile random access memory is allocated to store a second operating system. The second OS is stored at the partition. Information identifying the partition is stored at a first location accessible to a basic input output system executing at the data processing device.

Abstract: An energy-efficient nonvolatile microprocessor includes a processing core, a nonvolatile flip-flop array, a set of nonvolatile interconnections, and a store-enable register. When a power source is recovered to a stable state, the processing core determines whether data of nonvolatile registers is not transmitted before power-off. If yes, the processing core executes programmable recovery entry decision to avoid recovery failures for different applications. The processing core has plural system states divided into programmer visible states and programmer invisible states. The nonvolatile interconnections are connected between the processing core and the nonvolatile flip-flop array. When the power source is unstable, the processing core only stores the programmer visible states into the nonvolatile flip-flop array and, at the same time, only stores the system states of the peripheral modules corresponding to the bits of the store-enable register that are set to be “true” into the nonvolatile flip-flop array.

Abstract: Responsive to a request from a user device, a content server may perform an electronic discovery function. The request may include information on a quantity of data objects desired from a collection of data objects stored in a repository. Objects stored in the repository may be managed by the content server. The content server may determine a number of batches and process the collection of data objects into batches, each having a batch size. An efficient selection process may be determined and utilized in selecting data objects from each of the batches such that a total number of data objects selected from the collection is not less than the quantity of data objects desired. The content server may make a disk image of the selected data objects and communicate same to the user device over a network.

Abstract: Determining the bandwidth required for data replication for disaster recovery. Given a specified recovery point objective (RPO), bandwidth requisitioning and usage is determined according to meet the RPO based on observed factors.

Abstract: Data files can be backed up by copying, in response to a backup request, files from a client device to a backup archive and recording the status of the files. Transformed copies of files in the backup archive can be created by automatically applying a transform to the files received from the client device. Upon receiving a subsequent backup request, differences can be identified between transformed files in the backup archive and files on the client device, and in response to identified differences in the files, the transformed files can be copied back to the client device.

Abstract: Provided a computer program product, system, and method for rebuilding damaged areas of a volume table using a volume data set for managing data sets assigned data units in a volume in a storage. A determination is made of damaged areas in a volume table providing information on data sets allocated in the volume. The determined damaged areas are formatted to produce reformatted areas to make the volume table usable. A volume data set in the volume having information on data sets configured in the volume is processed to determine from the volume data set salvaged data sets comprising the data sets in the volume not indicated in the volume table. Data set information is rebuilt in the reformatted areas of the volume table for the salvaged data sets.

Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a computer implemented method that includes receiving an out-of-synchronization indication associated with at least one of a plurality of channels in the memory system. A memory control unit in communication with the channels performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.

Abstract: The present disclosure includes detecting a failure associated with a first storage location on which a first agent virtual computing instance (AVCI) is deployed, wherein the first AVCI is being executed by a first hypervisor, stopping the execution of the first AVCI, determining whether a second AVCI that provides services analogous to the first AVCI is being executed by a second hypervisor and is deployed on a second storage location, creating a linked clone of the second AVCI on the second storage location responsive to the second AVCI being executed by the second hypervisor and deployed on the second storage location, redeploying the first AVCI on the second storage location responsive to the second AVCI not being executed by the second hypervisor or not deployed on the second storage location, and deleting files of the first AVCI from the first storage location after the failure is corrected.

Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. A method of testing a spike filter in a legacy I2C device includes generating a command to be transmitted on a serial bus in accordance with an I2C protocol, where the command includes an address corresponding to the legacy slave device, merging the command with a sequence of pulses to obtain a test signal, transmitting the test signal on the serial bus, and determining the efficacy of a spike filter in the first slave device based on whether the legacy slave device acknowledges the test signal. Each pulse in the sequence of pulses has a duration that is less than 50 ns. The spike filter is expected to suppress pulses that have a duration of less than 50 ns.

Abstract: Embodiments generally relate to a universal debug design which involves integrating a debug controller and a debug card with display together into a single debug design. Debug codes, such as power-on self-test (POST) codes and other error codes, are generated by various subsystems of a server-related system. The codes are transmitted to a controller, which stores the codes in memory. In some embodiments, a multiplexer outputs one debug code from the multitude of received codes, based on a user or event selecting which desired debug code should be displayed. In some embodiments, a decoder converts and sends the LED display signals to a debug card, which displays the debug code on a 7-segment LED display.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for: allocating a plurality of nodes; implementing a first pool of workers on the plurality of nodes, each node including one or more of the workers from the first pool; providing a set of instructions to the first pool of workers for performing a first task configured to interact with the computer system; employing the first pool of workers to perform the first task; and monitoring at least one performance metric associated with the computer system while the workers from the first pool are performing the first task.

Abstract: In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

Abstract: An input/output (I/O) line test device and a method for controlling the same are disclosed, which may relate to a technology for testing a base die having no cell using various patterns. The I/O line test device may include an interface controller configured to perform signal transmission/reception between a pad and an input/output line (IOL), and a signal transceiver configured to perform signal transmission/reception between the IOL and a through silicon via (TSV). The I/O line test device may include a latch unit configured to latch output data of the signal transceiver, and a test controller configured to output a control signal for controlling whether the signal transceiver performs a reception operation in response to a write enable signal and a test signal.

Abstract: In an approach for managing a set of tests to run on a set of platforms, a processor identifies a set of tests to run on a set of platforms and one or more priorities associated with the set of tests. A processor sends the set of tests and the one or more priorities associated with the set of tests to the set of platforms. A processor receives information about a first test run of a first test on a first platform of the set of platforms. A processor determines that the first test failed on the first platform. A processor updates the one or more priorities associated with the set of tests. A processor sends the updated one or more priorities associated with the set of tests to at least the second platform.

Abstract: A signal detection system includes a motherboard and a signal detection card. The signal detection card includes a connecting plate, a first interface, and a detection module. The first interface is mounted in the connecting plate. The connecting plate includes a first signal detection terminal. The first interface is coupled to the first signal detection terminal of the connecting plate. The first interface is coupled to the motherboard to receive a signal from the motherboard. The detection module is configured to couple to the first signal detection terminal of the connecting plate and detect the signal via the first interface. A signal detection card is also provided.

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.

Abstract: Method, system and product for assessments of an operation of an Heating Ventilation or Air-Conditioning (HVAC) unit. In module for receiving, directly or indirectly, information from at least one sensor; and a power consumption determination component for indirectly assessing power consumption of an HVAC unit from the information received from the at least one sensor. In another embodiment, the apparatus being configured to receive a set of physical measurements over time from a physical location that is affected by the HVAC unit; fitting the set of physical measurements on a predetermined curve using parametric fit, wherein the predetermined curve has an horizontal asymptote, wherein the predetermined curve has a decreasing slope over time; and comparing a target measurement of the HVAC unit with a location of the horizontal asymptote to determine whether the HVAC unit is expected to reach the target measurement.

Abstract: An application performance management system is disclosed. Operational elements are dynamically discovered and extended when changes occur. Programmatic knowledge is captured. Particular instances of operational elements are recognized after changes have been made using a fingerprint/signature process. Metrics and metadata associated with a monitored operational element are sent in a compressed form to a backend for analysis. Metrics and metadata from multiple similar systems may be used to adjust/create expert rules to be used in the analysis of the state of an operational element. A 3-D user interface with both physical and logical representations may be used to display the results of the performance management system.

Abstract: A system and method to parallelize data race detection in multicore machines are disclosed. The system and method does not generally require any change in the underlining system and the same race detection algorithm may be used, such as FastTrack. In general, race detection is separated from application threads to perform data race analysis in worker threads without inter-thread dependencies.

Abstract: Embodiments of the present invention provide a system and method for a dynamic tracing framework for debugging in a virtualized environment. Embodiment of the present invention can include selecting a home node and a set of remote nodes to which apply a set of probes. Data collection is performed by a tracing agent of each node and the collection of data is shared across multiple software systems.

Abstract: A debugging method is proposed in the disclosure. A computer running a program generates a master core dump file and one or more slave core dump files in response to a triggering event such as an internal failure. The core dump files are analyzed by another computer for debugging the program. The master core dump file includes an index list, and each entry of the index list corresponds to a slave core dump file of the one or more slave core dump files. The master core dump file can be the first to be transferred to the other computer. Based on the information in the index list, the other computer selectively requests one or more slave core dump files from the generated slave core dump files for debugging.

Abstract: As disclosed herein a method, executed by a computer, includes launching a session corresponding to a test environment, saving a session context to provide a saved session context, and associating the saved session context with a defect record entered in a defect tracking system. The method further includes receiving a request to recreate the test environment using the saved session context and reconnecting to a session corresponding to the saved session context, in response to receiving the request to recreate the test environment. The method further includes terminating the session corresponding to the saved session context, in response to verifying resolution of an error identified in the defect record. A computer system, and a computer program product corresponding to the method are also disclosed herein.

Abstract: As disclosed herein a method, executed by a computer, includes launching a session corresponding to a test environment, saving a session context to provide a saved session context, and associating the saved session context with a defect record entered in a defect tracking system. The method further includes receiving a request to recreate the test environment using the saved session context and reconnecting to a session corresponding to the saved session context, in response to receiving the request to recreate the test environment. The method further includes terminating the session corresponding to the saved session context, in response to verifying resolution of an error identified in the defect record. A computer system, and a computer program product corresponding to the method are also disclosed herein.

Abstract: An approach for dynamic test topology visualization is provided. The approach retrieves test data from one or more databases. The approach retrieves test data from an application under test. The approach creates a visual diagram, wherein the visual diagram includes one or more topological elements, one or more topological relationships between the one or more topological elements, the test data, and a screen snapshot of an application under test. The approach overlays the visual diagram with user interaction information. The approach associates the visual diagram to the test execution performed on the application under test.

Abstract: Examples disclosed herein provide tools for capturing spatial gestures performed by a user and scripting the gestures for testing an application under test. Scripts may be produced by capturing movement of extremities of a skeletal body corresponding to the user, wherein the movement is captured according to a change in coordinates of the extremities from an original position. The movement of the extremities may be matched to a predefined gesture found in a gesture database. A script may be generated from the matched predefined gesture with reference to the extremities captured and coordinates of the extremities from the original position, such that the user is emulated.

Abstract: An automated software resting and validation system allows testing of a software application under test (SAUT) regardless of the dynamic nature of the SAUT. An abstracted set of hierarchal or linear objects model certain regions of the SAUT. Automated test scripts utilize theses regions to intuitively navigate and identify potions of the SAUT to automate. The scripts also access specific SAUT elements contain within each defined region. These elements can then be used to invoke actions or verify outputs there from. The system uses a set of rich identification rules embodied in the system which allow the user to configure the identification of any element within the abstracted region. The rules are customizable to allow the user to configure the desired level of loose coupling between the automated scripts and the target element to adapt the scripts to the nature of the SAUT.

Abstract: Disclosed is a method of preparing and launching a test application on a first machine that is automatically executed on a second machine. A developer can prepare a test application on the first machine, and instead of the developer performing multiple steps to copy the test program to a second machine and set up the test environment, the method can automatically detect test environment data, and transmit the test application and the test environment data. Test environment data can include the directory of where the test program should be installed and executed. The test application can be run on the second machine and the results can be returned to the first machine where they can be displayed to the developer.

Abstract: An approach for dynamic test topology visualization is provided. The approach retrieves test data from one or more databases. The approach retrieves test data from an application under test. The approach creates a visual diagram, wherein the visual diagram includes one or more topological elements, one or more topological relationships between the one or more topological elements, the test data, and a screen snapshot of an application under test. The approach overlays the visual diagram with user interaction information. The approach associates the visual diagram to the test execution performed on the application under test.

Abstract: A system for checking data for errors, the system comprising a checking module operable to check tuples of data stored in a target database for errors, the tuples in the target database originating from the output of at least one query transformation module which applies a query transformation to tuples of data from at least one data source an identification module operable to identify a problematic tuple from a data source that produces an error in the target database, the identification module being operable to quantify the contribution of the problematic tuple in producing the error in the target database, and a description generation module operable to generate a descriptive query which represents at least one of errors identified by the checking module in the target database which are produced by the at least one query transformation module, and problematic tuples identified in a data source by the identification module.

Abstract: A system and method for communicating with power tools using a universal protocol. The universal protocol may be implemented using a universal core module that is installed across a variety of power tools and other devices to enable communications therewith. Communications to and from the power tools are translated to a universal protocol once received. The translated communications are handled by the universal core module of a particular tool according to a set of rules. In response, the universal core module outputs communications according to the universal protocol and the set of rules, which may be translated to another protocol for receipt by components of the tool or an external device. The communications may be used, for example, to obtain tool performance data from the tools and to provide firmware updates.

Abstract: Embodiments of the invention relate to sparsity-driven matrix representation. In one embodiment, a sparsity of a matrix is determined and the sparsity is compared to a threshold. Computer memory is allocated to store the matrix in a first data structure format based on the sparsity being greater than the threshold.

Abstract: A memory heap management facility is provided that is able to perform various management tasks, including, but not limited to, garbage collection, compaction, and/or re-ordering of objects within a heap. One or more of these management tasks improve system performance by limiting movement of pages in and out of virtual memory. The garbage collection technique selectively performs garbage collection such that certain objects, such as old but live, infrequently referenced objects, are not garbage collected each time garbage collection is performed.

Abstract: A method and technique are provided for providing a service address space. The method includes providing a service co-processor with a service address space attached to a main processor. The main processor is provided with a main address space, and the service address space and the main address space include a full range of memory available to the respective service-co-processor and the main processor. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service address space is updated by receiving storage delta packets from the main processor and applying the storage delta packets to the service address space.

Abstract: A system and a method are disclosed to control flow of victim transactions received at a coherent interconnect from a coherent device of a processing system. A victim transaction is received from the coherent device at the coherent interconnect if a value of a first token indicates that at least one victim transaction is available to be received by the coherent interconnect. A victim transaction is available to be received by the coherent interconnect for each increment of the value of the first token greater than zero. The value of the first token is decremented for each victim transaction received by the coherent interconnect from the coherent device. An indication of the value of the first token is sent to the coherent device from the coherent interconnect.

Abstract: A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.

Abstract: A hint bit detection and correction method uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.

Abstract: There is provided a data processing device including an output port to transmit a request value to an interconnect arranged to implement a coherency protocol, to indicate a request to be subjected to the coherency protocol. An input port receives an acknowledgement value from the interconnect in response to the request value and coherency administration circuitry defines behaviour rules for the data processing device in accordance with the coherency protocol and in dependence on the request value and the acknowledgement value. Storage circuitry administers data in accordance with the behaviour rules. There is also provided an interconnect including an input port to receive a request value, issued by a data processing device having storage circuitry, to indicate a request for the data processing to be subjected to a coherency protocol.

Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.

Abstract: Route table cache clear commands may be performed using a communications platform that communicates with a web service and/or terminal emulator. The communications platform may implement a command that clears the route tables for an IPv4 network or link. The communications platform may also implement a general command that clears the route tables for all IPv4 and IPv6 networks or links, or any subsets thereof. These commands may give an administrator greater flexibility in managing the impact of network or configuration changes on the behavior of the communications platform. When network changes occur, the administrator may use these commands to invoke re-discovery of network paths, potentially avoiding connection interruptions.

Abstract: Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer implemented method for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a component used in a power-loss save of the write cache. The component is selected from the group consisting of an energy storage element, a non-volatile memory, and a transfer logic. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.

Abstract: The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Abstract: In one embodiment, a computer-implemented method includes receiving a large frame area (LFAREA) request, including a request for a plurality of page frame table entries (PFTEs) to back a plurality of frames in an LFAREA of main memory. Each of the plurality of frames has one of a first size and a second size, where the second size is larger than the first size. The method further includes counting how many frames in the main memory have yet to be initialized and have one of the first size and the second size. A size needed for the plurality of PFTEs is calculated, based at least in part on the counting. A storage area is reserved for the plurality of PFTEs, by a computer processor, where a size of the storage area is the size calculated based at least in part on the counting.