Abstract: A mechanism for performing monitoring system activities using a performance monitor. A method of embodiments of the invention includes identifying a plurality of monitoring tools to monitor activities of a plurality of system components at the computer system, and each monitoring tool monitors activities of at least one system component of the plurality of system components. The method further includes generating a monitoring template to include monitoring capabilities of each of the plurality of monitoring tools, and customizing, via the monitoring template, the performance monitor to serve as a universal monitoring tool to facilitate the plurality of monitoring tools to monitor the activities of the plurality of system components.

Abstract: Methods and systems for dynamically providing application analytic information are provided herein. The method includes inserting instrumentation points into an application file via an application analytic service and dynamically determining desired instrumentation points from which to collect application analytic data. The method also includes receiving, at the application analytic service, the application analytic data corresponding to the desired instrumentation points and analyzing the application analytic data to generate application analytic information. The method further includes sending the application analytic information to a client computing device.

Abstract: A method for code analysis comprising steps of inputting program code to an analyzer, assigning an objective quality measure to components of the analyzed code; and displaying graphically the objective quality measures.

Abstract: Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.

Abstract: Embodiments of the present invention provide methods, systems, and computer program products for building an environment. Embodiments of the present invention can be used to allocate resources and build an environment such that the environment is built when a user is prepared to test one or more portions of code in the environment. Embodiments of the present invention can be used to reduce the “lag time” developers experience between waiting for the code to be built and for resources to be provisioned, and can also provide a less costly alternative to maintaining and operating dedicated environments.

Abstract: A system for testing two or more applications associated with a computerized process may include a central repository, a user interface and a testing coordinator. The central repository may be used to store at least one test case each including a test data set and two or more sets of test scripts. The user interface may facilitate a selection of one or more test cases for use by the testing coordinator. The testing coordinator may be configured to test the operation of the computerized process by initiating testing of a first application by a first test tool using the test data set and a first set of scripts and initiating testing of the second application by the second test tool using the test data set and the second set of scripts from the selected test case. In some cases, the first test tool is incompatible with the second test tool.

Abstract: A system for testing two or more applications associated with a computerized process may include a central repository, a user interface and a testing coordinator. The central repository may be used to store at least one test case each including a test data set and two or more sets of test scripts. The user interface may facilitate a selection of one or more test cases for use by the testing coordinator. The testing coordinator may be configured to test the operation of the computerized process by initiating testing of a first application by a first test tool using the test data set and a first set of scripts and initiating testing of the second application by the second test tool using the test data set and the second set of scripts from the selected test case. In some cases, the first test tool is incompatible with the second test tool.

Abstract: A method for testing a software application is provided. The method may comprise associating a plurality of controls on a software application screen with testing actions to be performed on the controls, thereby creating a plurality of test steps, and generating a test component. The method may include analyzing a plurality of testing actions on a software application screen to learn characteristics of the testing actions and automatically assigning one or more parameters to one or more of the plurality of test steps based on a library that matches parameters to the names of testing actions. A parameter may comprise a reference to a column in a test data spreadsheet, which is separate from the test component and the library, the column in the test data spreadsheet comprising a plurality of different rows of test data to be utilized in conjunction with an associated control.

Abstract: A chip multiprocessor includes a plurality of cores each having a translation lookaside buffer (TLB) and a prefetch buffer (PB). Each core is configured to determine a TLB miss on the core's TLB for a virtual page address and determine whether or not there is a PB hit on a PB entry in the PB for the virtual page address. If it is determined that there is a PB hit, the PB entry is added to the TLB. If it is determined that there is not a PB hit, the virtual page address is used to perform a page walk to determine a translation entry, the translation entry is added to the TLB and the translation entry is prefetched to each other one of the plurality of cores.

Abstract: A technique for efficient swap space management creates a swap reservation file using thick provisioning to accommodate a maximum amount of memory reclamation from a set of one or more associated virtual machines (VMs). A VM swap file is created for each VM using thin provisioning. When a new block is needed to accommodate page swaps to a given VM swap file, a block is removed from the swap reservation file and a block is added to the VM swap file, thereby maintaining a net zero difference in overall swap storage. The removed block and the added block may be the same storage block if a block move operation is supported by a file system implementing the swap reservation file and VM swap files. The technique also accommodates swap space management of resource pools.

Abstract: A method for optimizing memory usage in a device having a universal controlling application includes receiving into the device data for use in configuring the universal controlling application wherein the data is used to identify from within a library of command code sets stored in a memory of the device a command code set that is appropriate for use in commanding functional operations of the appliance and causing a non-identified one or more of the command code sets of the library of command code sets stored in the memory of the device to be discarded to thereby create freed space in the memory of the device.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable local hash value generation in a non-volatile data storage system (e.g., using a flash memory device). In one aspect, rather than having Bloom filter logic in a host, Bloom filter functionality is integrated in the non-volatile data storage system. In some implementations, at a non-volatile data storage system, the method includes receiving from a host a plurality of requests that specify respective elements. The method further includes, for each respective element specified by the received requests, (1) generating a respective set of k bit positions in a Bloom filter, using k distinct hash functions, where k is an integer greater than 2, and (2) setting the respective set of k bit positions in the Bloom filter, which is stored in a non-volatile storage medium of the non-volatile data storage system.

Abstract: Systems and methods are provided for performing memory management in a storage device. The systems and methods may include receiving, at the storage device, a command to perform an operation on a data segment, wherein the command includes an indication of access properties associated with the data segment. The systems and methods may further include determining a plurality of physical memory locations associated with the data segment, and performing memory management on the plurality of physical memory locations based on information about the access properties.

Abstract: The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data.

Abstract: A data storage device includes a data storage medium, a cache, and a cache control memory. The data storage medium has M data blocks. M is an integer greater than 1. The cache includes N cache blocks having N cache block addresses, respectively. N is an integer greater than 1. The cache control memory includes M memory elements corresponding to the M data blocks, respectively. The cache control memory is configured to, in response to a request to cache data of one of the M data blocks: (a) write the data from the one of the M data blocks to one of the N cache blocks; and (b) write, in the one of the M memory elements corresponding to the one of the M data blocks, one of the N cache block addresses corresponding to the one of the N cache blocks where the data is written.

Abstract: Software solutions in a business software framework can expose their data via web services, which can readily provide access to all non-customized fields of objects included as part of the default installation of the software solution. However, customer-added extensions, such as for example custom fields and the like, added to customize the software solution for a specific business or business use can be difficult to add to web services by a typical business user who lacks technical abilities. Described herein are approaches to enabling addition of custom fields to web services via an intuitive interface that does not require technical understanding of the software solution, the business software framework, web services, etc.

Abstract: Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.

Abstract: An apparatus includes a fuse array and a stores. The fuse array is disposed on a die, and is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompresses the compressed configuration data, and stores a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores, and where, following a power gating event, one of the each of the plurality of cores subsequently accesses a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the caches.

Abstract: A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.

Abstract: A scalable, storage cloud enabled data center includes a cluster of enterprise storage nodes. Each storage node includes a storage grid, a computation grid, and data availability and data protection modules. The data center is scaled by adding additional storage nodes to a cluster of storage nodes which are interconnected, e.g., via a hardware interface, switches, and switch-routers.

Abstract: Disclosed is a system for controlling write actions to a plurality of data storage devices, the system comprising a plurality of write caches, wherein each cache is associated with a set of said data storage devices; and a controller adapted to issue write permissions to said data storage devices, said write permissions including a permission to perform a data destage operation from a cache to a data storage device; wherein each cache has a first performance score expressed as the difference between the number of data destage operations said cache has in flight and the maximum number of data destage actions said cache is permitted to issue in parallel; and wherein the controller is adapted to offer a data destage operation permission to the cache in said plurality of caches associated with the highest first performance score.

Abstract: Embodiments of the present invention disclose a method and apparatus of cache management for a non-volatile storage device. The method embodiment includes: determining a size relationship between a capacity sum of a clean page subpool and a dirty page subpool and a cache capacity; determining, when the capacity sum is equal to the cache capacity, whether identification information of a to-be-accessed page is in a history list of clean pages or a history list of dirty pages; and when it is determined that the identification information of the to-be-accessed page is in the history list of clean pages, adding a first adjustment value to a clean page subpool capacity threshold; and when the identification information of the to-be-accessed page is in the history list of dirty pages, subtracting a second adjustment value from the clean page subpool capacity threshold.

Abstract: A system and computer program product for resetting of memory locks in a transactional memory system. The system includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The system further includes the processor determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.

Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment, a fractured erase process is performed in which a pre-program process, erase process and soft program process are initiated independently. Memory cells can be pre-programmed and conditioned independent of an erase command. The initiation of the independent pre-programming is partitioned from an erase command which is partitioned from initiation of a soft-programming command. A cell is erased wherein the erasing includes erase operations that are partitioned from the pre-preprogramming process. In one embodiment, the independent pre-program process is run in the background.

Abstract: Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.

Abstract: Memory encryption engine (MEE) integration technologies are described. A processor can include a processor core and an arbiter of a MEE system coupled to the processor core. The arbiter can receive a first contending request from a first queue and a second contending request from a second queue. The arbiter can further select the first queue to communicate the first message to an MEE of the MEE system or the second queue to communicate the second message to the MEE in view of arbitration criteria. The arbiter can further communicate the selected first message or the selected second message to the MEE.

Abstract: Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller. The memory device may have a register that enables or disables access to the portion when data indicating whether to enable or disable access to the portion is written into the register via a serial data in (SI) input.

Abstract: An information processing apparatus is configured to make access to a storage device via a first path. A virtualization control apparatus is configured to control access to a virtual storage device via a second path, where the virtual storage device is provided by virtualizing the storage device. The virtualization control apparatus sends an identifier of the storage device in response to a query from the information processing apparatus which requests information about a storage space that is accessible via the second path. The information processing apparatus incorporates the second path as an inactive standby path when the identifier received as a response to the query matches with an identifier of the storage device accessible via the first path.

Abstract: An input system includes a communication device and a first input device. The communication device includes a communication chip and a communication port. The first input device includes a signal port connectable with the communication port and a device connecting port connectable with a second input device. In an input method, the communication device transmits a first pairing signal to the first input device so as to acquire a first identification code and a connection information of the first input device, and then the communication device transmits a first inquiring signal containing the first identification code to the first input device so as to acquire a first input signal from the first input device. If a second pairing signal and a second inquiring signal are transmitted to the second input device, the communication device acquires a second input signal from the second input device.

Abstract: A method of selecting an interface by a hub, includes searching for a device of the hub, and measuring a distance from the hub to the device based on information of an available interface of the device that is received from the device. The method further includes setting an optimal interface to communicate with the device, based on the distance, and transmitting data to the device through the optimal interface.

Abstract: Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.

Abstract: Systems and methods for timing read operations with a memory device are provided. A timing signal from the memory device is received at a gating circuit. The timing signal is passed through as a filtered timing signal during a gating window. The gating circuit is configured to open the gating window based on a control signal. The gating circuit is further configured to close the gating window based on a first edge of the timing signal. The first edge is determined based on a counter that is triggered to begin counting by the control signal. At a timing control circuit, the control signal is generated based on i) a count signal from the counter, and ii) a second edge of the timing signal that precedes the first edge in time.

Abstract: An request controller for controlling requests of a processing unit. The request controller may include an request controller input for receiving an request and an request processing unit connected to the request controller input. The request may request to switch a context of said processing unit or to switch the processing unit from a current an operation to another operation. The request processing unit may decide on the request based on a decision criterion. An request controller output may be connected to the request processing unit, for outputting information about at least granted request. The request processing unit may include a control logic unit including: a state input for receiving information about a current state of a system including the processing unit; and a request input for receiving information about a received request.

Abstract: A computer can manage an interruption while a processor is executing a transaction in a transactional-execution (TX) mode. Execution, in a program context, of the transaction is begun by a processor in TX mode. An interruption request is detected for an interruption, by the processor, in TX mode. The interruption is accepted by the processor to execute a TX compatible routine in a supervisor context for changing supervisor resources. The TX compatible routine is executed within the TX mode. The processor returns to the program context to complete the execution of the transaction. Based on the transaction aborting, the processor does not commit changes to the supervisor resources.

Abstract: The disclosure is applied to a field of communication technologies and relates to a method for controlling multiple CAN interfaces through a single SPI bus.

Abstract: A method for operating an automation device having a CPU module that is configured to effect read or write access to local peripherals that are each provided with two interface modules that are each wired up in ring form to an input/output controller, wherein peripheral access operations are executed via one of the rings or via both rings, and wherein a redundancy manager that is provided for each ring is used to logically interrupt the respective ring in a normal mode and to initiate ring reconfiguration for this ring in the event of a physical ring interruption so as to provide a basis for allowing peripheral access operations during the actual period of this ring reconfiguration.

Abstract: Universal serial bus (USB) communication systems and methods are disclosed. In particular, aspects of the present disclosure optimize polling and scheduling of bulk data transfers from bulk endpoints connected through a USB connection. By reducing the amount of polling, and by favoring endpoints that are known to have data to transfer, unnecessary signaling is avoided. Reduction in signaling allows more data to be transferred in a shorter amount of time. Reducing the time required for a data transfer may allow for low power modes to be used, which in turn further saves power.

Abstract: Systems and methods for preventing excessive buffering of transactions in a coherence point. The coherence point uses a lookahead mechanism to determine if there are enough credits from the memory controller for forwarding the outstanding transactions stored in the IRQ. If there are not enough credits, then the coherence point prevents the switch fabric from forwarding additional transactions to the coherence point. By preventing excessive buffering in the IRQ, the QoS-based ordering of transactions performed by the switch fabric is preserved.

Abstract: Example embodiments disclosed herein relate to selectively connecting an interconnect bus to an expansion slot. A first chip is connected to a first interconnect bus. A second chip is connected to a second interconnect bus. A switch selectively connects the first interconnect bus to one of a plurality of expansion slots.

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

Abstract: Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.

Abstract: In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a packet for communication along an interconnect and to transmit the packet. This packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.

Abstract: A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal.

Abstract: A method begins by a processing module generating a payload section of a dispersed storage network (DSN) frame regarding a check request operation by generating one or more slice name fields of the payload section to include one or more slice names corresponding to one or more encoded data slices and generating a transaction number field of the payload section to include a transaction number corresponding to the check request operation. The method continues with the processing module generating a protocol header of the DSN frame by generating a payload length field of the protocol header to include a payload length that represents a length of the payload section and generating remaining fields of the protocol header.

Abstract: A method of determining orientation parameters of a rigid body, including: associating at least two multi-axis accelerometers with the rigid body, wherein the body has a base end, a distal end, and a line of symmetry between the base end and the distal end. The two first multi-axis accelerometers are disposed at a first point along the line of symmetry between the base end and the distal end. Each first multi-axis accelerometer is disposed at equal distances from the line of symmetry. The line of symmetry and both first multi-axis accelerometers lie in a first plane. The method further includes: associating a gyroscope with the body at the first point, equally between both first multi-axis accelerometers; gathering measured data from the two first multi-axis accelerometers and the gyroscope; and applying analysis free of calculus to determine a first inclination angle, of the body from a stable orientation.

Abstract: A driving analysis server may be configured to receive vehicle operation data from vehicle sensors, and may use the data to identify a potentially high-risk or unsafe driving event by the vehicle. The driving analysis server also may receive corresponding image data, video, or object proximity data from the vehicle or one or more other data sources, and may use the image, video, or proximity data to analyze the potentially high-risk or unsafe driving event. A driver score for the vehicle or driver may be calculated or adjusted based on the analysis of the data and the determination of one or more causes of the driving event.

Abstract: Asynchronous arithmetic units including an asynchronous IEEE 754 compliant floating-point adder and an asynchronous floating point multiplier component. Arithmetic units optimized for lower power consumption and methods for optimization are disclosed.

Abstract: A first source node transmits a first transmission vector formed by multiplying a vector of input values and an inverse of a transfer matrix that relates vectors transmitted from the first source node via a plurality of intermediate nodes to vectors received at a plurality of destination nodes. Each of the intermediate nodes transmits a vector formed by a linear operation performed on received vectors. The linear operation may be determined based on linear combinations of the first transmission vector and one or more second transmission vectors transmitted by second source nodes. The linear combinations are to be received at the destination nodes. The linear operation is chosen so that propagation of the first transmission vector through the intermediate nodes produces, at the destination nodes, predetermined linear combinations of the first transmission vector and one or more second transmission vectors transmitted by one or more second source nodes.

Abstract: In any context where a user can view multiple different content items, switching among content items is provided using an array mode. In a full-frame mode, one content item is visible and active, but other content items may also be open. In response to user input the display can be switched to an array mode, in which all of the content items are visible in a scrollable array. Selecting a content item in array mode can result in the display returning to the full-frame mode, with the selected content item becoming visible and active. Smoothly animated transitions between the full-frame and array modes and a gesture-based interface for controlling the transitions can also be provided.

Abstract: Therefore, what has been described is an improved for visually implementing a web page layout, where the web page layout includes a nested drop zone. Allowing the user to interactively implement nested drop zones provides numerous benefits, including the benefit of being able to create specialized layout configurations for a web page without requiring the need for expert programmers to write computer code for the new configuration. This permits the user to implement highly customized layout in a very easy and efficient way. In addition, an improved approach has been described to implement a new type of widget that obtains its context information from another widget. For example, when a contextual widget is dropped into a drop zone, that contextual widget would obtain its context data from its parent drop zone widget.