Patents Issued in January 24, 2017
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Patent number: 9552256Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.Type: GrantFiled: December 22, 2015Date of Patent: January 24, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-gyeum Kim, Hyeok-man Kwon, Young-jun Kwon, Ki-young Choi, Jun-whan Ahn
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Patent number: 9552257Abstract: Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.Type: GrantFiled: March 3, 2016Date of Patent: January 24, 2017Assignee: Micron Technology, Inc.Inventors: Zhenlei Shen, William H. Radke, Peter Feeley
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Patent number: 9552258Abstract: A redundant array of independent disk (RAID) memory storage system comprising data storage blocks arranged in a first plurality of data rows and a second plurality of data columns, wherein parity data is stored in additionally defined parity blocks, and wherein numbers of data blocks in respective columns are different, to accommodate the additional diagonal parity data block that the geometry of the system requires. The system is suitable for an SSD array in which sequential disk readout is not required.Type: GrantFiled: February 27, 2015Date of Patent: January 24, 2017Assignee: EMC IP Holding Company LLCInventors: Renen Hallak, Yaron Segev
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Patent number: 9552259Abstract: A method and system are provided for dynamic provisioning of snapshots in a data backup system with a software defined storage (SDS). The method implemented by the backup system receives a snapshot provisioning request including a user selection of snapshot objectives by a dynamic snapshot module, converts a file system reference mapping to a logical unit number (LUN) of the SDS, consolidates the snapshot provisioning request to the mapping and snapshot frequency, and passes the consolidated snapshot provisioning request to the SDS to provision snapshots.Type: GrantFiled: May 30, 2014Date of Patent: January 24, 2017Assignee: EMC IP Holding Company LLCInventors: Shelesh Chopra, Vladimir Mandic, John Rokicki, Joseph Murphy
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Patent number: 9552260Abstract: A method for using a retain block in application code executing on a virtual machine includes identifying an instruction in application code, the instruction pertaining to an object, determining the instruction is part of a retain block, prior to executing the instruction, determining whether the instruction is to cause the object to be modified, and when the instruction is to cause the object to be modified, storing data indicating a first state of the object in a retain block store and causing the first state of the object to be modified using a second state. Also, the method includes in response to an error occurring during an execution of the instruction, returning the object from the second state to the first state using the stored data.Type: GrantFiled: June 2, 2014Date of Patent: January 24, 2017Assignee: Red Hat, Inc.Inventors: Filip Eliá{hacek over (s)}, Filip Nguyen
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Patent number: 9552261Abstract: A method begins by a processing module of a dispersed storage network (DSN) identifying a data segment to be retrieved from storage units of the DSN, where the data segment is encoded into a set of encoded data slices that is divided into block sets of encoded data slices, and where each storage unit stores a block set of encoded data slices. The method continues with the processing module generating a set of read requests in accordance with retrieval information which assures that at least a decode threshold number of encoded data slices of the set are retrievable, where each request includes identity of a block set a number of encoded data slices that are to be read from a storage unit. The method continues with the processing module sending the set of read requests to the storage units and decoding received encoded data slices to recover the data segment.Type: GrantFiled: November 20, 2014Date of Patent: January 24, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason K. Resch, Wesley Leggette
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Patent number: 9552262Abstract: The present invention provides a method, system and program product for deploying, allocating and providing backup for an autonomic sensor network ecosystem. Under the present invention, the autonomic sensor network ecosystem includes: (1) a set (e.g., one or more) of sensor networks for storing data components; (2) a set of sensor collector information gateways in communication with the sensor networks; and (3) a set of enterprise gateways and storage hubs (hereinafter enterprise gateways). Each sensor network includes a set of sensor peers and at least one super peer. The super peer manages the sensor network and communicates with the set of sensor collector information gateways. The autonomic sensor network ecosystem of the present invention is deployed and allocated in such a manner that backup and resiliency is provided.Type: GrantFiled: April 21, 2014Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Riz S. Amanuddin, Jonghae Kim, Moon J. Kim, Eric Yee
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Patent number: 9552263Abstract: A method for dynamically changing system recovery actions based on system load. The method includes measuring a value of a workload characteristic of a computer system over a period of time, detecting an error in the computer system, determining a workload level of the computer system, and selecting a set of error recovery actions in response to the system workload analysis module determining the workload level of the computer system. A workload characteristic defines a type of work performed by the computer system. A workload level can be based on user defined parameters or a measurement of the value of one or more workload characteristics.Type: GrantFiled: August 12, 2014Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Herve G. P. Andre, Mark E. Hack, Larry Juarez, Todd C. Sorenson
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Patent number: 9552264Abstract: Virtual Network Interface Connection (VNIC) is a client-server protocol that virtualizes access to a single physical Ethernet network adapter. “Dedicated VNIC” describes a configuration where a VNIC server is connected to a single VNIC client via a command/response queue (CRQ), allowing minimal overhead when communicating between the client and the Ethernet network adapter. A VNIC server failover mechanism includes multiple VNIC servers on a prioritized list. The top VNIC server on the prioritized list is selected to serve a VNIC client when a CRQ is opened by the client. When the selected VNIC server stops working, the VNIC server failover mechanism selects the next VNIC client in the prioritized list as the active VNIC server, and establishes a connection to the VNIC client's CRQ. In this manner, recovery of a failure in a VNIC server is done in a way that does not require any changes to the VNIC client.Type: GrantFiled: March 1, 2016Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Colin R. DeVilbiss, Charles S. Graham, Nicholas J. Rogness, Kristopher C. Whitney
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Patent number: 9552265Abstract: There is provided an information processing apparatus including a control unit. The control unit adds type information indicating a first type in a first operation request in which operation target storage devices are specified by unique identifiers, respectively, used in a first storage apparatus and outputs the first operation request to the first storage apparatus through the network. When the control unit transmits the first operation request to a second storage apparatus and receives an error response indicating a type error from the second storage apparatus after transparent failover is executed, the control unit adds type information indicating the second type in a second operation request in which operation target storage devices are specified by unique identifiers, respectively, used in the second storage apparatus and outputs the second operation request to the second storage apparatus through the network.Type: GrantFiled: March 17, 2015Date of Patent: January 24, 2017Assignee: FUJITSU LIMITEDInventors: Takumi Saito, Ryoko Masuda, Hajime Kondo, Shinichi Nishizono
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Patent number: 9552266Abstract: The invention provides, in one aspect, a digital data processor-based test data generator, that includes a digital data processing system with one or more digital data processors that are coupled for communications. A scenario creator executes on the digital data processing system and accepts, for each of one or more entities (“domains”), a plurality of parameters, including a hierarchical relationship between that entity and one or more other entities, a priority-of-test-data-creation relationship between that entity and one or more entities, and one or more attributes of that entity. The scenario creator generates a parameter set that defines a test data set specifying the aforesaid entities, relationships and attributes. The test generator further includes an engine that enumerates values for the entities and their attributes in an order determined by the aforesaid relationships.Type: GrantFiled: April 5, 2013Date of Patent: January 24, 2017Assignee: GenRocket, Inc.Inventors: Hycel B. Taylor, III, Gregg Bolinger
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Patent number: 9552267Abstract: Apparatuses, methods and storage medium associated with automatic SATA receiver equalization margin determination and setting, are disclosed. In embodiments, an apparatus may comprise a BIOS configured to determine, during POST, whether a device is attached to one of the SATA ports, and on determination that a device is attached to one of the SATA ports, further determine whether a receiver equalization margin has been set for the device. Additionally, the BIOS may be configured to perform a DTLE training to dynamically determine and set the receiver equalization margin for the device, on determination that a receiver equalization margin has not been set for the device. Other embodiments may be described and/or claimed.Type: GrantFiled: December 9, 2014Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Chee Keong Sim, Kai Chong Ng, Tze Ming Hau
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Patent number: 9552268Abstract: A testing device (10) comprises a storage unit (13), a display unit (11) and a control unit (12). The storage unit (13) is embodied to store messages of at least one test performed on at least one device under test. The control unit (12) is embodied to read in at least one part of the messages, to add them to a selection and to display at least an excerpt of the selection in a view on the display unit (11). The control unit (12) provides a zoom device (16), which, in the selection of messages, controlled by a user by means of an operating device (14), is configured to increase a number of contained messages in the case of a first user entry, and/or to reduce a number of contained messages in the case of a second user entry.Type: GrantFiled: June 11, 2013Date of Patent: January 24, 2017Assignee: ROHDE & SCHWARZ GMBH & CO. KGInventors: Daniela Raddino, Guido Lauerburg
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Patent number: 9552269Abstract: An apparatus that includes a serial interconnect is provided, wherein the serial interconnect includes test logic to send a number of reporting messages, wherein each reporting message is associated with a link sub-segment in a link in the serial interconnect, and each reporting message comprises a status region for the associated link sub-segment to report transmission errors. The test logic also includes analysis logic to record errors in the link sub-segment.Type: GrantFiled: December 23, 2014Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Debendra Das Sharma, Daniel S. Froelich
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Patent number: 9552270Abstract: A method for analyzing data is disclosed that includes receiving an analysis request to analyze selected data corresponding to one or more monitored assets, wherein the analysis request includes one or more parameters corresponding to performance categories of computing resources for processing the analysis request, the performance categories include at least one of a time for processing the analysis request or a cost for processing the analysis request; determining a computing resource allocation plan for processing the analysis request based on the one or more parameters; and processing the analysis request using the determined computing resource allocation plan to provide analysis results. Also disclosed is an analytic router that includes a mapper, an estimator, an optimizer, and a resource provisioner.Type: GrantFiled: September 10, 2014Date of Patent: January 24, 2017Assignee: General Electric CompanyInventors: Anil Varma, Nicholas Roddy, Feng Xue
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Patent number: 9552271Abstract: A system and method for enhanced dispatch of an operationally critical system is disclosed. The method receives a minimum equipment list associated with the system including a plurality of dispatch critical applications with at least one dispatch critical application instance. A rules set determines a plurality of schedules of the dispatch critical application instances in compliance with the minimum equipment list, each schedule associates a specific processing resource with a specific dispatch critical application instance. A monitor tracks the availability of each dispatch critical application instance and, should one or more instanced become unavailable, the method implements an alternate schedule of dispatch critical application instances in accordance with the rules set and the minimum equipment list.Type: GrantFiled: June 6, 2014Date of Patent: January 24, 2017Assignee: Rockwell Collins, Inc.Inventors: Jeffery E. Fetta, Eric N. Anderson
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Patent number: 9552272Abstract: A computing system intercepts a message generated by an application at runtime. The message has content to be logged in a log data store. The computing system identifies sensitive information in the message content and modifies the message content to protect the sensitive information. The computing system causes the modified message content to be logged in the log data store.Type: GrantFiled: July 29, 2011Date of Patent: January 24, 2017Assignee: Symantec CorporationInventors: Cheng-hsuan Liang, Xiaozhong Wang
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Patent number: 9552273Abstract: Methods and devices are provided for adapting an I/O pattern, with respect to a processing device using a non-volatile block storage device based on feedback from the non-volatile block storage device. The feedback may include information indicating a status of the non-volatile block storage device. In response to receiving the feedback, a storage subsystem, included in an operating system executing on processing device, may change a behavior with respect to the non-volatile block storage device in order to avoid, or reduce, a negative impact to the non-volatile block storage device or to enhance an aspect of the non-volatile block storage device. The feedback may include performance information and/or operating environmental information of the non-volatile block storage device. When the non-volatile block storage device is not capable of providing the feedback, the processing device may request information about the non-volatile block storage device from a database service.Type: GrantFiled: January 12, 2016Date of Patent: January 24, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Vladimir Sadovsky, Nathan Steven Obr, James C. Bovee, Robin A. Alexander
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Patent number: 9552274Abstract: Techniques are described for providing recommendations to enhance the logging code in a computer program. In particular, the methods described herein can identify source code locations which lack log printing statements or contain noisy log printing statements. The methods analyze static call graph of the source code, the corresponding commit and bug history, and propose recommendations to enhance logging. The logging behavior in methods whose log printing statements have been significantly modified can be considered to be ideal. The analysis discovers such methods and quantifies their logging behavior. It then compares this logging behavior with the logging behavior of highly critical and/or less critical methods to generate logging enhancement recommendations.Type: GrantFiled: August 13, 2014Date of Patent: January 24, 2017Assignee: VMware, Inc.Inventor: Vipin Balachandran
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Patent number: 9552275Abstract: Embodiments are directed towards mobile application development in a cloud-based architecture. Mobile applications may be designed to communicate with a cloud platform over a network. Mobile application developers may be enabled to submit cloud code to cloud platforms for use by mobile applications. If cloud code is provided to a cloud platform, the cloud platform may perform one or more actions to authenticate the cloud code, such as, ensuring that that the user providing the cloud code is authorized to provide the cloud code. If the cloud code is authenticated the cloud platform may perform one or more actions to validate the cloud code. If validated, the cloud code may be activated for use by mobile applications and/or mobile application developers. Activation of the cloud code may include associating the cloud code with one or more function calls and/or with one or more trigger points.Type: GrantFiled: October 8, 2015Date of Patent: January 24, 2017Assignee: PARSE INC.Inventors: Shyamsundar Jayaraman, Henele Litaka Adams, Bryan Jay Klimt, Jr., Kevin David Lacker, Charity Hope Majors, David Eitan Poll, Ilya Sukhar, James Jacob Yu
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Patent number: 9552276Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generated aggregated dependencies between software elements in a code base. One of the methods includes receiving a query that defines a dependency between the software elements in a project. Searching a database to identify matching source software elements having the one or more source attributes and target software elements having the one or more target attributes of the query. Identifying pairs of matching source software elements and matching target software elements having the specified relationship, and generating, for each pair of matching source software elements and matching target software elements having the specified relationship, a new dependency in a raw dependency graph, the new dependency being a dependency from a source software element of the pair to the target software element of the pair.Type: GrantFiled: March 17, 2016Date of Patent: January 24, 2017Assignee: Semmle LimitedInventors: Joshua George Hale, Luke James Cartey, Geoffrey White
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Patent number: 9552277Abstract: A synchronized JAVA debugger maintains synchronization between a JAVA source file in the debugger current working directory and a corresponding JAVA stored procedure in a database to be debugged. The debugger includes fetching module, storage module, display module, and execution module. The fetching module fetches a corresponding JAVA source file for a JAVA stored procedure from a database. The display module displays a recompile option, as a button, menu, or command line interface. In response to selection of the recompile option in the user interface, the execution module terminates the debugging session, sends a modified JAVA source file to the remote target JAVA Virtual Machine (JVM) and instructs the remote JVM to recompile the JAVA stored procedure using the modified JAVA source file before a new debugging session is started. Communication between the debugger and the remote database is by sending and receiving JAVA Debug Wire Protocol (JDWP) command packets.Type: GrantFiled: September 9, 2009Date of Patent: January 24, 2017Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Kiran Deshmukh, Nataraju Neeluru
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Patent number: 9552278Abstract: A method, computer program product, and system performing a method that include a processor defining a code fingerprint by obtaining parameters describing at least one of an event type or an event. The code fingerprint includes a first sequence. The processor loads the code fingerprint into a register accessible to the processor. Concurrent with executing a program, the processor obtains the code fingerprint from the register and identifies the code fingerprint in the program by comparing a second sequence in the program to the first sequence. Based on identifying the code fingerprint in the program, the processor alerts a runtime environment where the program is executing.Type: GrantFiled: January 4, 2016Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Giles R. Frazier, Michael K. Gschwind, Christian Jacobi, Chung-Lung K. Shum
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Patent number: 9552279Abstract: A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated digital signal processing device via a data bus network is described. The data bus network interface module being arranged to receive at least one data bus message from at least one remote network node via the data bus network, read an identifier field of the received at least one data bus message, and make data content of the received at least one data bus message available to at least one debug module if the identifier field comprises an identifier value defined for debug use.Type: GrantFiled: August 16, 2013Date of Patent: January 24, 2017Assignee: NXP USA, INC.Inventors: Mark Maiolani, Ray C. Marshall, Gary L. Miller
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Patent number: 9552280Abstract: Methods, systems, and computer-readable media to generate a user interface (UI) to analyze a complex event processing (CEP) query are disclosed. A particular method includes receiving data representing an event flow associated with execution of a CEP query. The CEP query includes a plurality of operators. A UI including a graph is generated. The graph includes a plurality of nodes. Each node of the graph corresponds to an operator of the CEP query, and each edge of the graph corresponds to a stream between operators of the CEP query. The method includes receiving an input identifying a particular node of the graph, where the particular node corresponds to a particular operator of the CEP query. In response to the input, an operator-specific output associated with at least one event processed by the particular operator is displayed.Type: GrantFiled: May 13, 2010Date of Patent: January 24, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Ramkumar Krishnan, Tihomir Tarnavski, Sebastien Peray, Ivo José Garcia dos Santos, Olivier Nano, Marcel Tilly
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Patent number: 9552281Abstract: Systems and methods are disclosed for integrating JAVA objects, such as handlers, into a scripting language to be used as part of a test automation environment including a test automation tool. The environment can access and execute one or more script files coded using diverse scripting languages designed to exercise and test DNS servers, registries, and/or other network entities. The test automation tool can invoke a set of generalized handlers that may comprise compiled JAVA objects configured to perform specific testing functions. The test automation tool may load a script for a test case and a scripting language, establish a controller, and interface the script to the intermediate JAVA handlers to abstract individual script files for use in a more universal fashion, avoiding incompatibilities that can arise between various script languages.Type: GrantFiled: December 21, 2012Date of Patent: January 24, 2017Assignee: VERISIGN, INC.Inventors: Jeffrey Trim, Hasani Jaali
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Patent number: 9552282Abstract: Module interrogation techniques are described in which modules configured to rely upon one or more operating system features are interrogated to determine which features are used and by which modules. A module is loaded that is configured to interact with a plurality of features provided by an operating system. Using one or more redirection techniques, calls made by the module to access features of the operating system are redirected to alternate functionality. Based on the redirection, data is generated to indicate the features of the operating system that are used by the module. The techniques may be performed for each of a plurality of modules to populate a database that relates features of the operating system to the plurality of modules.Type: GrantFiled: December 7, 2011Date of Patent: January 24, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Ashwin S. Needamangala, Mariyan D. Fransazov, John R. Ashmun, Kantcho I. Bogdev, Ying Deng
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Patent number: 9552283Abstract: Various systems and methods are disclosed for automatically generating a spreadsheet template to store information usable to generate one or more data transfer objects for input to a system under test. One such method involves identifying one or more properties of a data transfer object to be input to a software system under test. Identifying the properties of the data transfer object involves inspecting one or more structural requirements of a module within the software system under test that consumes that data transfer object. The method then automatically generates a spreadsheet template corresponding to the data transfer object, such that the spreadsheet template includes a respective column for each of the properties of the data transfer object. The spreadsheet template is configured to store information representing one or more versions of the data transfer object.Type: GrantFiled: November 12, 2008Date of Patent: January 24, 2017Assignee: CA, Inc.Inventor: John J. Michelsen
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Patent number: 9552284Abstract: A method to determine valid input sequences for an unknown binary program is provided. The method includes obtaining multiple input sequences, which each include two or more different inputs, for an unknown binary program. The inputs for the input sequences may be valid inputs for the unknown binary program. The method may further include executing an instrumented version of the unknown binary program separately for each input sequence. For each execution of the instrumented version of the unknown binary program, a set of execution traces may be generated by recording execution traces generated by the execution of the instrumented version of the unknown binary program. The method may further include comparing the sets of execution traces and determining which of the input sequences the unknown binary program accepts as valid based on the comparison of the sets of execution traces.Type: GrantFiled: May 15, 2015Date of Patent: January 24, 2017Assignee: FUJITSU LIMITEDInventors: Bogdan Copos, Praveen Murthy
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Patent number: 9552285Abstract: Micro-execution is the ability to run any code segment in isolation. Implementations for micro-execution of code segments are described. A test engine determines an effective address of a memory operation of an instruction of an executable program. The test engine determines, prior to performing the memory operation and based on a memory policy, that the effective address is to be replaced with a replacement address. Based on determining that the effective address is to be replaced, the test engine allocates the replacement address and executes the instruction based on the allocated replacement address.Type: GrantFiled: May 2, 2013Date of Patent: January 24, 2017Assignee: Microsoft Technology Licensing, LLCInventor: Patrice Godefroid
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Patent number: 9552286Abstract: The installation of multiple applications by an installer is executed in a mode that does not display an error message in a display device. Upon an installation performed by the installer ending, the result of the installation performed by the installer is determined. As a result of the determination, an installer that failed at the installation is caused to re-execute the installation of the application whose installation failed in a mode that displays an error message in the display device. As a result of the re-execution, an error message is displayed in the display device by the installer that failed at the installation.Type: GrantFiled: April 24, 2014Date of Patent: January 24, 2017Assignee: CANON KABUSHIKI KAISHAInventor: Yousuke Sugai
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Patent number: 9552287Abstract: A data management method, a memory controller and an embedded memory storage apparatus are provided. The embedded memory storage apparatus has a plurality of physical blocks and each of the physical blocks has fast physical pages and slow physical pages. The method includes detecting a status of a state indication unit. The method further includes automatically reading data stored in the embedded memory storage apparatus, using the fast and slow physical pages of the embedded memory storage apparatus to re-store the data and marking status of the state indication unit as a second status when the status of the state indication unit is a first status. Accordingly, the storage space of the embedded memory storage apparatus can be efficiently used.Type: GrantFiled: April 19, 2011Date of Patent: January 24, 2017Assignee: PHISON ELECTRONICS CORP.Inventors: Khein-Seng Pua, Jiunn-Yeong Yang, Kim-Hon Wong
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Patent number: 9552288Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a data object is stored in a first non-volatile tier of a multi-tier memory structure. A metadata unit is generated to describe the data object, the metadata unit having a selected granularity. The metadata unit is stored in a different, second non-volatile tier of the multi-tier memory structure responsive to the selected granularity.Type: GrantFiled: February 8, 2013Date of Patent: January 24, 2017Assignee: Seagate Technology LLCInventors: Ryan James Goss, Mark Allen Gaertner, Michael Joseph Steiner
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Patent number: 9552289Abstract: A logical address is received that references data stored at a physical address of a non-volatile memory. From the logical address, one or more words of a forward table in random access memory are received. The one or more words encompass the physical address. A bit address within the one or more words is also received. The bit address is not aligned with boundaries of the one or more words. The logical address is forward mapped to the physical address utilizing the one or more words and the bit address.Type: GrantFiled: November 25, 2014Date of Patent: January 24, 2017Assignee: SEAGATE TECHNOLOGY LLCInventor: Thomas V. Spencer
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Patent number: 9552290Abstract: An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of R-blocks. The controller is coupled to the non-volatile memory. The controller is configured to (i) write data using the R-blocks as a unit of allocation and (ii) perform recycling operations selectively on either an entire one of the R-blocks or a portion less than all of one of the R-blocks.Type: GrantFiled: January 22, 2015Date of Patent: January 24, 2017Assignee: Seagate Technology LLCInventors: Leonid Baryudin, Alex G. Tang, Earl T. Cohen
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Patent number: 9552291Abstract: A method for managing main memory including DRAM and NVRAM in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the DRAM, and loading predetermined read-only data and the like into the NVRAM; (b) in a state transition from a normal operation to a suspend state, moving data in the DRAM to the NVRAM; (c) in a state transition from the suspend state to the normal operation, reading data from the NVRAM for program execution; (d) in the case where a data write to the NVRAM occurs, stopping the data write, and moving data in a data area of the NVRAM subjected to the data write, to the DRAM; and (e) performing the data write to the DRAM to which the data has been moved.Type: GrantFiled: May 27, 2015Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Seiji Munetoh, Nobuyuki Ohba
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Patent number: 9552292Abstract: A storage management apparatus configured to allocate physical addresses in a physical storage area, to virtual addresses in a virtual storage area for storing data is provided. The storage management apparatus includes a processor that executes a process to define, in the physical area, a continuous area having a plurality of continuous physical addresses, and define, based on a virtual address to which a physical address in the continuous area has initially been allocated, an allocation range of virtual addresses for allocating the defined continuous area; and allocate a physical address in the defined continuous area to a virtual address in the defined relation range.Type: GrantFiled: May 21, 2015Date of Patent: January 24, 2017Assignee: FUJITSU LIMITEDInventors: Fumihiro Ooba, Shuko Yasumoto, Hisashi Osanai, Shunsuke Motoi, Daisuke Fujita, Tetsuya Nakashima, Eiji Hamamoto
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Patent number: 9552293Abstract: A method of managing processor caches. The method includes invalidating a cache line from a first instruction cache level and in response to invalidating the cache line from the first cache level, fetching data associated with the invalidated cache line from a third cache level or memory and writing the fetched data to a second cache level. The third cache level is larger or differently associative than the second cache level and the second cache level is larger or differently associative than the first cache level.Type: GrantFiled: August 6, 2012Date of Patent: January 24, 2017Assignee: Google Inc.Inventors: Benjamin Charles Serebrin, David Levinthal, Kevin D. Kissell, Clinton Wills Smullen, IV
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Patent number: 9552294Abstract: The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode. In these embodiments, when performing a write operation in the cache memory, the cache controller determines whether a region in the main memory where the cache block is from is configured in the write-back mode or the write-through mode and then performs a corresponding write operation in the cache memory.Type: GrantFiled: January 7, 2013Date of Patent: January 24, 2017Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Jaewoong Sim, Mithuna S. Thottethodi, Gabriel H. Loh
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Patent number: 9552295Abstract: Technologies are described herein for improving performance and energy efficiency in a computing system while using a large memory page size. Some example technologies may configure a main memory of the computing system to include a page-to-chunk table and a data area. The page-to-chunk table may include multiple entries such as a first entry. The first entry may correspond to a page that is made up of multiple chunks. The first entry may include pointers to the multiple chunks stored in the data area.Type: GrantFiled: September 25, 2012Date of Patent: January 24, 2017Assignee: Empire Technology Development LLCInventor: Yan Solihin
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Patent number: 9552296Abstract: A method, a system and a computer program product including instructions for verification of the integrity of a shared memory using in line coding is provided. It involves an active step wherein multiple bus masters write a corresponding data to a shared memory. After that it also includes a verification step where data entered in the shared memory by multiple bus masters is verified.Type: GrantFiled: March 15, 2013Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Duy Q Huynh, Lyndsi R McKinney
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Patent number: 9552297Abstract: A method for providing improved sequential read performance in a storage controller is provided. In response to the storage controller receiving a host read request from a host computer, the method includes identifying, by the storage controller, a largest burst length of a plurality of burst lengths in a memory of the storage controller, and determining a maximum number of consecutive times between bursts having a value less than a predetermined value. A burst includes a consecutive group of sequential host read requests from the same host computer. The method also includes multiplying the largest burst length of the plurality of burst lengths by the maximum number of consecutive times between bursts having a value less than the predetermined value to obtain an effective burst length and reading into a storage controller cache memory at least the effective burst length of data from storage devices coupled to the storage controller.Type: GrantFiled: July 29, 2013Date of Patent: January 24, 2017Assignee: Dot Hill Systems CorporationInventors: Zachary David Traut, Michael David Barrell
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Patent number: 9552298Abstract: Methods and systems configured to facilitate smart pre-fetching for sequentially accessing tree structures such as balanced trees (b-trees) are described herein. According to various described embodiments, a pre-fetch condition can be determined to have been met for a first cache associated with a first level of a tree such as a b-tree. A link to a bock of data to be read into the cache can be read into the cache by accessing a second level of the tree. The data elements associated with the retrieved link can subsequently read into the cache.Type: GrantFiled: December 27, 2013Date of Patent: January 24, 2017Assignee: Sybase, Inc.Inventors: Shailesh Mungikar, Blaine French
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Patent number: 9552299Abstract: Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory.Type: GrantFiled: June 10, 2011Date of Patent: January 24, 2017Assignee: California Institute of TechnologyInventor: Mark A. Stalzer
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Patent number: 9552300Abstract: A cache system for a storage device includes a solid state drive (SSD), a random access memory (RAM), and a cache control device. The cache control device is configured to: retrieve data from the storage device in response to a request to read data from the storage device, store at least some of the data in one or both of (i) the SSD and (ii) the RAM, when storing the at least some of the data to the RAM, write to the RAM non-sequentially with respect to a memory space of the RAM, and when storing the at least some of the data in the SSD, write to the SSD sequentially with respect to a memory space of the SSD. The cache control device comprises an SSD interface device configured to allocate memory for storing data in the SSD sequentially with respect to the memory space of the SSD.Type: GrantFiled: June 8, 2015Date of Patent: January 24, 2017Assignee: Marvell World Trade Ltd.Inventors: Shailesh Shiwalkar, Hy Dinh Vu, Jagadish K. Mukku, Sandeep Karmarkar, Anil Goyal
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Patent number: 9552301Abstract: A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line.Type: GrantFiled: July 15, 2013Date of Patent: January 24, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Zhe Wang, Junli Gu, Yi Xu
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Patent number: 9552302Abstract: To enable moving and copying structured data as block data at high speed, and tracing the moved or copied structured data at high speed. A data processing apparatus that processes structured data including a pointer includes a processing unit configured to process the structured data that uses as the pointer a relative address whose origin is the address of a word in which the pointer is stored.Type: GrantFiled: December 8, 2014Date of Patent: January 24, 2017Assignee: NEC CORPORATIONInventor: Yasushi Kanoh
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Patent number: 9552303Abstract: A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a transfer, from one processing unit to another, of data associated with more than one but less than all of the pages of shared memory.Type: GrantFiled: July 25, 2016Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Ravindra Babu Ganapathi, Hu Chen
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Patent number: 9552304Abstract: A computer-implemented method includes storing commands and maintaining an order of receipt of the commands in a command processing unit. The commands include address translation cache miss commands that are organized as one or more linked lists and stored in a content-addressable memory (CAM). All nodes within a single linked list include commands having addresses that map to the same hash value. Based on receiving a memory fetch completion indicator for a cache entry for a command in a head node in a linked list, all of the commands in the linked list are returned. The returning includes sending the commands in the linked list to an address translation unit in an order specified by the linked list.Type: GrantFiled: August 24, 2015Date of Patent: January 24, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Kauer, Lonny J. Lambrecht, Daniel Ramirez, Zelun Tie
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Patent number: 9552305Abstract: A method begins by a processing module identifying a first storage space zone that includes a plurality of deleted encoded data slices and a plurality of active encoded data slices. The method continues with the processing module determining to compact the first storage space zone based on a function of the plurality of deleted encoded data slices and the plurality of active encoded data slices. The method continues with the processing module retrieving the plurality of active encoded data slices from the first storage space zone, identifying a second storage space zone, storing the plurality of active encoded data slices in the second storage space zone, and erasing the plurality of deleted encoded data slices and the plurality of active encoded data slices from the first storage space zone when the first storage space zone is to be compacted.Type: GrantFiled: October 11, 2011Date of Patent: January 24, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ilya Volvovski, Jason K. Resch, Andrew Baptist, Greg Dhuse