Abstract: Embodiments provide, among other things, a circuit including a frequency generator and a charge pump. In embodiments, the frequency generator may be configured to provide the charge pump with a clock signal at a first frequency for a predefined period of time. Thereafter, the frequency generator may provide the charge pump with a clock signal at one or more other frequencies. In embodiments, the first frequency may enable the charge pump to settle in a reduced period of time when compared with the one or more other frequencies.

Abstract: A frequency multiplier includes an input terminal, an output terminal, a first transistor having a first gate to which a radiofrequency signal is input from the input terminal, a first drain from which an output signal is issued to the output terminal, and a first source, a second transistor having a second gate, a second source to which the radiofrequency signal is input from the input terminal, and a second drain from which an output signal is issued to the output terminal, and a stabilizing resistor which is a resistor connected to the second gate, wherein no resistor exists on the path for the radiofrequency signal, and wherein the stabilizing resistor suppresses a reflex gain produced by the second transistor.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

Abstract: An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter. The fractional output divider utilizes the filtered output signal to establish a value to divide the reference signal by to obtain a clean output clock signal. The clean output clock signal is fed back to the signal comparator and is used as the correction signal.

Abstract: A method and apparatus for mitigating offsets in an interpolator are disclosed. In the method and apparatus, a first number of clock cycles of a first clock signal observed over a first clock cycle of a second clock signal is determined and then stored. Also a second number of clock cycles of the first clock signal observed over a second clock cycle of the second clock signal subsequent to the first clock cycle is determined and stored. The first number of clock cycles and the second number of clock cycles are compared to determine whether they are different from each other. If they are different from each other, a reset signal is asserted under control of the second clock signal to reset at least one of a derivator stage and an integrator stage of an interpolator.

Abstract: A self clocking comparator for clocking a charge pump providing a high voltage output including multiple gain stages and a reset circuit. The gain stages are configured to assert the compare voltage at a first voltage level in a default state when the sense voltage is greater than the reference voltage, and to assert the compare voltage to a second voltage level in a reset state when the sense voltage falls below the reference voltage. The reset circuit resets, or otherwise forces, the gain stages back to the default state in response to the compare voltage transitioning to the second voltage level. The compare voltage oscillates while the sense voltage is less than the reference voltage at a frequency based on a magnitude of a difference between the sense voltage and the reference voltage up to a predetermined maximum frequency level.

Abstract: A method and apparatus are provided. The apparatus may be a capacitive element for adjusting a net capacitance of a circuit. The apparatus may be configured to be coupled to the circuit. The apparatus may be configured to adjust the net capacitance of the circuit to decouple common mode and differential loop bandwidth adjustment of the circuit. The capacitive element may include a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit, and a pair of negative gain buffers coupled to respective capacitors.

Abstract: A solid state power controller including: a plurality of pairs of FETs connected in parallel, each pair comprising a first, forward-facing FET and a second, backward-facing FET connected by their respective sources; gate drive means for switching said FETs on and off; and means for isolating the sources of the backwards-facing FETs of the plurality of pairs of FETs from each other and operating the backwards-facing FETs in 3rd quadrant operation mode.

Abstract: Two or more pads and are connected to a gate region, so that a pad for applying a gate voltage can be selected. In the case where, for example, the peripheral region is likely to overheat, a turn-on voltage is applied to the first pad to turn on the peripheral region later than the central region, and a turn-off voltage is applied to the second pad to turn off the peripheral region earlier than the central region. The problem that the peripheral region is likely to overheat can be addressed. In the case where the flow of an excess current raises the temperature, the turn-off voltage is applied to the second pad. The problem that the temperature is likely to rise in the peripheral region when an excess current flows can be addressed.

Abstract: A driving circuit for an IGBT module is provided. The driving circuit includes: a gate driving resistor connected with the IGBT module; a driving module connected with the gate driving resistor; an integrating circuit connected with the driving module, in which the integrating circuit comprises an equivalent resistor and a first capacitor connected in series with the equivalent resistor, and a time constant of the integrating circuit is adjusted by changing a resistance of the equivalent resistor; a first optical coupler connected with the integrating circuit; and a micro control unit, connected with the first optical coupler. The disclosed driving circuit for an IGBT module can adjust an equivalent resistance of the gate driving resistor, thus driving the IGBT module working at different powers without replacing the gate driving resistor, and improving an operation state of the IGBT module.

Abstract: The present invention provides a GOA circuit based on LTPS semiconductor TFT, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part (100), a pull-up part (200), a first pull-down part (400) and a pull-down holding part (500); the pull-down holding part (500) utilizes a high/low voltage reverse design and comprises a first, a second and a third DC constant low voltage levels (VSS1, VSS2, VSS3) which are sequentially abated and a DC constant high voltage level (H), the influence of electrical property of the LTPS semiconductor TFT to the GOA driving circuit, and particularly the bad function due to the electric leakage issue can be solved; meanwhile, the existing issue that the second node voltage level the pull-down holding circuit part in the GOA circuit based on the LTPS semiconductor TFT cannot be at higher voltage level in the functioning period can be solved to effectively maintain the first node (Q(N)) a

Abstract: Systems, methods, and devices to control a transistor to maintain one or more substantially constant characteristics while activated or deactivated are provided. One such system includes a transistor that receives an activation signal on a gate terminal to become activated during a first period and receives a deactivation signal on the gate terminal to become deactivated during a second period. The transistor receives an input signal on an input terminal during the first period and the second period. The input signal varies during the first period and during the second period. The transistor may have improved reliability (e.g., substantially constant on resistance RON) because a first difference between the input signal and the activation signal substantially does not vary during the first period and a second difference between the input signal and the deactivation signal substantially does not vary during the second period.

Abstract: An optical keypad for use in hazardous areas and which can ensure safe and reliable detection of keystrokes through an at least 8 mm thick glass window, as is required for electronics equipment located in hazardous explosive areas (In accordance with ATEX Directive 94/9/EC and similar requirements) is obtained by providing a system in which at least 6 LEDs are lit in a pseudo-random sequence, modulated by a pseudo-random frequency and the interval between the lighting of each of the LEDs is change randomly to avoid interference between collocated keypads and light from other sources, such as daylight and artificial light.

Abstract: A fabric product includes a body having a skin made by interweaving a plurality of textile fabrics and a low powered activation arrangement which includes an electronic unit and one or more conductive threads extended underneath the skin of the body. The electronic unit includes a power source, an activation circuit which is a low powered activation circuit, and an operator. Each of the conductive threads has a proximal end portion electrically coupled with the activation circuit and a distal end portion which is extended to an outer surface of the skin of the body at a predetermined location thereof and is arranged in such a manner that when the distal end portion of the conductive thread is being contacted, the activation circuit is activated to actuate the operator.

Abstract: A multi-module integrated circuit (IC) can be configured in different types of packages having different modules enabled or disabled. A module that can be disabled has driven circuitry that is known a priori to have a low-power input vector that places the driven circuitry into a low leakage power state. The module also has driving circuitry with one or more package-aware cells. The IC has a package-aware controller that generates control signals for the package-aware cells that ensure that the outputs from the package-aware cells are forced to particular values (i.e., either logical-0 or logical-1) that cause the low power input vector to be applied to the driven circuitry when the IC is assembled in a package in which the module is disabled. In this way, module leakage power is reduced for package types in which certain modules are disabled.

Abstract: A physical unclonable function (PUF) having magnetic and non-magnetic particles is disclosed. Measuring both magnetic field and image view makes the PUF difficult to counterfeit. PUF may be incorporated into a user-replaceable supply item for an imaging device. A PUF reader may be incorporated into an imaging device to read the PUF. Other systems are disclosed.

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed, a semiconductor device includes a first conductive layer over an insulating layer, a semiconductor layer over the first conductive layer, a second conductive layer over the semiconductor layer, a gate insulating layer over the second conductive layer, and a gate electrode over the gate insulating layer. The semiconductor device may further include wiring layers. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width, and may be 1×10?17 A or less per micrometer. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Abstract: A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.

Abstract: A Field-Programmable Gate Array device is provided with programmable interconnect points in the form of interconnect circuits comprising one or more pass transistors, wherein at least some components of the interconnect circuits are implemented in the Back-End-Of-Line part of the Field-Programmable Gate Array device's production process. The memory element in an interconnect point is not produced as a Static Random Access Memory cell, but as a Dynamic Random Access Memory cell, requiring only a single select transistor and a storage capacitor for each memory element. The fabrication of at least the select transistor and the pass transistor involves the use of a thin film semiconductor layer, e.g., Indium Gallium Zinc Oxide, enabling production of transistors with low leakage in the Back-End-Of-Line.

Abstract: A data output circuit of a semiconductor apparatus includes a pull-up driver including a first plurality of leg units commonly electrically coupled to a data output pad and configured to pull up the data output pad in response to a first code signals, a pull-down driver including a second plurality of leg units commonly electrically coupled to the data output pad and configured to pull down the data output pad to a second code signals, and a code generator configured to generate the first and second code signals. The code generator generates the second code signals by comparing a replica voltage to a reference voltage.

Abstract: Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.

Abstract: A programmable integrated circuit device includes a plurality of clusters of programmable logic resources. Programmable device interconnect resources allow user-defined interconnection between the clusters of programmable logic resources. A plurality of specialized processing blocks have dedicated arithmetic operators and programmable internal interconnect resources, and having inputs and outputs programmably connectable to the programmable device interconnect resources. A plurality of dedicated memory modules have inputs and outputs programmably connectable to the programmable device interconnect resources. Programmably connectable direct interconnect between at least one respective individual one of the specialized processing blocks and at least one respective individual one of the dedicated memory modules allow the formation of a processor element from a specialized processing block and a memory module.

Abstract: Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.

Abstract: A circuit for generating a divided clock signal with a configurable phase offset comprises a first latch circuit adapted to receive a clock signal to be divided; a second latch coupled to an output of the first latch circuit and generating a divided output clock signal; and an initialization circuit coupled to the first latch circuit and the second latch circuit, the initialization circuit coupled to receive an initialization signal. The initialization signal determines a phase offset between the divided output clock signal and the clock signal to be divided. A method of generating a divided clock signal is also described.

Abstract: A control method for a delay locked loop includes: delaying an input signal to generate an internal signal; delaying the internal signal to generate an output signal; and selectively providing a reference clock signal or the output signal as the input signal according to the output signal and the internal signal.

Abstract: A DLL includes a phase detector, a counter, a delay circuit, and a false-lock detection and recovery circuit. The false-lock detection and recovery circuit checks whether the DLL is in a true-lock condition or not, based on an average of a phase difference between a clock signal and an intermediate clock signal. The intermediate clock signal is generated by the delay circuit based on a count value generated by the counter and a select signal generated by the false-lock detection and recovery circuit. The false-lock detection and recovery circuit generates and provides a control signal to the counter. Based on the control signal, the counter modifies the count on which a delay between the clock signal and an output signal of the DLL depends when the DLL is not in the true-lock condition.

Abstract: In a clock generating circuit, a variable frequency division circuit generates a variable divided clock by dividing a source clock in accordance with a division ratio setting signal. A first clock synchronization circuit generates a first delayed clock that is delayed by a maximum number of clocks from the variable divided clock in synchronization with the source clock and supplies the first delayed clock to a control circuit. One or more second clock synchronization circuits generate one or more second delayed clocks, each of which is delayed by the maximum number of clocks from the variable divided clock in synchronization with the source clock, and supply each of the one or more second delayed clocks to each of one or more functional modules.

Abstract: A frequency synthesizer and a method for frequency synthesis are provided. The frequency synthesizer includes a subband phase-locked loop (PLL) and a main PLL. A divisor of an adjustable non-integer frequency divider in the subband PLL is adjusted, and a channel frequency of a maximum frequency band of all frequency bands is output. A divisor of an adjustable integer frequency divider in the main PLL is adjusted, and a center frequency required for each frequency band of the all frequency bands is output. The center frequency and the channel frequency are mixed by a mixer to produce a band frequency. A quantization noise generated by the adjustable non-integer frequency divider is filtered out by the subband PLL to reduce the impact of the quantization noise on the main PLL.

Abstract: Various embodiments improve accuracy by increasing the number of atoms engaged in a clock transitions in an optical lattice clock. An exemplary optical lattice clock an embodiment comprises an optical waveguide, an optical path, a laser light source, and a laser cooler. The optical path has a hollow pathway that extends from a first end to a second end while being surrounded with a tubular wall, which is used as a waveguide path. The optical path passes between mirrors and through the pathway. The laser light source supplies to the optical path a pair of lattice lasers (L1 and L2) propagating in opposite directions with each other. The laser cooler supplies cooled atoms that have two levels of electronic states associated with a clock transition to the vicinity of the first end of the optical waveguide.

Abstract: A time-interleaved analog-to-digital converter that samples an analog input signal at a sampling frequency and converts the analog input signal into a digital output signal is enabled to perform correction processing on an error by: converting the analog input signal into the digital output signal by a plurality of analog-to-digital conversion circuits in a time-interleaved manner; and performing gain correction processing and skew correction processing with respect to the analog-to-digital conversion circuit, on the basis of a mixed signal, the mixed signal being obtained by mixing an output signal from the analog-to-digital conversion circuit with a signal made by shifting a phase of the output signal by ?/2.

Abstract: In an example, a successive approximation register analog-to-digital converter includes a switched capacitor digital-to-analog converter (DAC) first array to sample an input signal and to convert a sample of the input signal to a digital value represented by a plurality of bits, the first array including a first group of capacitors representing at least some of the plurality of bits, a switched capacitor DAC second array including a second group of capacitors representing at least some of the plurality of bits, wherein at least one bit of the plurality of bits represented by the second group of capacitors is represented by at least two capacitors, and wherein each of the two capacitors is configured to be selectively connected to a selected one of at least two reference potentials such that the at least one bit represented by the second group of capacitors is switchable between at least three states.

Abstract: The present disclosure provides a system, circuit, and method for correcting clock skew in time-interleaved analog-to-digital converters. At least two clock signals are received along respective channels. A delay of a first channel, carrying a first clock signal, is accounted for by applying one or more first adjustment factors to the channels until an edge of the first clock signal is aligned with a transition point of a reference signal. The first clock signal is swapped to the second channel, and vice-versa. A value of the reference signal as sampled by the first clock signal is compared to values of the reference signal as sampled by the second clock signal to determine a skew of the second channel vis-à-vis the first channel, and one or more second adjustment factors are applied to the second channel based on the determined skew of the second channel.

Abstract: An electrical signal is processed by digitizing the electrical signal to produce a stream of digitized data in the time domain, wherein the stream has an original frequency spectrum, transmitting the stream to N signal paths (N>1), and down-converting and filtering the stream in each of the N signal paths to produce N streams of digitized data in the time domain, wherein the N streams have N frequency spectra, respectively, and the N frequency spectra cover N different portions of the original frequency spectrum, respectively.

Abstract: Methods and apparatuses are described to convert analog signals to digital signals using a local charge averaging capacitor array (LCACA) in an analog-to-digital converter (ADC.) An apparatus includes a comparator. The comparator is configured with a first high input, a first low input, and is configure to receive a clock signal. A logic/latch block is configured to receive the clock signal and an output from the comparator. The logic/latch block is configured to output a control signal and a digital N-bit output signal. A local charge-averaging capacitor array (LCACA) is configured to receive the control signal and a reference voltage. An output of the LCACA is coupled to the first low input. The first LCACA is divided into a high sub-array and a low sub-array. The high sub-array is pre-charged to a high reference voltage and the low sub-array is pre-charged to a low reference voltage. The high reference voltage is greater than the low reference voltage.

Abstract: An R-2R ladder resistor circuit including: plural first resistance elements, one end of each being connected to an input terminal; plural second resistance elements, one end of each being connected to a reference potential; plural third resistance elements, one end of each being connected to an output terminal; and plural switching connection sections that are each in correspondence relationships with the first resistance elements, the second resistance elements, and the third resistance elements, and that connect the input terminal and the output terminal according to a bit signal, wherein, according to the bit signal, each switching connection section switchably connects another end of the third resistance element to another end of the first resistance element or to another end of the second resistance element, among the first resistance element, the second resistance element, and the third resistance element corresponding thereto.

Abstract: In order to improve the compression rate for configuration information including address information and data information when transmitting or storing configuration information which includes addresses and data having differing characteristics, an information compression device is provided with a compressor which receives as input and compresses the configuration information provided with the addresses and data, and a compressed information storage module for storing the configuration information which is compressed, that is, compressed configuration information, as the information to be decompressed for the user, said compressor including an information separating module for separating the configuration information into address information and data information, an address compressor and data compressor which separately compress the separated address information and data information, and a compressed information outputting module for combining the compressed address information and data information and output

Abstract: A source data set is processed to produce a symbol table and a distribution without using a tree construct or any tree-related processing. The symbol table and the distribution outputted for encoding the data set and decoding encoded versions of the data set.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes a segmenter configured to segment Layer 1 (L1) signaling; and an encoder configured to perform Low-Density Parity Check (LDPC) encoding with respect to each of the segmented L1 signalings, and the encoder punctures parity bits from LDPC parity bits added by the LDPC encoding as many as bits of a predetermined group unit.

Abstract: A data storage device includes a nonvolatile memory and a controller having a decoder. The nonvolatile memory is operatively coupled to the controller. The nonvolatile memory is configured to store a set of bits. The decoder is configured to receive the set of bits from the memory. The decoder is further configured to perform a decoding operation using the set of bits based on a parity check matrix. The parity check matrix includes a block row. The block row has a first non-zero sub-matrix and a second non-zero sub-matrix that is separated from the first non-zero sub-matrix within the block row by at least a threshold number of null sub-matrices of the block row.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

Abstract: A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings.

Abstract: A method for Error Correction Code (ECC) encoding includes receiving data to be encoded. The data is encoded to produce a composite code word that includes multiple component code words. Each component code word in at least a subset of the component code words is encoded in accordance with a respective component code and has at least one respective bit in common with each of the other component code words.

Abstract: An apparatus having a memory and a controller is disclosed. The memory is configured to store a codeword. The controller is configured to (i) determine one or more least-reliable bit positions in a soft-decision version of the codeword in response to failing to decode a hard-decision version of the codeword, (ii) generate a trial codeword by selecting at random a respective value in one or more trial positions among the least-reliable bit positions in the hard-decision codeword and (iii) perform a hard-decision decoding of the trial codeword.

Abstract: Provided are a transmitter for processing an L1 signaling including an L1-pre signaling and an L1-post signaling, a receiver of the L1 signaling, and methods of controlling the transmitter and the receiver. The transmitter includes: an encoder configured to perform Bose, Chaudhuri, Hocquenghem (BCH) encoding and Low Density Parity Check (LDPC) encoding with respect to the L1-post signaling, and a puncturing unit configured to puncture at least a part of LDPC parity bits constituting an LDPC codeword generated by the LDPC encoding of the L1-post signaling, wherein the number of bits to be punctured is calculated based on the number of bits available for transmission of the LDPC codeword and a modulation order of the L1-post signaling.

Abstract: Provided is a technique capable of improving isolation characteristics between a plurality of signal paths through which RF signals pass, without using ground electrodes or the like. Wiring electrodes 10a and 20a through which RF signals do not pass simultaneously are formed so as to be adjacent to each other in a central region of a component mounting surface 2a of a circuit board 2, and wiring electrodes 11a and 21a through which RF signals pass simultaneously are formed so as to be distanced from transmission paths 10 and 20. Accordingly, the RF signals do not simultaneously pass through the transmission paths 10 and 20, which are disposed near each other, and thus there is no risk that the RF signal passing through one of the signal paths will interfere with the RF signal passing through the other signal path.

Abstract: A single hybrid receiver is provided for processing both single carrier and carrier aggregated (CA) communications signals where carriers are split into independent receive paths without any additional external components. The receiver receives all contiguous and non-contiguous intra-band CA and inter-band CA signals, including those of unequal bandwidths, allowing for improved rejection and balanced rejection of jamming signals on either side of the two carrier signals.

Abstract: An electromagnetic Extremely High Frequency (EHF) communication chip includes one or more local oscillator circuits, a transducer circuit and at least one of a modulator or a demodulator coupled to the transducer circuit. Each of the local oscillator circuits may have a local oscillator and configured collectively to generate first and second carrier signals having respective first and second EHF frequencies. The first EHF frequency may be different than the second EHF frequency. The transducer circuit may have a first transducer for transmitting and receiving EHF communication signals. The modulator may be coupled to the local oscillator circuits for modulating the first carrier signal or the second carrier signal with a first transmit base data signal. The demodulator may be for demodulating the first carrier signal or the second carrier signal to produce a first receive base data signal.

Abstract: Provided herein are apparatus and methods for reconfigurable directional couplers in an RF transceiver. Reconfigurable directional couplers can be reconfigured and designed to provide high directivity using configurable capacitors to effect a mutual coupling and using lumped components or delay lines to effect a phase shift. Depending on the embodiment, the reconfigurable directional coupler can include capacitors, inductors, and switching components. The coupler can be designed for multi-band operation with an adjustable coupling factor conducive to semiconductor process integration. The coupler can have configurable coupling capacitors and phase shifters.