Abstract: An information processing method is provided, which is applied to an electronic device. The electronic device includes a main body, a display unit and a projection unit. The method includes: obtaining trigger information for instructing the electronic device to switch from a first state to a second state; controlling the electronic device to switch from the first state to the second state in response to the trigger information; obtaining at least one parameter information; determining whether to enable the projection unit based on the at least one parameter information; and controlling the projection unit to be in the enabled state, in a case that it is determined to enable the projection unit based on the at least one parameter information.

Abstract: A system is described for maintaining synchrony of operations among a plurality of devices that have independent clocking arrangements. The system includes a task distribution device that distributes tasks to a synchrony group comprising a plurality of devices that are to perform the tasks distributed by the task distribution device in synchrony. The task distribution device distributes each task to the members of the synchrony group over a network. Each task is associated with a time stamp that indicates a time, relative to a clock maintained by the task distribution device, at which the members of the synchrony group are to execute the task.

Abstract: When using finite-state devices to perform various functions, it is beneficial to use finite state devices representing regular grammars with terminals having markup-language-based semantics. By using markup-language-based symbols in the finite state devices, it is possible to generate valid markup-language expressions by concatenating the symbols representing the result of the performed function. The markup-language expression can be used by other applications and/or devices. Finite-state devices are used to convert strings of words and gestures into valid markup-language, for example, XML, expressions that can be used, for example, to provide an application program interface to underlying system applications.

Abstract: The present invention discloses a gate driving circuit and a display device having the same. The gate driving circuit includes a logic circuit, a plurality of shift register units and enable circuits. The logic circuit is configured to receive a first clock signal, a second clock signal, a third clock signal, and a fourth signal, and output a logic pulse signal for driving the plurality of shift register units and enable circuits. Each of the plurality of enable circuits is connected with one of the plurality of shift register units and configured to receive a first pulse signal outputted by one of the plurality of shift register units and the logic pulse signal outputted by the logic circuit, and output two second pulse signals to drive two respective gate lines.

Abstract: A disk drive is disclosed comprising a head actuated over a disk comprising a plurality of tracks, each track comprising a plurality of data sectors. A circular buffer is defined comprising a plurality of the tracks. During a garbage collection operation, write data is read from previously written valid data sectors corresponding to a tail of the circular buffer and stored in a non-volatile cache. During a flush operation, the write data is flushed from the non-volatile cache to the disk.

Abstract: A two wire interface is disclosed that serializes messaging signals and GPIO signals into frames transmitted over a transmit pin. The two wire interface is configured to perform flow control by monitoring a voltage for the transmit pin.

Abstract: In an embodiment, a method of compiling a pattern into a non-deterministic finite automata (NFA) graph includes examining the pattern for a plurality of elements and a plurality of node types. Each node type can correspond with an element. Each element of the pattern can be matched at least zero times. The method further includes generating a plurality of nodes of the NFA graph. Each of the plurality of nodes can be configured to match for one of the plurality of elements. The node can indicate the next node address in the NFA graph, a count value, and/or node type corresponding to the element. The node can also indicate the element representing a character, character class or string. The character can also be a value or a letter.

Abstract: A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.

Abstract: An extensible iterative multiplier design is provided. Embodiments provide cascaded 8-bit multipliers for simplifying the performance of multi-byte multiplications. Booth encoding is performed in the lowest order multiplier, with the result of the Booth encoding then provided to higher order multipliers. Additionally, multiply-add operations can be performed by initializing a partial product sum register. Configurable connections between the multipliers facilitate a variety of possible multiplication options, including the possibility of varying the width of the operands.

Abstract: A method and apparatus for additive range reduction are disclosed. A constant may be pre-stored in a look-up table (LUT), and at least one section of the constant may be retrieved from the LUT for generating a product of an input argument and the constant such that a precision of the product may be controlled in any granularity. For a trigonometric function, 2/? is stored in the LUT, and at least one section of 2/? may be retrieved from the LUT. The argument is multiplied with the retrieved sections of 2/?. The retrieved sections are determined to correctly generate the two least significant bits (LSBs) of an integer portion and a scalable number of most significant bits of the multiplication result. An output of the trigonometric function is generated for the argument with a fractional portion of the multiplication result based on two LSBs of the integer portion of the multiplication result.

Abstract: A random number generating device of the present disclosure includes: an arithmetic random number generator that generates an arithmetic random number sequence; an arithmetic random number converter that sequentially reads at least one arithmetic random number from the arithmetic random number sequence and converts a value of the read arithmetic random number into a voltage or current value of at least two predetermined levels of gray scale having an identical polarity; a hysteresis unit that outputs values depending on a presently-input voltage or current value and a previously-input voltage or current value with respect to the sequentially-input voltage or current value; and a threshold processor that binarizes the output of the hysteresis unit.

Abstract: A set of characteristics is received in response to a questionnaire. Using the characteristics, various tasks are identified as requiring or not requiring user input because of the applicability to the customer. An associated task owner is determined for a subset of tasks. In response to receiving a selection of a selectable dependency indication associated with a first task, displaying task dependency data associated with the first task is displayed, the task dependency data including a set of tasks on which the first task depends for completion, a set of tasks that depend on the first task for completion, and for each of these dependent tasks, an associated task owner and a task status. A task list that indicates tasks needing to be completed is presented to the user. Software is installed according to the task list.

Abstract: For each of a plurality of different tenants configured to concurrently execute in a virtual environment, a respective class loader graph can be constructed. For each respective class loader graph, unique types of edges between nodes that affect class loading can be identified. The edges can be traversed. Based on traversing the edges of the class loader graph, a respective unique dependency identifier (UDI) can be assigned to each class loader request. Class loader requests that are assigned the same UDI can be identified in at least two of the tenants. Responsive to identifying the class loader requests that are assigned the same UDI, a shared class loader can be assigned to each of the class loader requests. Each respective class loader request that is assigned the same UDI can be configured to call the shared class loader to load at least one class required by the respective tenant.

Abstract: A device may identify a function identifier input into a programming environment, and may determine an input argument associated with the function, based on the function identifier. The device may provide a user interface that depicts a representation of the input argument, and may provide, via the user interface, an input mechanism to be used to receive a value of the input argument. The device may receive, based on an interaction with the input mechanism, a value of the input argument. The device may provide information that indicates an association between the value and the input argument, based on receiving the value of the input argument.

Abstract: A computer implemented modeling method and system that includes using a visual programming language to create a topological framework model configured to spatially arrange a set of one more agent submodels and incorporate an environmental submodel for each position of the topological framework model. The method further includes capturing the topological framework model by converting elements of the visual programming language into a textual programming language.

Abstract: In an embodiment, a technique for generating a comment for an entity associated with a model. The comment may be generated based on at least (1) a structural usage of the entity and (2) a dynamically-specified rule that is associated with the structural usage of the entity. The rule may be used to control content of the comment. The comment may be incorporated in generated code for the model and the generated code including the comment may be outputted (e.g., displayed, stored).

Abstract: The present invention generally relates to systems and methods for executing scripts (a sequence of declarative operations) on large data sets. Some implementations store descriptions of previously-executed operations and associated input and output data sets. When executing similar operations on the same, a subset of, a superset of, or any fragment of data subsequently, some implementations detect duplication of operations and access previously-stored output data sets in order to re-use data and reduce the amount of execution, thus avoiding time-consuming duplicative computations.

Abstract: An architecture for altering the content of a menuing system with little or no change to existing firmware of an electronic device is disclosed. A menu text file is generated and the menu text file is compiled into source code. Menu firmware is compiled and liked using the source code into a downloadable binary for the electronic device. The downloadable binary does not alter existing firmware of the electronic device.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for flow analysis. In one aspect, a method includes modifying a dataflow graph, the dataflow graph including a plurality of paths connecting at least one entry point and at least one exit point, including adding components to the dataflow graph that add flow units to data records and remove flow units from data records, each flow unit identifying a segment of a path traversed by the data record. The method also includes identifying execution paths based on flow units obtained by processing a plurality of data records using the modified dataflow graph. The method also includes determining a subset of the plurality of data records, wherein a selected set of execution paths are represented by the subset.

Abstract: Statically extensible types allow a static type system to model the behavior of dynamic object model extension in dynamic runtime systems. Static types that model dynamically extended types can be extended using additional declarations in the same compilation. Declarations for a particular type can come from multiple independent sources which can have been defined at multiple points in time. Extension declarations can use the same syntax as the initial type declaration. Hence presence of one or more declarations for the same type in a compilation can indicate that the type has been extended. These features allow static type checking of dynamic plug-ins to be supported using statically extensible types. Declarations and extension declarations for a type can be merged together to create an extended type that enables different processing paths and dependencies.

Abstract: Technology is disclosed for providing configurable synchronization mechanisms for automatic synchronization of application states across multiple devices using cloud storage. In accordance with the techniques introduced here, a method includes steps of receiving a request for supplemental application synchronization information associated with a first application on a first remote computing device. In response the request for the supplemental application synchronization information, application-specific configuration information is determined for synchronizing a state of the first application to a cloud-based storage service. The supplemental application synchronization information including the application-specific configuration information is then provided to the first remote computing device for facilitating synchronization of the state of the first application to the cloud-based storage service.

Abstract: The invention generally relates to the delivery of content to devices of disparate platforms in executable format. The invention provides a way to create and deliver content and functionality to a number of different electronic devices having different platforms. In certain aspects, the invention provides an apparatus configured to receive a client application and a content application including functionality.

Abstract: Users design and develop a current version of an application to be rendered on different devices. The application is configured and deployed with its current version on a platform server. The application can run on different servers provided from different platforms. A desktop browser displays the current version of the application by loading a Uniform Resource Locator (URL). The current version of the application can be tested both on a desktop browser and on a browser, installed on a remote device. Additionally, a visually encoded dynamic code is generated that is scanned by a remote device to launch the deployed version of the application. The visually encoded dynamic code encrypts dynamic information for locating the deployed application that is dependent on the platform server used for deployment. After displaying the current version on the remote device, further points for improvement of the design and functionality of the application are defined.

Abstract: An information processing apparatus having a safe mode for operation restricting a function of a bundle more than in a normal operation mode, comprises: an installation unit that installs a host bundle, and inactivates, as a temporary install, a fragment bundle added to the host bundle in order to extend a function of the host bundle, and stores the fragment bundle in a first memory area; and a holding unit that holds a list defining whether the temporarily installed fragment bundle is activated or inactivated when the information processing apparatus starts in the safe mode, wherein the installation unit, when the information processing apparatus starts in the safe mode, moves a fragment bundle defined to be activated in the list, out of temporarily installed fragment bundles, to a second memory area to activate that fragment bundle.

Abstract: The present invention provides a common framework to determine if machines are patched and automatically applies patches as required. It provides an automated tool to assess patch levels and apply patches on several different UNIX machine types. Further, it provides a centralized, consistent method of providing patches to multiple roles within an organization while automatically managing large quantities of machines. It can manage multiple security standards, machine classifications, and patch security levels and be customized to interface with existing asset management tools. It evaluates the most suitable patch to satisfy the minimal patch requirements and is an early warning system that will tell a user when the user's machine will go out of compliance. The tool is composed of two parts: a server component and client component.

Abstract: Communication endpoints, software update servers, and related methods are disclosed. A communication endpoint includes a data storage device including a boot loader partition, a boot loader settings partition, and a plurality of combo image partitions. A method includes receiving an update package including a new combo image and one or more repair modules configured to diagnose and repair at least one of a boot loader, boot loader settings, and a file system of the communication endpoint. The method also includes replacing a combo image stored on one of the plurality of combo image partitions with the new combo image, and executing at least one of the one or more repair modules. A software update server includes a data storage device including the update package, and communication elements configured to transmit the update package to the communication endpoint.

Abstract: A method for managing application patterns. Service application programming interfaces required for use by an application on a runtime platform are provisioned. The application is based on an application pattern. Deployment information for deploying the application on the runtime platform is generated. The deployment information includes values for properties of the application pattern for configuring the application on the runtime platform. The deployment information is used to deploy the application on the runtime platform. In response, the runtime platform runs the application with the application using the service application programming interfaces previously provisioned for use by the application on the runtime platform.

Abstract: Methods and apparatus for analyzing the interface usage and requirements within software applications. In one embodiment, the interfaces comprise application programming interfaces (APIs) used with Java-based software, and the apparatus comprises a computer program that analyzes file paths (or classpaths) containing one or more files comprising Java bytecode. The names of the classes are extracted and placed into a class dictionary. The different classes listed in the dictionaries are broken down into their individual methods. Each method is then dissembled and analyzed for method or field invocations on other classes found in the dictionary. Methods called are added to a “used class” report. The used class report preferably contains the name of the class, method and the instruction information.

Abstract: In an approach for refining data for an impact analysis, a computer receives a selection of source code and impact analysis criteria, wherein the impact analysis criteria includes at least a time frame. The computer determines a subset of the selected source code, the subset within a time frame specified by the selected impact analysis criteria. The computer returns results based on the selected impact analysis criteria, wherein the results include the subset of the selected source code.

Abstract: A method, system, and computer program product for evaluating compliance of a user interface design are provided in the illustrative embodiments. A hierarchy of elements of a user interface is received from a first application executing in a client data processing system. A second application presents the user interface including a set of user interface elements at the client data processing system. A compliance rule is selected from a set of compliance rules. An evaluation is made whether an attribute associated with a user interface element meets a condition specified in the compliance rule. Responsive to the evaluating being negative, the user interface element is reported as being non-compliant with the compliance rule.

Abstract: A method and system configured for detecting availability of destination port associated with a virtual connection between a client and server communicating using SCSI over a fiber channel network by a server fiber channel adapter, reading data from a head of a singly linked list of a data stream storing data to be forwarded by the virtual connection engine executing the virtual connection without a lock by a consumer process thread while a producer process thread has access to the linked list of the data stream, and forwarding the data read from the head of the linked list to the destination port.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for selecting native code instructions. One of the methods includes receiving an initial machine language instruction for execution by a processor in a first execution mode; determining that a portion of the initial machine language instruction, when executed by the processor in a second execution mode, satisfies one or more risk criteria; generating one or more alternative machine language instructions to replace the initial machine language instruction for execution by the processor in the first execution mode, wherein the one or more alternative machine language instructions, when executed by the processor in the second execution mode, mitigate the one or more risk criteria; and providing the one or more alternative machine language instructions.

Abstract: Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.

Abstract: A partitioned key-value store is provided that supports atomic memory operations. A server performs a memory operation in a partitioned key-value store by receiving a request from an application for at least one atomic memory operation, the atomic memory operation comprising a memory address identifier; and, in response to the atomic memory operation, performing one or more of (i) reading a client-side memory location identified by the memory address identifier and storing one or more key-value pairs from the client-side memory location in a local key-value store of the server; and (ii) obtaining one or more key-value pairs from the local key-value store of the server and writing the obtained one or more key-value pairs into the client-side memory location identified by the memory address identifier. The server can perform functions obtained from a client-side memory location and return a result to the client using one or more of the atomic memory operations.

Abstract: Embodiments relate to a system for relative offset branching in a reduced instruction set computing (RISC) architecture. One aspect is a system that includes memory and a processing circuit communicatively coupled to the memory. The system is configured to perform a method that includes fetching a branch instruction from an instruction stream having a fixed instruction width. A relative offset value is acquired from the instruction stream. The relative offset value is formatted as an offset relative to a program counter value and sized as a multiple of the fixed instruction width. The relative offset value is added with the program counter value to form a branch target address value. The branch target address value is loaded into a program counter based on the branch instruction. Execution of the instruction stream is redirected to a next instruction based on the branch target address value in the program counter.

Abstract: In one embodiment, a computer-implemented method includes tracking a size of a load-store queue (LSQ) during compile time of a program. The size of the LSQ is time-varying and indicates how many memory access instructions of the program are on the LSQ. The method further includes scheduling, by a computer processor, a plurality of memory access instructions of the program based on the size of the LSQ.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

Abstract: Various embodiments relating to executing different types of instruction code in a micro-processing system are provided.

Abstract: The present invention is a data parallel system which is able to utilize a very high percentage of processing elements. In an embodiment, the data parallel system includes an array of processing elements and multiple instruction sequencers. Each instruction sequencer is coupled to the array of processing elements by a bus and is able to send an instruction to the array of processing elements. The processing elements are separated into classes and only execute instructions that are directed to their class, although all of the processing elements receive each instruction. In another embodiment, the data parallel system includes an array of processing elements and an instruction sequencer where the instruction sequencer is able to send multiple instructions. Again, the processing elements are separated in classes and execute instructions based on their class.

Abstract: Methods and arrangements for automatically finding the dependency of a software product on other software products or components. From an install image or directory, a signature is found by deriving the same from a directory structure of the software. Further, a directory tree structure is built and an approximate sub-tree matching algorithm is applied to find commonalties across software products.

Abstract: An information processing system includes an operation part that receives an operation performed by a user; and a body part that operates based on a request from the operation part. The operation part includes a power control part that, when receiving a power turning off instruction from the body part, reboots the operation part and causes the operation part to stand by in a power saving state in which some of operations are stopped, and, when receiving a start up notification from the body part, causes the operation part to return from the power saving state.

Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.

Abstract: A method for dynamically modifying a mobile device. The method includes a computer processor identifying a plurality of profiles on a mobile device. The method further includes a computer processor receiving one or more inputs on the mobile device. The method further includes a computer processor identifying at least one trigger that corresponds to the received one or more inputs, wherein the at least one trigger is associated with at least one profile of the plurality of profiles. The method further includes a computer processor determining if the at least one trigger activates a response, based at least in part, on data included in the at least one profile that is associated with the at least one trigger. The method further includes a computer processor responding to the determination that the at least one trigger activates a response and applying the response to the mobile device.

Abstract: Systems and methods for caching firmware instructions in a non-volatile memory of an information handling system (IHS). In an illustrative, non-limiting embodiment, an IHS may include a processor, a non-volatile memory coupled to the processor, and a unified extensible firmware interface (UEFI) chipset coupled to the processor. The processor may be configured to: copy instructions stored in the UEFI chipset to the non-volatile memory prior to a reboot or restart of the HIS, and, at least in part in response to the reboot or restart operation, load at least a subset of the instructions directly from the non-volatile memory rather than from the UEFI chipset as part of a fast boot mode of operation.

Abstract: In one embodiment, a triggered reboot of a field area router (FAR) of a computer network is initiated, and gathered states of the FAR are saved. The nodes in the computer network are informed of the triggered reboot, and then feedback may be collected from the nodes in response to the triggered reboot. As such, it can be determined whether to complete the triggered reboot based on the feedback, and the FAR is rebooted in response to determining to complete the triggered reboot. In another embodiment, a node receives information about the initiated triggered reboot of the FAR, and determines whether it has critical traffic. If not, the node buffers non-critical traffic and indicates positive feedback in response to the triggered reboot, but if so, then the node continues to process the critical traffic and indicates negative feedback in response to the triggered reboot.

Abstract: An information processing apparatus includes a startup condition acquisition unit that acquires a startup condition of multiple program modules, a determination unit that determines a startup order of the multiple program modules by multiple CPU cores, a startup unit that starts up the multiple program modules by executing an executable program module in accordance with the startup order by the multiple CPU cores, an updating unit that updates load information that indicates multiple CPU core load that fluctuates during a startup process, and a limitation unit that limits startup of the program module by the multiple CPU cores based on the load information updated by the updating unit.

Abstract: Disclosed is a baseboard management controller (BMC) that may include a bootloader, and an interface to a removable storage device having a first firmware file. The bootloader may be configured to load the first firmware file from the removable storage device for the BMC to run a kernel.

Abstract: In an information processing device, if the power state of a peripheral device changed by a class driver is the low-power state, in which the peripheral device consumes less power than in its normal state but its operation is limited, a filter driver below the class driver suspends controlling the peripheral device in accordance with a control request from an application program without passing through the class driver until the power state of the peripheral device returns to the normal state.