Abstract: A framework for the automated testing of mobile applications is disclosed. A mobile application to be operated on a mobile device is built based on a source code of the mobile application. The mobile application operates with a backend system. A test configuration for the mobile application and the backend system are defined. An automated test is performed with the test configuration on the mobile application on the mobile device and on the backend system. A log of test results is generated from the automated test performed on the mobile application and on the backend system.

Abstract: A method, system, and/or computer program product propagates system upgrades to peer computers in a peer community. A peer community is defined by identifying peer computers that each have a copy of a same system component. Each of the peer computers in the peer community is autonomous, such that no peer computer controls another peer computer. A test computer is selected from the peer computers. An upgrade to a system component on the test computer is installed and tested. In response to the upgrade to the system component functioning properly within the test computer, a message is sent to other peer computers within the peer community recommending that they install the upgrade.

Abstract: One or more test controls within code under test are enabled and then executing the code under test is executed. When enabled, the test control will interact with a tester when the code under test is executed (e.g., by providing data to the tester). The selection to enable the test control can be made based on whether the system accessing the code under test is a tester. If the system is a tester, the test control is enabled. Otherwise, the test control is disabled. The test control can include an execution control, a data definition control, and/or a log control.

Abstract: Various embodiments test an optimized binary module. In one embodiment, a region in a set of original binary code of an original binary module in which branch coverage is expected to be achieved is selected based on a set of profile information. The region is selected as a target region to be optimized. An optimized binary module is created, where the target region has been optimized in the optimized binary module. The optimized binary module is verified by synchronizing execution of the optimized binary module with execution of the original binary module at a checkpoint while executing both the optimized binary module and the original binary module. The optimized binary module is further verified by comparing an output from executing the optimized binary module to an output from executing the original binary module.

Abstract: Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or more errors are detected during a two-pass scrub operation on the memory address. Based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address is selected. The one or more selected counters are updated based on the result of the two-pass scrub operation.

Abstract: Disclosed is an address mapping method for a data storage device using a hybrid mapping scheme. The address mapping method determines whether write data includes a defined super sequential block (SSB), and selects an address mapping mode for the write data in accordance with whether or not a SSB is present.

Abstract: A FLASH memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write protection mapping table shows the write protection statuses of the different logical addresses. In accordance with logical addresses issued via a dynamic capacity management command from a host, a controller of the data storage device modifies the logical-to-physical address mapping table to break the logical-to-physical mapping relationship of the issued logical addresses. Further, the controller asserts a flag, corresponding to the issued logical addresses, in the write protection mapping table, to a write protected mode. According to a change in the amount of write-protected flags of the write protection mapping table, the controller adjusts an end-of-life judgment value of the FLASH memory and thereby a lifespan of the FLASH memory is prolonged.

Abstract: A data storage device is provided. The data storage device, coupled to a host, includes: a flash memory; and a controller, configured to control accessing of the flash memory; wherein when the host performs random data accessing to the flash memory, the controller retrieves address information of a corresponding block and a corresponding page in the flash memory associated with first data to be read based on a global mapping table, and pre-fetches the corresponding page from the flash memory based on the address information; wherein when the controller obtains the address information, the controller further determines whether the first data is located in a current buffer block based on a local mapping table; wherein when the first data is located in the current buffer block, the controller further cancels the pre-fetched corresponding page, and reads the first data from the current buffer block.

Abstract: A storage control device that controls a solid state drive group including two or more solid state drives sharing data storage includes a detector that detects a wear state of each of the solid state drives, a separation controller that separates a solid state drive having a wear value, which represents a wear state, exceeding a first threshold among the solid state drives, and an enlargement controller that, when detecting a solid state drive having a wear value, which represents a wear state, exceeding a second threshold less than the first threshold among the solid state drives in the solid state drive group, enlarges a difference in a wear value, which represents a wear state, between the solid state drive having the wear value exceeding the second threshold and a remainder of the solid state drives.

Abstract: A method for writing update data into a flash memory module to replace original data is provided. The flash memory module includes at least one block including a plurality of sectors. Each of the sectors records a flag. The data storing method includes: getting a first sector, wherein all the bits of the flag of the first sector are the second storage status; writing the update data into the first sector, and programming at least one bit as the first storage status and at least one bit as the second storage status in the flag of the first sector; identifying a second sector storing original data, wherein at least one bit of the flag of the second sector is first storage status and at least one other bit is second storage status; programming all the bits of the second sector as the first storage status.

Abstract: Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations. Persistent storage may be maintained by systems with or without memory management units.

Abstract: Resources of an address space are managed in dynamically sized ranges, extents, sets, and/or blocks. The address space may be divided into regions, each corresponding to a different, respective allocation granularity. Allocating a block within a first region of the address space may comprise allocating a particular number of logical addresses (e.g., a particular range, set, and/or block of addresses), and allocating a block within a different region may comprise allocating a different number of logical addresses. The regions may be configured to reduce the metadata overhead needed to identify free address blocks (and/or maintain address block allocations), while facilitating efficient use of the address space for differently sized data structures.

Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.

Abstract: A technique for operating a cache memory of a data processing system includes creating respective pollution vectors to track which of multiple concurrent threads executed by an associated processor core are currently polluted by a store operation resident in the cache memory. Dependencies in a dependency data structure of a store queue of the cache memory are set based on the pollution vectors to reduce unnecessary ordering effects. Store operations are dispatched from the store queue in accordance with the dependencies indicated by the dependency data structure.

Abstract: Some embodiments of the inventive subject matter are directed to operations that include determining that an access request to a computer memory results in a cache miss. In some examples, the operations further include determining an amount of cache resources used to service additional cache misses that occurred within a period prior to the cache miss. Furthermore, in some examples, the operations further include servicing the access request to the computer memory based, at least in part, on the amount of the cache resources used to service the additional cache misses within the period prior to the cache miss.

Abstract: A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.

Abstract: Methods and systems may provide for receiving, at a graphics processor, a workload from a host processor and using a kernel on the graphics processor to issue a thread group for execution of the workload on the graphics processor. Additionally, one or more coherency messages may be initiated, by the graphics processor, in response to a thread-related condition of one or more caches on the graphics processor. In one example, the thread-related condition is associated with the execution of the workload on the graphics processor and indicates that the one or more caches on the graphics processor are not coherent with a system memory associated with the host processor.

Abstract: Prefetching is permitted to cross from one physical memory page to another. More specifically, if a stream of access requests contains virtual addresses that map to more than one physical memory page, then prefetching can continue from a first physical memory page to a second physical memory page. The prefetching advantageously continues to the second physical memory page based on the confidence level and prefetch distance established while the first physical memory page was the target of the access requests.

Abstract: A device for multi-stage translation of prefetch requests includes a prefetch queue for providing queued prefetch requests, each of the queued prefetch requests including N different control entries; N serial-connected translation stages for the translation of N control entries of one of the queued prefetch requests into a translated prefetch request, wherein a translation in a i-th translation stage is dependent on a translation in a (i?1)-th translation stage, i?[1, . . . , N]; and a prefetch issuer which is configured to control an index for each of the N different control entries in the prefetch queue and to issue a prefetch of the indexed control entry of the N different control entries for the highest non-stalled translation stage.

Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

Abstract: Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The data may include data intended to be stored in the storage area. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a write command and may further be configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

Abstract: An integrated nonvolatile memory control subsystem and method are disclosed. The integrated nonvolatile memory control subsystem includes a nonvolatile buffer cache, a nonvolatile journal area, nonvolatile storage, and an integrated memory control unit. The integrated memory control unit performs a read operation, a write operation, a commit operation and a checkpoint operation on the cache blocks of the nonvolatile buffer cache and the journal blocks of the nonvolatile journal area. The integrated memory control unit sets each of data blocks of the nonvolatile storage as one among valid state, erasable state and invalid state, depending on being cached or not, being journaled or not, and being a clean cache or not, so as to maintain an authentic original up-to-date consistent data within any one of the nonvolatile buffer cache, the nonvolatile journal area and the nonvolatile storage.

Abstract: A method and apparatus for selectively powering down a portion of a cache memory includes determining a power down condition dependent upon a number of accesses to the cache memory. In response to the detection of the power down condition, selecting a group of cache ways included in the cache memory dependent upon a number of cache lines in each cache way that are also included in another cache memory. The method further includes locking and flushing the selected group of cache ways, and then activating a low power mode for the selected group of cache ways.

Abstract: A hierarchical cache structure includes at least one real indexed higher level cache with a directory and a unified cache array for data and instructions, and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache of a split real indexed second level cache includes a directory and a corresponding cache array connected to the real indexed third level cache. A data cache of the split second level cache includes a directory connected to the third level cache. An instruction cache of a split virtually indexed first level cache is connected to the second level instruction cache. A cache array of a data cache of the first level cache is connected to the cache array of the second level instruction cache and to the cache array of the third level cache. A directory of the first level data cache is connected to the second level instruction cache directory and to the third level cache directory.

Abstract: Systems and methods for lazy memory transformation in virtual machine live migration. An example method may comprise: receiving, by a computer system, a plurality of transformed memory blocks, each transformed memory block comprising one or more memory pages mapped into an address space of a virtual machine being migrated to the computer system; storing, in a memory data structure, one or more mappings, each mapping comprising a guest virtual address of a memory page and an identifier of a transformed memory block containing the memory page; responsive to detecting an access to a memory page by the virtual machine, identifying, using the memory data structure, a transformed memory block containing the memory page being accessed; and storing in a memory mapped into the address space of the virtual machine the memory page produced by performing a reverse transformation of the transformed memory block.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device performs translation lookaside buffer coherency for a translation lookaside buffer of the graphics processing unit of the device. In this embodiment, the device receives a request to remove an entry of the translation lookaside buffer of the graphics processing unit, where the device includes a central processing unit and the graphics processing unit. In addition, the entry includes a translation of virtual memory address of a process to a physical memory address of system memory of a central processing unit and the graphics processing unit is executing a compute task of the process. The device locates the entry in the translation lookaside buffer and removes the entry.

Abstract: A computer-implemented method for migrating a buffer used for direct memory access (DMA) may include receiving a request to perform a DMA data transfer between a first partitionable endpoint and a buffer of a first memory in a system having two or more processor chips. Each processor chip may have an associated memory and one or more partitionable endpoints. The buffer from the first memory may be migrated to a second memory based on whether the first memory is local or remote to the first partitionable endpoint, and based on a DMA data transfer activity level. A memory is local to a partitionable endpoint when the memory and the partitionable endpoint are associated with a same processor chip. The DMA data transfer may then be performed.

Abstract: A memory can be a sum addressed memory (SAM) that receives, for each read access, two address values (e.g. a base address and an offset) having a sum that indicates the entry of the memory to be read (the read entry). A decoder adds the two address value to identify the read entry. Concurrently, a predecode module predecodes the two address values to identify a set of entries (e.g. two different entries) at the memory, whereby the set includes the entry to be read. The predecode module generates a precharge disable signal to terminate precharging at the set of entries which includes the entry to be read. Because the precharge disable signal is based on predecoded address information, it can be generated without waiting for a full decode of the read address entry.

Abstract: To improve response performance of a storage control device. A storage control device 1 connected to a host computer 2 includes: a communication unit 1A that receives a command, to which a priority is set, from the host computer; a command executing unit 1B that executes the command received from the communication unit according to the priority; a cache memory 1C that is used by the command executing unit; a cache controller 1E that manages slots of the cache memory; and a plurality of storage devices 1D(1) and 1D(2) that stores data used by the host computer. The cache controller sets the priority to a slot that stores target data of the command and controls the data stored in the slot according to the priority.

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract: Computers and networks are configured to operate according to alternative protocols for using software applications, depending on geographic location. In one approach each computer incorporates a GPS receiver using GPS satellite signals to generate the computer's current location. The location is compared with permitted use region information stored in the computer or network, e.g. based on a boundary defining a permitted use region. In another approach, E-911 compliant transceivers use signals from E-911 towers in the same manner. In a further approach, each computer incorporates a WiFi adaptor, RFID reader or RFID tag, and the territory is defined by the distance from a center point. In all cases, the computer either operates under a relatively open protocol relative to using a given software application, or operates under a relatively restricted protocol, depending on whether it is inside or outside of the permitted use region.

Abstract: A method and system for detecting tampering of authenticated memory blocks that are accessible by an untrusted host processor. by (1) periodically re-authenticating the memory blocks from a trusted computing environment, and (2) disabling accessing of the memory blocks by the untrusted host processor when the re-authenticating fails. In one implementation, each of the memory blocks has an authentication code, and the accessing of the memory blocks is disabled by disabling the untrusted host processor. The memory blocks may be re-authenticated sequentially or randomly, e.g., based on a random block selection based on the block location, or based on temporal randomness. The re-authenticating is preferably effected by an authentication module in the trusted computing environment.

Abstract: Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation specifying both a user key and a version identifier, the storage system may permanently delete the specified version of an object having the specified key. In response to a delete operation specifying a user key, but not a version identifier, the storage system may create a delete marker object that does not contain object data, and may generate a new version identifier for the delete marker. The delete marker may be stored as the latest object version of the user key, and may be addressable in the storage system using a composite key comprising the user key and the new version identifier. Subsequent attempts to retrieve the user key without specifying a version identifier may return an error, although the object was not actually deleted.

Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Abstract: Monitoring and reporting methods and apparatus include the acquisition of detailed aircraft state and systems data, analysis of the collected data, and transmission of the collected data and/or analysis of the collected data to a destination automatically via a portable electronic device which is carried onto and off of the aircraft by the pilot or another crew member. More particularly, monitoring and reporting methods and apparatus include collecting analog or digital sensor data onboard an aircraft, analyzing the data in real-time, and automatically transmitting the data and/or analysis of the data to a destination including a portable storage device such as a portable computer, electronic flight bag (EFB), or smart phone, by means such as wireless transmission, for automatic transfer to another destination when the portable computer, electronic flight bag (EFB), or smart phone is off of the aircraft.

Abstract: A hosting computer accepts specialized keyboard and mouse input via a generic device redirection channel from a client computer. A device manager has interfaces to the generic device redirection channel and to a system queue for communicating keyboard and mouse input events to an operating system. The system queue has a separate interface to a virtual channel for receiving redirected keyboard and mouse input from standard keyboard and mouse devices. The device manager identifies keyboard and mouse functions of other devices connected to the client computer and having device input redirected to the hosting computer via the generic device redirection channel, and establishes respective device context engines for handling input events from the identified functions. The device context engines open the keyboard and mouse functions, and upon receiving input events from functions, queues the input events on the system queue to communicate them to the operating system.

Abstract: Systems, methods, and computer program product embodiments for a reconfigurable system are described herein. An embodiment includes a power supply an integrated controller configured to host a plurality of sensors and a display. The embodiment also includes a video decoder configured to receive a plurality of inputs and route a selected input based on an interaction with the display. Further, the embodiment includes memory devices configured to store the selected input.

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.

Abstract: Provided are a method and device for buffer processing in a System on Chip (SoC). The method includes that when a first datum of a first user needs to be buffered, a current storage start address is read, the first datum is stored into a buffer space from the current storage start address, wherein the buffer space occupied by the first datum is a first buffer space; corresponding to the first datum, storage location information including a start address and a space length of the first buffer space is saved, so that when the first datum needs to be read, the first buffer space is located according to the start address and the space length, and the first datum is read from the first buffer space; the current storage start address is updated with a next address of the first buffer space, so that next data needing to be buffered is buffered from the updated current storage start address.

Abstract: Embodiments are provided for isolating Input/Output (I/O) execution by combining compiler and Operating System (OS) techniques. The embodiments include dedicating selected cores, in multicore or many-core processors, as I/O execution cores, and applying compiler-based analysis to classify I/O regions of program source codes so that the OS can schedule such regions onto the designated I/O cores. During the compilation of a program source code, each I/O operation region of the program source code is identified. During the execution of the compiled program source code, each I/O operation region is scheduled for execution on a preselected I/O core. The other regions of the compiled program source code are scheduled for execution on other cores.

Abstract: An interface unit configured to perform transfers between a processor and one or more peripheral devices is disclosed. A system includes a processor, a number of devices (e.g., peripheral devices), and an interface unit coupled therebetween. The interface unit includes FIFOs for storing data transmitted to or received from the devices by the processor. The interface unit may access data from a device responsive to a request from the processor. The data may be loaded into a FIFO according to transfer parameters controlled by the device. After the data has been received by the FIFO, the interface unit may generate an interrupt to the processor. Data may then be transferred from the interface unit to the processor according to transfer parameters controlled by the processor. The interface unit may thus homogenize a processor interface to a number of different devices.

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module command signals and module control signals. The module command signals are provided to memory devices organized in groups, each group including at least one memory device, while the module control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits. The plurality of buffer circuits are associated with respective groups of memory devices and are distributed across a surface of the memory module such that each module control signal arrives at the plurality of buffer circuits at different points in time.

Abstract: The present disclosure provides methods and systems to allow user space applications running on different cores to efficiently communicate interrupts between each other without have to enter an OS kernel. In one aspect, a hardware device for delivering inter-processor interrupts is provided. The hardware device includes a memory having a memory space that corresponds to a virtual memory space of a first guest process and a controller coupled to the memory. The controller may be configured to detect when interrupt information is recorded in the memory space. In that regard, the interrupt information is directed to a second guest process associated with a particular CPU core. In response to detecting interrupt information recorded in the memory space, the controller is configured to cause the second guest process to run on a different CPU core without making an operating system call.

Abstract: The present invention relates to the field of communications on rail trains. A PicoBlaze-based MVB controller includes a pMVB controller, a traffic memory, an ARM adapter, and a bus arbiter. The pMVB controller, the traffic memory, ARM adapter, and the bus arbiter are connected to an external bus BUS1. The pMVB controller is connected to the traffic memory. The ARM adapter is connected to an external ARM processor and the bus arbiter. The traffic memory can store network communication data and input control information, and send them to the pMVB controller. The pMVB controller responds to the control information, and sends the communication data, and after it is encoded, to the MVB bus via the external bus BUS1. The pMVB controller also decodes data received from the pMVB bus and triggers an interrupt. The bus arbiter is responsible for bus arbitration in accordance with the instructions from the pMVB controller.

Abstract: A system having an arbitrated interface bus and a method of operating the same are provided. The system may include, but is not limited to, one or more registers configured to store data, a plurality of external interfaces configured to receive data access requests for the register(s), an arbitrator communicatively coupled to each of the plurality of external interfaces, and an interface bus communicatively coupled between the arbitrator and the register(s), wherein the arbitrator is configured to arbitrate control of the interface bus between the plurality of external interfaces.

Abstract: A sideband PCI Express (PCIe) packet initiator in a distributed PCIe switch fabric verifies a PCIe connection between a host device and a PCIe endpoint device without having to power on the host device. The packet initiator assembles a PCIe test packet that acts as a ping for testing reachability of the endpoint device, from the perspective of the host device. The test packet may also verify configurations and settings of the path to the endpoint device. The distributed switch fabric is configured to compare completion data with expected results to verify the PCIe connection, without having to boot the host device.

Abstract: Provided is a remote terminal device having an industrial versa module eurocard bus (VMEbus) structure and including a main module that receives control logic information of a field device from an input/output module, and a programmable logic controller (PLC) function module that receives the control logic information from the main module, performs a logic corresponding to the control logic information, and outputs a result of the performed logic. The PLC function module includes a dual port RAM including a plurality of memory areas, and a PLC chip that reads the control logic information written on one of the plurality of memory areas, performs the logic corresponding to the read control logic information, and outputs the result of the performed logic to another one of the plurality of memory areas.

Abstract: A peripheral component interconnect (PCI) adapter includes a PCI connector for connecting to a PCI slot of a motherboard, a first PCI expansion slots for connecting a first PCI card, a second PCI expansion slot for connecting a second PCI card, a detection control circuit connected to the first PCI expansion slot and the second PCI expansion slot, and an alarm circuit connected to the detection control circuit. The detection control circuit detects operation power of the first PCI card and the second PCI card, and controls the alarm circuit to report a fault alarm when the operation power of the first PCI card exceeds a threshold power of the first PCI expansion slot or the operation power of the second PCI card exceeds a threshold power of the second PCI expansion slot.