Abstract: Systems and methods for disposing and supporting a solar panel array are disclosed. The embodiments comprise various combinations of cables, support columns, and pod constructions in which to support solar panels. Special installations of the system can include systems mounted over structures such as parking lots, roads, aqueducts, and other bodies of water. Simplified support systems with a minimum number of structural elements can be used to create effective support for solar panel arrays of varying size and shapes. These simplified systems minimize material requirements and labor for installation of the systems.

Abstract: A solar-powered system includes a mounting assembly to affix a solar active component mounted to a support member by the mounting assembly, such that both sides of the solar active component have solar exposure.

Abstract: A system for measuring the power or energy loss in a photovoltaic array due to soiling, which is the accumulation of dust, dirt, and/or other contaminants on the surfaces of photovoltaic modules, comprising: a pair of photovoltaic reference devices placed within or near the photovoltaic array and co-planar to the modules comprising the array, wherein one reference device is a module similar to those of the array and is allowed to accumulate soiling at the natural rate, and wherein the second reference device is a module or a cell and is periodically cleaned; and a measurement and control unit which measures and compares the electrical outputs of the soiled reference device and the clean reference device in order to determine the fraction of power lost by the soiled reference module due to soiling.

Abstract: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.

Abstract: Adaptive biasing circuits for input differential pairs of a buffer or an amplifier adapt to autozero currents for discrete pair selection or continuous pair selection. The adaptive biasing circuits include a multistage device including current source and follower devices with a plurality of switches for a two-phase operation: autozero and amplifying phases. During an autozero phase, input differential pairs are isolated from subsequent stages and biasing currents are determined for autozeroing of input offset voltages. During an amplifying phase, both input differential pairs can be coupled to subsequent stages for continuous selection or a selected input differential pair can be coupled to subsequent stages for discrete selection.

Abstract: An amplifier circuit with improved accuracy is provided that comprises a cascade of amplifier stages, a control line for controlling the amplifier stages, a feedback circuit having an input port for receiving a reference signal, and a feedback loop connecting the feedback circuit to the control line. Via the feedback circuit and the feedback loop, the large signal behavior of the amplifier stage is accurately fixed. As a result, the small signal gain of the amplifier stages has an improved accuracy as well.

Abstract: A low noise amplifier and a chip. The amplifier includes a biasing circuit unit, a first amplifying circuit unit, a first adjusting unit, a first signal input, a second signal input and a first signal output; the biasing circuit unit includes a first voltage output and a second voltage output; the first amplifying circuit unit includes a first N-type transistor, a first P-type transistor, a first output capacitor, a second output capacitor, a first impedance and a second impedance; gates of first N-type and P-type transistors are connected to first voltage output and first signal input, and second voltage output and first signal input, respectively, via adjusting unit; source of first N-type transistor is connected to source of first P-type transistor and second signal input; drains of first N-type and P-type transistors are connected respectively to impedance, and to first signal output and second signal output via output capacitor.

Abstract: A parallel resonant circuit with excellent distortion and saturation characteristics is provided at low power consumption. A first power-supply voltage is applied to the parallel resonant circuit. In the parallel resonant circuit, a variable resistor includes one or more parallel-connected branches. Each of the branches includes a series circuit of a resistor and a MOS switch. A second power supply supplies power of control signals applied to respective gates of the MOS switches, and supplies back gate voltages to the MOS switches. A power-supply voltage of the second power supply is higher than the first power-supply voltage.

Abstract: One example includes an OP-AMP circuit system. The system includes a signal amplification path comprising a signal amplification path comprising a signal amplifier and an output stage. The signal amplification path can be configured to amplify an input voltage received at an input to provide an output voltage via the output stage. The system also includes an offset-reduction path coupled to the input of the signal amplification path and to an output of the signal amplifier. The offset-reduction path includes a transconductance amplifier and at least one chopper that are configured to mitigate noise in the signal amplification path and a noise-filtering feedback path configured to provide chopper feedback with respect to an offset voltage associated with the offset-reduction path, the noise-filtering feedback path comprising a feedback path input coupled to the input of the transconductance amplifier via a resistor.

Abstract: An RF circuit for wireless devices comprises a single differential power amplifier and an impedance balancing circuit for each frequency band. The impedance balancing circuit serves both to provide an appropriate impedance at the output of the amplifier as the operating mode of the device changes, and also transforms the differential output of the amplifier to a single-ended output. The impedance balancing circuit optionally comprises a BALUN circuit and a variable capacitor that is varied as the operating mode changes in order to vary the impedance at the output of the amplifier.

Abstract: An embodiment of an amplifier has a bandwidth defined by low and upper cutoff frequencies. The amplifier includes an input impedance matching circuit and a transistor. The transistor has a gate, a first current conducting terminal coupled to an output of the amplifier, and a second current conducting terminal coupled to a reference node. The input impedance matching circuit has a filter input coupled to an input of the amplifier, a filter output coupled to the gate of the transistor, and a multiple pole filter coupled between the filter input and the filter output. A first pole of the filter is positioned at a first frequency within the bandwidth, and a second pole of the filter is positioned at a second frequency outside the bandwidth. The input impedance matching circuit is configured to filter the input RF signal to produce a filtered RF signal at the filter output.

Abstract: The present invention relates to a class D audio amplifier comprising a pulse width modulator, an adjustable loop filter and a feedback loop. The pulse width modulator generates a first set of pulse width modulated control signals at an adjustable modulation frequency for respective switch control terminals of a first output driver. A controller of the class D audio amplifier is configured to control frequency response characteristics of the adjustable loop filter based on a frequency setting of the adjustable modulation frequency.

Abstract: A variable gain amplifier circuit includes a differential pair of transistors and a variable current source circuit. The differential pair of transistors generates an output signal based on an input signal. The variable current source circuit is coupled to the differential pair of transistors. A gain of the output signal relative to the input signal varies in response to variations in a bias current through the variable current source circuit. The variable gain amplifier circuit maintains a common mode voltage of the output signal substantially constant in response to the variations in the bias current through the variable current source circuit.

Abstract: The disclosure relates to an enhanced Doherty amplifier that provides significant performance improvements over conventional Doherty amplifiers. The enhanced Doherty amplifier includes a power splitter, combining node, a carrier path, and a peaking path. The power splitter is configured to receive an input signal and split the input signal into a carrier signal provided at a carrier splitter output and a peaking signal provided at a peaking splitter output. The carrier path includes carrier power amplifier circuitry, a carrier input network coupled between the carrier splitter output and the carrier power amplifier circuitry, and a carrier output network coupled between the carrier power amplifier circuitry and the Doherty combining node.

Abstract: Provided is a redundant amplifier, including: a first switch for connecting, on a one-to-one basis, inputs P1 to Pm to m of outputs Q1 to Qn, where m and n are natural numbers and m<n is satisfied; a second switch for connecting, on a one-to-one basis, m of inputs R1 to Rn to m outputs S1 to Sm; and amplifiers A1 to An connected on a one-to-one basis between the outputs Q1 to Qn and the inputs R1 to Rn. Signal paths L1 to Lm are formed in accordance with a connection state between an input and an output of each of the first switch and the second switch, the signal paths L1 to Lm connecting the input P1 and the output S1, the input P2 and the output S2, . . . , and the input Pm and the output Sm, respectively, via any one of the amplifiers A1 to An. The connection state has at least two types in which the signal paths L1 to Lm each have the same length.

Abstract: A client device with one or more processors and memory identifies an action mode of a user of the client device in an application while executing the application. The client device detects an event in the action mode. The client device adjusts an audio mixing mode of sound effects in the application (e.g., adjusting a volume of audio associated with the event and a volume of background music for the application) based on the detected event.

Abstract: An example method may involve a device determining a first loudness representation for a playback device based on a first equalization setting applied to a representation of average music. The device may also determine a second loudness representation for the playback device, based on a second equalization setting applied to the representation of average music. The device may also determine a loudness adjustment factor based on the first and second loudness representations, and then causing the playback device to play back media based on the second equalization setting and the determined loudness adjustment factor.

Abstract: There is disclosed a balun for dividing an input electrical signal to produce first and second output electrical signals which are substantially out of phase, the balun including: an input port for receiving the input electrical signal; an input line for coupling the input electrical signal to a slotline; and an output line for coupling the first and second output electrical signals to, respectively a first output port and a second output port, the output line having a junction with the slotline; wherein the slotline couples the input electrical signal to the junction, and the junction acts as a divider to produce the first and second electrical signals; in which at least one of the input line, slotline and output line has a width and a length wherein the width varies over the length.

Abstract: RF communications circuitry, which includes a first RF filter structure and control circuitry, is disclosed. The first RF filter structure includes a pair of weakly coupled resonators and a first tunable RF filter. The control circuitry provides a first filter control signal. The first tunable RF filter receives and filters an upstream RF signal to provide a first filtered RF signal, such that a center frequency of the first tunable RF filter is based on the first filter control signal.

Abstract: A second conductor plane (102) is formed in a layer different from a layer in which a first conductor plane (101) is formed, and faces the first conductor plane (101). A first transmission line (104) is formed in a layer different from the layers in which the first conductor plane (101) and the second conductor plane (102) are formed, and faces the second conductor plane (102), and one end thereof is an open end. A conductor via (106) connects the other end of the first transmission line (104) and the first conductor plane (101). An insular conductor (112) is connected to a portion of the first transmission line (104) other than a portion thereof at which the transmission line (104) is attached to the conductor via (106), is located in a layer different from the layer in which the second conductor plane (102) is located, and faces the second conductor plane (102).

Abstract: A Radio Frequency (RF) filter configured by combining a hybrid coupler with a general filter, for having different characteristics from original characteristics of a general filter is provided, in which a coupler receives an input signal through a first port, divides the input signal, outputs the divided signals through second and third ports, combines signals received through the second and third ports according to phases of the signals, and outputs the combined signal through the first port or as an output signal of the RF filter through a fourth port, and a first filter unit has a first port connected to the second port of the coupler and a second port connected to the third port of the coupler, for having a predetermined frequency filtering characteristic.

Abstract: A splitter circuit includes a first branch circuit and a second branch circuit. Each branch circuit includes a capacitor, an inductor and a resistor. A first end of the capacitor is configured to receive RF signals. A first end of the inductor is coupled to a second end of the capacitor. The second end of the inductor is coupled to ground. The resistor is coupled to the second end of the capacitor to output RF signals. The resistor in the first branch circuit and the resistor of the second branch circuit respectively output RF signals to different devices.

Abstract: An elastic wave device making use of an SH plate wave propagating in LiNbO3 substrates includes a LiNbO3 substrate, IDT electrodes located on at least one surface of the LiNbO3 substrate, and a support which is bonded to the LiNbO3 substrate such that the support is located outside a region provided with the IDT electrodes and supports the LiNbO3 substrate, wherein ? of the Euler angles (0°, ?, 0°) of the LiNbO3 substrate ranges from about 92° to about 138° and the thickness of the LiNbO3 substrate ranges from about 0.05? to about 0.25?, where ? is the wavelength determined by the pitch between electrode fingers of the IDT electrodes.

Abstract: Active-RC low-pass filters based on R-0.5R ladders are implemented to provide high linear and low power design solutions for integrated biomedical applications. Among various R-?R ladders family, R-0.5R ladders provide the best low frequency selectivity characteristics. The filters exhibit ultra-low pole frequencies and occupy relatively compact silicon areas by using the R-0.5R ladders.

Abstract: In order to achieve a circuit device capable of stably supplying an antenna with electric power in a broad power range to output a transmission signal, the circuit device includes a current source adapted to supply a first current in a first operation mode, and supply a second current higher than the first current in a second operation mode, and a drive section supplied with the electric power from the current source, and adapted to perform drive for outputting a transmission signal to an antenna via a matching circuit.

Abstract: Aspects and embodiments are directed to non-linear systems including a digital compensator structure, a method of digital compensation, and methods for designing digital compensator structures for analog receivers. A digital compensator is configured to substantially reduce the one or more nonlinear distortion components in the sampled digital output signal from the analog receiver to provide an output signal achieving a receiver linearity requirement for the combination of the analog receiver and a digital compensator.

Abstract: A first apparatus includes at least one scan chain. Each of the at least one scan chain includes scan cells coupled together. Each scan cell in the at least one scan chain includes a first type of scan cell when a reset state of the scan cell is a first state, and a second type of scan cell when the reset state of the scan cell is a second state. One or more scan chains of the at least one scan chain includes at least one of the first type of scan cell and at least one of the second type of scan cell. A second apparatus includes first and second sets of scan chains including flip-flops without both set and reset functionality. Each of the flip-flops in the first and second sets of scan chains has a reset state of a first state and a second state, respectively.

Abstract: Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described.

Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

Abstract: Disclosed herein are systems and methods for generating injection-locked, frequency-multiplied output signals. In an embodiment, a circuit includes a ring of a number (N) serially connected delay-buffer elements and an injection-pulse-generation circuit. Each delay-buffer element provides a time delay (D), and at least some of them have at least one pulse-locking injection port. The injection-pulse-generation circuit is configured to transmit balanced-delay injection-pulse signals—that are generated by applying balanced-delay selection logic to a clock signal according to pulse-selection control signals—to the pulse-locking injection ports to provide, at the ring output port, an injection-locked, frequency-multiplied output signal having a frequency that equals the reciprocal of (N*D) and that bears the same proportional relationship to the frequency of the clock signal that the period of the clock signal bears to (N*D).

Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.

Abstract: A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

Abstract: Toggling functional critical path timing sensors measure delays in toggling functional critical paths that are replicas of actual critical paths or representations of worst-case delay paths. A Toggle flip-flop or Linear-Feedback-Shift Register (LFSR) drives high-transition-density test patterns to the toggling functional critical paths. When a toggling functional critical path's delay fails to meet set-up timing requirement to a next register, the toggling functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. A margin delay buffer adds a delay to the toggling functional critical path before being clocked into an early capture flip-flop. A reference register receives the test pattern without the delay of the toggling functional critical path, and an exclusive-OR (XOR) gate compares outputs of reference and early capture flip-flops to generate timing failure signals to the controller.

Abstract: Toggling functional critical path timing sensors measure delays in toggling functional critical paths that continuously receive patterns from an aging pattern generator. Wear is accelerated. A margin delay adjustment controller sweeps margin delays until failures occur to measure delays. The margin delay is then adjusted in functional critical path timing sensors that add the margin delay to functional critical paths that carry user data or chip controls during normal operation. When the path delays fail to meet requirements, the functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. Wear on the toggling functional critical paths is accelerated using both toggle and low-transition-density patterns. Circuit aging is compensated for by increasing margin delays to timing sensors.

Abstract: Duty cycle error vectors that indicate both the magnitude and direction of the duty cycle error relative to a desired duty cycle are generated within a duty cycle measurement circuit, enabling threshold-based determination of whether duty cycle adjustment is necessary, refraining from power-consuming adjustment and follow-up measurement in those cases where the duty cycle is within a target range. When duty cycle adjustment is deemed necessary, the magnitude of the duty cycle error indicated by the duty cycle error vector may be applied to effect proportional rather than incremental duty cycle adjustment, quickly returning the clock duty cycle to a target range.

Abstract: A circuit and a method for controlling operation voltage, and a storage device are provided. The circuit includes: a voltage boost unit adapted for: if receiving a first signal, performing a voltage boost process; and if receiving a second signal, stopping the voltage boost process; a voltage division unit including a plurality of different voltage division coefficients, adapted for performing a voltage division process; a comparison unit adapted for: comparing the divided voltage with a reference voltage; if the divided voltage is low, outputting the first signal; and if not, outputting the second signal; a control unit adapted for performing a descending switching operation on the voltage division coefficients; and an output unit. The establishing speed of the operation voltage is effectively controlled, and an effect on device power consumption and performance caused by the threshold voltage and variations of the threshold voltage in the working process is eliminated.

Abstract: An absorptive switch architecture suitable for use in high frequency RF applications. A switching circuit includes a common terminal and one or more ports, any of which may be selectively coupled to the common terminal by closing an associated path switch; non-selected, unused ports are isolated from the common terminal by opening an associated path switch. Between each path switch and a port are associated shunt switches for selectively coupling an associated signal path to circuit ground. Between each path switch and a port is an associated absorptive switch module. Each absorptive switch module includes a resistor coupled in parallel with a switch. The combination of the resistor and the switch of the absorptive switch module is placed in series with a corresponding signal path from each port to the common terminal, rather than in a shunt configuration.

Abstract: A voltage generation apparatus may include an external voltage sensing circuit configured to generate a first start signal and a second start signal by sensing the magnitude of a first external voltage and the magnitude of a second external voltage. The voltage generation apparatus may include an internal voltage sensing circuit configured to generate a voltage generation signal by comparing an internal voltage with a target voltage. The voltage generation apparatus may include a voltage pumping circuit configured to be activated in response to the first start signal, configured to perform a pumping operation based on the voltage generation signal, and configured to generate the internal voltage. The voltage generation apparatus may include a voltage regulating circuit configured to be activated in response to the first and second start signals, and configured to generate the internal voltage based on the voltage generation signal.

Abstract: A gate driving circuit includes plural-stage output circuits, an Nth stage output circuit of the plural-stage output circuits includes an Nth stage shift register and a mixer. The Nth stage shift register is configured to output an Nth pulse signal. The mixer is coupled to the Nth stage shift register and an (N+M)th stage shift register, for respectively outputting a first clock signal and a predetermined pulse signal during different periods according to the Nth pulse signal and an (N+M)th pulse signal of the (N+M)th stage shift register. Wherein pulse widths or phases of the first clock signal and the predetermined pulse signal are different, and N and M are positive integers.

Abstract: A System-on-Chip includes a controller for generating a switching signal for driving a switching element of a power stage of a switched power converter. The power stage generates an output voltage according to the switching signal and an input voltage by the switching element. The controller is located on the same chip as the System-on-Chip and wherein the output voltage is generated for powering a supply domain of the System-on-Chip.

Abstract: A solid state switch may include a plurality of inputs, such as to receive a control signal to cause the solid state relay to selectively deliver power from an AC power source to an electrical load (e.g., a heater, a pump, a lighting source, a motor, etc.). The solid state switch may include at metal-oxide-semiconductor field-effect transistors (MOSFETs) connected in a series opposition arrangement, where a gate of each of the MOSFETs may be electrically connected to a corresponding one of the plurality of inputs. A signal output from the MOSFETs may provide a triggering signal at a gate input of each of a corresponding semiconductor switching device to close the solid state relay to enable power delivery from the AC power source to the electrical load.

Abstract: Apparatus and methods for radio frequency (RF) PIN diode switches are provided herein. In certain configurations, one or more PIN diode switches are integrated with a driver chip in a common package. The driver chip includes voltage regulators, such as switching regulators and/or charge pumps configured to generate voltage levels used to control biasing of the PIN diode switches. Thus, the packaged switch can operate using a single power supply voltage, which the voltage regulators of the driver chip use to generate biasing voltage levels used for controlling the PIN diode switches.

Abstract: A technique reduces erroneous judgment due to effects of noise accompanying PWM control while using PWM control for brightness adjustment of light-emitting diodes disposed proximate of an electrode. An electrode is disposed proximate of operating portions that are subject to touch operations by unit of a conductive body. An operating portion of a light-emitting diode is lightened. A CPU performs brightness adjustment of the light-emitting diode through PWM control. A detecting circuit outputs detected values in accordance with electrostatic capacitances of the electrode. The CPU judges that a touch operation has been made when a difference between a detected value of the detecting circuit and a reference value stored in a RAM is not less than a prescribed value. The CPU stores a detected value that is first detected by the detecting circuit after transition of an executing state of PWM control in the RAM as a reference value.

Abstract: A processing system for a capacitive input device comprises sensor circuitry and control logic. The sensor circuitry is configured to be communicatively coupled with sensor electrodes of the capacitive input device. The control logic is configured to operate the capacitive input device in a first mode comprising interference sensing at a first level and input object sensing. The control logic is also configured to operate the capacitive input device in a second mode instead of in the first mode in response to: interference measured in the first mode meeting an interference condition; and a determination that input is in a sensing region of the capacitive input device. While operating in the second mode, interference sensing with the capacitive input device is either not performed or else is performed at a second level that is lower in fidelity than the first level.

Abstract: A touch key assembly includes a light guiding film between a window and a display panel, a flexible printed circuit (FPC) film attached to the light guiding film, and an attaching member including an attaching portion interposed between the light guiding film and the window, and a blocking portion interposed between the window and the display panel.

Abstract: A circuit is disclosed that includes a plurality of voltage control circuits and a control module. Each of the voltage control circuits is controlled by a control signal. The control module is configured to generate the control signal and to determine a voltage level or a pulse width of the control signal in accordance with a current process corner condition of the voltage control circuits and at least one of first predetermined data and second predetermined data.

Abstract: An apparatus for an integrated clock gating cell is provided. The apparatus includes a logic gate that receives an unbuffered enable signal (E), a scan test enable signal (SE), and outputs an inverted enable signal (EN); a first transmission gate that receives E, SE, and EN; a second transmission gate that is connected to the first transmission gate and receives a clock signal (CK) and an enabled and inverted clock signal (ECKN); a first transistor having terminals connected to a power supply voltage (VDD), an output of the logic gate, and the first transmission gate respectively; a second transistor including terminals connected to the first transmission gate and VDD respectively; and a latch including terminals connected to the second transmission gate and the second transistor respectively.

Abstract: In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. In particular, the power gated block may include a set of series-connected flops that receive the block enable from the power manager circuit. The power gated block may include a set of multiplexors (muxes) that provide the local block enables for each power switch segment. One input of the muxes is coupled to the block enable, and the other input is coupled to another enable propagated through one of the other power switch segments. Accordingly, the muxes may be controlled to select the propagated enables or the input block enable.

Abstract: An input circuit includes: an input buffering unit suitable for receiving one or more input data, wherein each toggling time is defined according to a value of each input data; and a data transformation unit suitable for transforming the input data into an output data according to a mapping table and the toggling time of the input data during a data input duration.

Abstract: A device is disclosed that includes a driver circuit and a control circuit. The driver circuit is configured to provide an output signal according to an input signal, and operated with a first voltage and a second voltage. The driver circuit includes a pull up unit and a pull down unit configured to pull up and pull down a voltage level of the output signal, respectively. The control circuit is configured to selectively enable one of the pull up unit and the pull down unit according to the input signal, so as to adjust the voltage level of the output signal. The control circuit is further configured to drive the enabled one of the pull up unit and the pull down unit in a voltage mode or a current mode selectively according to the voltage level of the output signal, the first voltage and the second voltage.