Abstract: A clock circuit configured to generate a falling edge independently of an input clock signal is disclosed. In one embodiment, a clock circuit includes an input circuit coupled to receive an input clock signal. A corresponding first clock signal is provided on a first clock node, while a second clock signal that is a delayed version of the first is provided on a second clock signal. The clock circuit may generate an output clock signal based on the first and second clock signals and a feedback signal received from a functional circuit coupled to receive the output clock signal. The rising edge of the output clock signal is generated dependent upon when the rising edge of the input clock signal is received. The falling edge of the output clock signal is generated by the clock circuit independently of when the falling edge of the input clock signal is received.

Abstract: An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory.

Abstract: A semiconductor die having: a logic unit having a plurality of inputs/outputs; a plurality of pads whereby electrical connections can be made to the die; and a multiplexer arranged between the inputs/outputs and the pads, the multiplexer being operable in a first mode in which it maps a first number of the inputs/outputs to a first number of the pads with a first mean spacing between those pads, and a second mode in which it maps a second number of the inputs/outputs to a first number of the pads with a second mean spacing between those pads, wherein the first number is larger than the second number and the first spacing is smaller than the second spacing.

Abstract: A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2N-M?1 times out of 2N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2N-M, 2N-M times, using the divider.

Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.

Abstract: A capacitance phase interpolation circuit including a first capacitance phase interpolation unit and a second capacitance phase interpolation unit is disclosed. The first capacitance phase interpolation unit includes a first capacitance group, wherein a plurality of capacitors in the first capacitance group are in a ring coupling, and the first capacitance phase interpolation unit receives a plurality of reference clock signals. The second capacitance phase interpolation unit is coupled to the first capacitance phase interpolation unit and includes a second capacitance group, wherein a plurality of capacitors in the second capacitance group are in a ring coupling, and each of the output clock signals is obtained via the first capacitance phase interpolation unit and the second capacitance phase interpolation unit by performing phase interpolation on all the reference clock signals.

Abstract: A multi-channel delay locked loop includes a global delay locked loop and a plurality of local delay locked loops. The global delay locked loop is configured to lock an input clock signal and output a global delay control signal corresponding to a delay amount of the input clock signal during a locking operation. Each of the plurality of local delay locked loops is configured to output a channel clock signal by locking the input clock signal, and initialize the delay amount of the input clock signal according to the global delay control signal.

Abstract: Provided are a digital phase-locked loop (DPLL) having improved signal characteristics, and a method of operating the DPLL. The DPLL includes a first tracking unit configured to receive a reference signal and a feedback signal that is generated by feeding back an output signal of the DPLL, track the feedback signal, and output a delayed reference signal, and a second tracking unit configured to receive a delayed feedback signal generated by delaying the feedback signal, and the delayed reference signal, and generate an output signal of the DPLL, of which a frequency is controlled according to a phase difference between the delayed feedback signal and the delayed reference signal.

Abstract: A delay circuit device configured for delay adjustment monotonicity and method of operating therefor. This delay circuit device is configured with hybrid coarse-fine delay cells and uses a sequence of these delay cells activated in a way that builds-up the delay as a sequence of fine steps until it reaches the coarse delay value. This configuration allows for the continuing build of propagation delay by adding the fine steps of the following delay cells. In this manner, the monotonicity of the signal delay circuit is ensured by the architecture independent from device mismatch, thus eliminating problems with conventional delay circuits such as gaps and overlaps specific the these conventional delay cells.

Abstract: This invention discloses a clock generation circuit and a clock generation method for generating a clock. The clock generation circuit includes a reference clock generation circuit, which is installed in a chip for independently generating a reference clock; a temperature sensor for sensing an ambient temperature to generate temperature information; a temperature compensation module, coupled to the temperature sensor, for generating a temperature compensation coefficient according to the temperature information; and a clock adjusting circuit, coupled to the clock generation circuit, for generating the clock according to the reference clock and the temperature compensation coefficient. The temperature compensation module generates the temperature compensation coefficient dynamically such that the frequency of the clock approaches a target frequency and does not substantially vary with the temperature.

Abstract: Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: Disclosed systems include a clock-multiplying phase locked loop (PLL) generating a clock signal for a DAC comprising a plurality of DAC cells, the systems configured to control that a phase of the DAC output has a predefined relation to a phase of a PLL input reference clock. An exemplary system incorporates an auxiliary DAC cell implemented as a replica of one of the DAC cells of the DAC and operation of the DAC and the auxiliary DAC cell is timed with the same clock signal generated by the PLL, so that outputs of the auxiliary cell and the DAC are phase synchronized by design. The system is configured to ensure that a phase of the auxiliary DAC cell output is related to the phase of the PLL reference clock, which results in a phase of the DAC output also being related to the phase of the PLL reference clock.

Abstract: The present disclosure provides systems and methods for identifying changes in and failures of a reference voltage of an analog to digital (A/D) converter. A non-scalar function of the reference voltage of the A/D converter can be determined and output to the A/D converter. The A/D converter is configured to output a digital value to the A/D conversion system, wherein the digital value corresponds to the non-scalar function of the reference voltage. The A/D conversion system decodes the non-scalar function of the reference voltage with a corresponding inverse function, and may determine the drift factor associated with the reference voltage. The A/D conversion system can report a change in, or a failure of, the A/D converter or its reference voltage, and can operate or prevent operation of protection elements.

Abstract: An integrated circuit (IC) includes an analog-to-digital converter (ADC). The ADC includes an ADC core circuit integrated in the IC to receive an analog signal, to convert the analog signal to a digital signal in response to a trigger signal. The ADC core circuit further provide the digital signal as an output of the ADC. The ADC further includes internal trigger circuitry integrated in the ADC to provide the trigger signal to the ADC after a prescribed delay period has expired.

Abstract: A modified topology for a CTDSM (referred herein as “SCFF”) can effectively deal with signal transfer function (STF) peaking, an inherent property of continuous time feedforward delta sigma converters. The SCFF approach involves providing an additional digital-to-analog (DAC) feedback path to the input of the second integrator (incurring an additional DAC in the circuitry, converting the output of the quantizer into an analog signal and feeding the analog signal to the input of the second integrator). Furthermore, the SCFF approach involves providing two feed-ins: a first feed-in to the input of the second integrator and a second feed-in to the input of the third integrator. The first feed-in can be negative. Advantageously, the modified continuous time delta sigma modulator implementing this approach alleviates some of the peaking issues in the signal transfer function while still enjoy low power consumption.

Abstract: A processor includes an execution unit to decode compressed data. The execution unit includes a code information array, a matching logic unit, a code value generator, and a decoder. The code information array includes a pre-computed code length counter and a pre-computed last code. The matching logic unit includes logic using the code information array to match a segment of a payload of the compressed data with a matching code length and a matching code index. The code value generator includes logic to translate the matching code index into a code value. The decoder includes logic to generate decompressed data from the code value and the matching code length.

Abstract: Real-time reduction of CPU overhead for data compression is performed by a processor device in a computing environment. Non-compressing heuristics are applied on a randomly selected data sample from data sequences for determining whether to compress the data sequences. A compression potential is calculated based on the non-compressing heuristics. The compression potential is compared to a threshold value. The data sequences are either compressed if the compress threshold is matched, compressed using Huffman coding if Huffman coding threshold is matched, or stored without compression.

Abstract: Data records may be managed in a relational database by monitoring, a record length for a first data record in a page of memory, an amount of free space in the page, and a page length. In response to receiving an operator command to replace the first data record with a second data record, a database management system may determine whether an estimated record length of a compressed second data record is outside of the amount of free space in the page. In response to determining the estimated record length of a compressed second data record is outside of the amount of free space in the page, the database management system may determine whether an estimated length of a compressed page is outside of the page length. In response to determining the estimated length of a compressed page is within the page length, the page may be compressed.

Abstract: Methods and apparatus for wireless communication in a wireless communication network include determining a transmit data packet size at a transmitting device and computing an early termination scheme associated with a receiving device. Aspects of the methods and apparatus include increasing a transmission length of a Cycle Redundancy Check (CRC) field associated with the transmit data packet before transmission of the transmit data packet, wherein the transmitted length of the CRC field is based on the early decoding scheme. Aspects also include transmitting the transmit data packet with the increased transmission length of the CRC field to the receiving device.

Abstract: An FEC codeword comprises channel information indicating the reliability of the information contained by the FEC codeword. The channel information can be used to generate an initial error channel estimate. Based on the initial error channel estimate, an FEC decoder can decode the FEC codeword to increase the reliability of the information contained by the FEC codeword. According to the present disclosure, a method and system of decoding comprises: comparing a current codeword to a previous codeword in order to identify bits corrected between the previous and current codewords; revising an error channel estimate based on the identified corrected bits, the revised estimate representing a change in the error channel over time; and decoding the codeword based on the revised error channel estimate.

Abstract: A method and apparatus as described herein provide a novel modification to any iterative FEC decoder method that can improve FER performance in the error floor region. Many iterative FEC methods, such as commonly used LDPC decoders, have error floors where the performance of the decoder does not improve below a certain threshold. Error Floors are caused by trapping sets from which traditional methods cannot escape. With Stochastic Floor Mitigation, according to embodiments of the present disclosure, noise is strategically added to the operations occurring during decoding resulting in significantly improved error floor performance.

Abstract: A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to “0” and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a predetermined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the predetermined column among one or more column(s) of the parity check matrix.

Abstract: Provided is an apparatus for designing a quantum code, which includes an analyzing unit for analyzing at least one quantum error generated in a quantum error channel as at least one binary error by using a standard form codeword stabilized quantum (CWS) code, a code generating unit for generating a binary error-correcting code which corrects the at least one binary error, a word operator generating unit for generating at least one word operator of the CWS code by using the at least one binary error-correcting code, and a codeword generating unit for generating at least one codeword including at least one entangled qubit (ebit) by using the at least one word operator.

Abstract: In one embodiment, a method includes loading first data into a first buffer of an interposer during a first time period and loading second data into a second buffer of the interposer and performing a first decoding operation on the first data using a first decoder during a second time period. The method includes loading third data into a third buffer of the interposer, performing the first decoding operation on the second data using the first decoder, and performing a second decoding operation on the first data using a second decoder during a third time period. Moreover, the method includes loading fourth data into a fourth buffer of the interposer, performing the first decoding operation on the third data using the first decoder, and performing the second decoding operation on the second data during a fourth time period. The first and second decoding operations are C1 or C2 decoding operations.

Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

Abstract: The present invention provides a design framework that is used to develop new types of constrained turbo block convolutional (CTBC) codes that have higher performance than was previously attainable. The design framework is applied to design both random and deterministic constrained interleavers. Vectorizable deterministic constrained interleavers are developed and used to design parallel architectures for real time SISO decoding of CTBC codes. A new signal mapping technique called constrained interleaved coded modulation (CICM) is also developed. CICM is then used to develop rate matching, spatial modulation, and MIMO modulation subsystems to be used with CTBC codes and other types of codes. By way of example, embodiments are primarily provided for improved 5G LTE and optical transport network (OTN) communication systems.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame.

Abstract: A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.

Abstract: According to one embodiment, a memory controller includes an encoding unit that generates a first code word, a duplication unit that duplicates the first code word, a memory interface that writes a code word group including the first code word and code words being duplicates of the first code word into a non-volatile memory, and reads the code words forming the code word group from the non-volatile memory, a determination unit that obtains a result of majority decision using the first code word and the plurality of code words, which are included in the code word group read from the non-volatile memory, and a decoding unit that decodes a code word being the result of the majority decision and corrects an error.

Abstract: Systems and methods are provided for decoding a codeword having a first codeword length using a decoding system. The systems and methods include receiving a vector corresponding to the codeword at the decoding system, wherein the decoding system comprises a first decoder and a second decoder, the first decoder is available to concurrently process codewords up to the first codeword length, and the second decoder is available to concurrently process codewords up to a second codeword length. The systems and methods further include determining that the received vector is to be decoded using the second decoder, partitioning the received vector of the first codeword length into a plurality of segments having a size no larger than the second codeword length, and decoding the plurality of segments using the second decoder.

Abstract: The present application describes a computer-implemented method for configuring a front end including sweeping a first tone through the frequency band of the receive channel; receiving a first signal and a second signal containing interference; characterizing the receive channel using the first tone; processing the compensated first signal using an infinite impulse response filter based on the characterized receive channel to generate an interference cancelling signal; and coupling the interference cancelling signal to the second signal to generate an interference cancelled receive signal.

Abstract: A wireless communication method is provided. This method includes: selecting one of a plurality of predetermined frequency bands each time a switch operation is manually performed in a transmitter, and then using the selected frequency band to transmit a radio signal corresponding to the switch operation for a predetermined specified transmission time; in a receiver apparatus, receiving the transmitted wireless signal, and then recognizing the content of a command that has already been assigned in accordance with the switch operation; and defining an intermittent reception standby period, which is repeated at a predetermined cycle for each of the frequency bands.

Abstract: The invention relates to a telecontrol (TEL) for the locking/unlocking and the starting of a motor vehicle comprising: —an electronic circuit (ELEC) comprising at least one pathway comprising an input pin (BE) and an output pin (BS), —a first radiofrequency antenna (ANT1) comprising a first loop disposed in the plane of the electronic circuit (ELEC), —a second radiofrequency antenna (ANT2) comprising a second loop disposed in the plane of the electronic circuit (ELEC), said second antenna (ANT2) comprising: —an input connector (CE) connected to the input pin (BE), —an output connector (CS) connected to the output pin (BS), —a tuning capacitor (C) linked to the electronic circuit (CIRC), for tuning the second antenna (ANT2) to a tuning frequency, characterized in that it comprises: —an inductive input component (COMP_E) placed between the input connector (CE) and the input pin (BE), and/or —an inductive output component (COMP_S) placed between the output connector (CS) and the output pin (BS).

Abstract: The present invention provides a compound transmitter having power efficiency characteristics and distortion characteristics superior, over a wide band, to those of a Doherty transmitter, and having fewer elements constituting an RF circuit. The present invention is therefore provided with a compound amplifier (201) for generating a signal (z) (efficiency improving signal) obtained by the amplitude modulation of a carrier signal from an RF modulation signal (a) (main signal); power-modulating, using two power amplifiers (50, 51), a signal (S1) obtained by adding together (a) and (z), and a signal (S2) obtained by subtracting (z) from (a); and setting, as a transmitter output point, the point (p1) where the respective outputs are combined via impedance inverters (60, 61), the efficiency improving signal (z) being generated under conditions in which the size of the envelope of either (S1) or (S2) is fixed.

Abstract: An aviation transponder system comprising a permanently-mounted antenna, a permanently-mounted receiver module comprising a receiver, a signal splitter, and an external connector, and a portable receiver module, wherein a signal received on the permanently-mounted antenna is passed to the signal splitter of the permanently-mounted receiver module, wherein the signal splitter splits the signal such that the signal is sent to both the receiver and to the external connector, and wherein the portable receiver module is connected to the external connector, whereby the permanently-mounted antenna is used by the receiver of the permanently-mounted receiver module and fed through the permanently-mounted receiver module and made available to the portable receiver module through the external connector.

Abstract: Devices and methods related to packaging of radio-frequency (RF) devices on ceramic substrates. In some embodiments, a packaged electronic device can include a ceramic substrate configured to receive one or more components. The ceramic substrate can include a conductive layer in electrical contact with a ground plane. The packaged electronic device can further include a die having an integrated circuit and mounted on a surface of the ceramic substrate. The packaged electronic device can further include a conformal conductive coating implemented over the die to provide shielding functionality. The packaged electronic device can further include an electrical connection between the conformal conductive coating and the conductive layer.

Abstract: A radio waves guiding window for a metal case is capable of transmitting radio waves smoothly and contains: a metal case. The metal case includes a modification area defined at a position thereof where corresponds to an antenna, wherein a metal material thickness is formed by ceramizating the modification area in a micro-arc oxidation (MAO) process, and a metal material of the modification area is modified to a metal oxide in the micro-arc oxidation (MAO) process. Accordingly, the metal case has brilliant appearance, transmits the radio waves smoothly, and is simplified.

Abstract: A method, system, and device provide power-efficient communications within the context of available power. Transmission and receipt data rates are scalable in accordance with output power available from a power source. Data is transmitted at a data rate determined, at least in part, by the available output power.

Abstract: A method and apparatus for providing information about a plurality of wireless charging pads to an electronic device such that the electronic device performs wireless charging efficiently is provided. The method includes receiving information about the plurality of wireless charging pads and displaying the information about the plurality of wireless charging pads on a screen of the electronic device.

Abstract: An accessory includes a case body, a cover unit, and first and second coupling units. The case body is formed with a receiving space for receiving a portable electronic device. The cover unit is configured to be coupled removably to the case body for closing and opening the receiving space. The first coupling unit includes a data and charge connector for mating electrical connection with a data and charge socket of the portable electronic device, and a data and charge port connected to the data and charge connector. The second coupling unit includes a connector jack for mating electrical connection with an audio socket of the portable electronic device, and an audio port connected to the connector jack.

Abstract: An apparatus is provided in one example embodiment and includes a motor, a first endless belt encircling a first pair of spaced apart shafts, a second endless belt encircling a second pair of spaced apart shafts, a drive element connecting the motor to one shaft each of the first pair of shafts and the second pair of shafts, and a continuous strip of film having a first end and a second end attached to the first endless belt and the second endless belt respectively. The motor activates the drive element to rotate one shaft each of the first pair of shafts and the second pair of shafts causing the belts to rotate, unwinding the film from the first endless belt and winding it on the second endless belt.

Abstract: The embodiment relates to a case apparatus including antenna elements, a shielding member interposed between the antenna elements and a protective part to encapsulate and couple the antenna elements and the shielding member. Even when the case apparatus is mounted on a mobile communication terminal, a near field communication between the mobile communication terminal and an external device is smoothly performed.

Abstract: A system that incorporates teachings of the present disclosure may include, for example, a matching network including a tunable reactance circuit configured to be coupled to at least one of a transmitter portion and a receiver portion of a communication device, where the tunable reactance circuit is adjustable to a plurality of tuning states, and where the determination of a tuning state is based on whether detected signal measurements are determined to be invalid and is based on information from at least one of an open-loop or closed-loop feedback configuration of the tunable reactance circuit. Additional embodiments are disclosed.

Abstract: A system and method to produce an electric network from estimated line impedance and physical line length among smart meter devices is provided using communication between the smart meters. The smart meters: (1) synchronize time using GPS pps signals, which provide an accurate time stamp; (2) send/receive an identifiable signal through the same phase of electric networks; (3) identify other smart meters on the same phase lines by listening to the information signal on the same phase lines; and (4) calculate time-of-arrival of an identifiable signal from other smart meters. The time of arrival information is used to calculate the line length, which is then used to calculate impedance of a line and topology of the electric network. The system then constructs an electric network by combining geo-spatial information and tree-like usual connection information.

Abstract: The present invention relates generally to addressing performance issues in xDSL communication systems, and more particularly to methods and apparatuses to measure and characterize CM noise impacting a DSL line in a customer premises, measurements and characterization of the projection of these CM signals in Differential Mode (DM), and finally a derivation of an estimate of the loop balance.

Abstract: Aspects of the subject disclosure may include, for example, a transmission device that includes a first coupler that guides a first electromagnetic wave to a first junction to form a second electromagnetic wave that is guided to propagate along the outer surface of the transmission medium via one or more guided-wave modes. These mode(s) have an envelope that varies as a function of angular deviation and/or longitudinal displacement. Other embodiments are disclosed.

Abstract: In one embodiment, a circuit, having a single supply, is provided to transmit a wireless signal with low common mode electromagnetic interference (EMI) emission. The circuit can achieve common mode attenuations of 40 dB or greater as a result of the symmetric built circuit. Also included is a system that includes a transmission circuit and a receiver circuit, and a method of using such a system.

Abstract: An example of information processing system includes a storage device; and an information processing device for performing near field communication with the storage device. The storage device includes a storage unit storing application data usable in a predetermined application program and shared data usable in an application program regardless of whether the application program is the predetermined application program. The information processing system receives an instruction regarding data read and/or data write from/to the storage device from an application program to be executed by the information processing device. Under the condition that the instruction is from the predetermined application program, the application data is passed to the predetermined application program. Regardless of whether the instruction is from the predetermined application program, the shared data is passed to the application program that issued the instruction.

Abstract: The present invention discloses a tag identification method and apparatus, relates to the field of communications network technologies, which can implement that there are few steps of determining a format of a tag by a device host in an NFC terminal, so that the tag can be quickly processed. In the embodiments of the present invention, a Near Field Communication NFC controller reads a type of a tag; the NFC controller determines whether a format of the tag is an NFC data exchange format NDEF according to the type of the tag; and the NFC controller sends a notification message to a device host when the NFC controller determines that the format of the tag is the NDEF, where the notification message includes that the format of the tag is the NDEF. The solutions provided in the embodiments of the present invention are applicable to identifying a tag.