Abstract: A system of solar PV strip modules and method of use designed to integrate with vertical structures such as poles. The system and method use articulated semi-rigid solar PV strip modules and components with elastic characteristics to enable a high static-friction attachment to the structure. The static friction exceeds the force of gravity, enabling the solar PV strip modules to remain in place upon the vertical structure. The PV strip modules can have a rectangular shape or any other shape that enables customized or variable modular assembly and attachment to the structure.

Abstract: A photovoltaic module includes: a solar cell module including a plurality of solar cells; a junction box including a dc/dc converter unit to convert the level of DC power supplied from the solar cell module; a plate on one surface of the solar cell module and disposed between the solar cell module and the junction box; and a coupling member attaching and detaching the junction box from the solar cell module.

Abstract: A resonator includes: a resonator element including a quartz crystal substrate that includes a first area performing a thickness-shear vibration and a second area with a thickness thinner than the first area and located around the first area; and a base substrate to which the second area of the resonator element on one edge side thereof is attached via a bonding material. The quartz crystal substrate has a major surface that is a surface including an X-axis and a Z?-axis, and has a thickness in a direction along a Y?-axis. The resonator satisfies the relation: 1.5×??Xp where Xp is the maximum length of an area of the second area where the bonding material is bonded along the X-axis in a plan view and ? is the wavelength of a flexural vibration occurring in the quartz crystal substrate.

Abstract: An injection locked frequency divider is disclosed. The injection-locked frequency divider includes a sub-harmonic injection-locked oscillator, a reference clock divider, a counter, and a variable load resistor control unit. The sub-harmonic injection-locked oscillator has variable load resistors that are adjusted in response to a resistance adjustment signal, and, when oscillation frequency determined based on the magnitudes of the variable load resistors is a sub-harmonic of an injection signal, outputs signals having the oscillation frequency as divided output signals. The reference clock divider generates a count-enable signal from a reference clock signal according to a reference division ratio. The counter generates divided output count signals based on the divided output signals in response to the count-enable signal.

Abstract: Certain aspects of the present disclosure provide techniques and circuits for frequency mixing signals. One example circuit generally includes a transformer comprising a primary winding and a secondary winding, the transformer configured to generate a signal across the secondary winding based on a signal at an input node coupled to the primary winding, and a first mixer coupled to the secondary winding of the transformer and configured to convert a frequency of the signal across the secondary winding. In certain aspects, the circuit also includes a biasing circuit having an output coupled to a tap of the secondary winding and configured to generate a biasing voltage by applying an offset voltage to a common-mode voltage of the first mixer and apply the biasing voltage to the tap of the secondary winding to bias the first mixer.

Abstract: An apparatus includes a cascode amplifier. The cascode amplifier includes a first transistor and a second transistor. The cascode amplifier is configured to receive a first bias voltage, a second bias voltage, and a signal. The cascode amplifier is also configured to amplify the signal based at least on the first bias voltage and the second bias voltage. The apparatus also includes a first feedback module and a second feedback module. The first feedback module is configured to adjust the first bias voltage based at least on the amplified signal. The second feedback module is configured to adjust the second bias voltage based at least on a voltage distribution across the first transistor and the second transistor. A system and method for maintaining cascode amplifier performance are also provided.

Abstract: An amplifying device includes an amplifying element that amplifies a fundamental wave signal, and a short stub that has an electric length one fourth a wavelength of the fundamental wave signal, and is connected to a line on an output side of the amplifying element, the short stub being used as both a bias circuit that supplies a certain bias voltage to the amplifying element and a reflection circuit with respect to a harmonic signal that has a frequency twice a frequency of the fundamental wave signal, wherein the short stub has a pattern width that is larger than a pattern width of the line.

Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.

Abstract: A system for amplifying a signal with active power management according to one embodiment includes a first digital to analog converter (DAC) circuit configured to provide a modulated carrier signal; a amplifier circuit coupled to the first DAC, where the amplifier circuit is configured to amplify the modulated carrier signal; an output stage circuit coupled to the amplifier circuit, where the output stage circuit is configured to provide the amplified signal to a network; a second DAC circuit configured to provide a full wave rectified envelope of the modulated carrier signal; and a switching regulator circuit including a voltage reference input coupled to the second DAC circuit, where the switching regulator circuit is configured to provide a supply voltage to the output stage circuit and the supply voltage is modulated in response to the envelope received at the voltage reference input.

Abstract: A method is for reducing power dissipation in a switching amplifier. The method may include comparing a load current with a ripple current and, if the load current is greater than the ripple current, then detecting a first potential value at a first output terminal of the switching amplifier, detecting a second potential value at a second output terminal of the switching amplifier, detecting a third potential value between first and the second terminals of a first capacitor, and coupling the first terminal of the first capacitor to one of the first output terminal and the second output terminal. The second terminal of the first capacitor may be coupled to a reference voltage, the first output terminal, or the second output terminal based upon whether the first potential value or the second potential value is equal to the third potential value.

Abstract: A power amplifier may include a first amplifying unit receiving a first bias signal to amplify a power level of an input signal; an envelope detecting unit detecting an envelope of the input signal; a comparing circuit unit comparing a peak value of the detected envelope with a preset reference voltage; and a second amplifying unit amplifying the power level of the input signal according to a second bias signal set depending on a comparison result of the comparing circuit unit.

Abstract: A first amplifier is coupled to an output node via a first line having first and second portions. A second amplifier is coupled to the output node via a second line having first and second portions. An auxiliary amplifier is coupled via an auxiliary line network to a first intersection between the first and second portions of the first line, and to a second intersection between the first and second portions of the second line. For each of the first and second lines, the first and second portions have a higher-impedance portion and a lower-impedance portion whose combined length is a half wavelength. Lengths of the respective first portions of the first and second lines sum to half a wavelength, and the lengths of the respective second portions of the first and second lines sum to half a wavelength.

Abstract: A Doherty amplifier for amplifying an input signal to an output signal, the Doherty amplifier comprising: a main amplifier for receiving a first signal and for amplifying the first signal to generate a first amplified signal; a first peak amplifier for receiving a second signal and for generating a second amplified signal, the first peak amplifier only operating when the second signal has reached a first threshold power, the first and second signal split from the input signal; and output circuitry to combine the first and second amplified signals to generate an output signal having an operating bandwidth, the output circuitry comprising inductors arranged in the format of a branch line coupler, the inductors coupled to the output parasitic capacitances of the main and peak amplifier.

Abstract: The feed reflected Doherty amplifier utilizes the output characteristics of the carrier amplifier to control the input signal of the peaking amplifier to improve the gain, linearity and efficiency of a Doherty amplifier. The feed reflected Doherty amplifier comprises an input power splitter, a carrier amplifier branch and a peaking amplifier branch combined into a common load, an output directional coupler and an input directional coupler connected via a phase shift element.

Abstract: A power converter may include a power inductor, a plurality of switches arranged to sequentially operate in a plurality of switch configurations, an output for producing the output voltage, wherein a first switch is coupled to a first output terminal of the output and a second switch is coupled to a second output terminal of the output, and a linear amplifier coupled to the output. The controller may be configured to, in a linear amplifier mode of the power stage, enable the linear amplifier to transfer electrical energy from an input source of the power stage to the load, and in at least one mode of the power stage other than the linear amplifier mode, sequentially apply switch configurations from the plurality of switch configurations to selectively activate or deactivate each of the plurality of switches in order to transfer the electrical energy from the input source to the load.

Abstract: A single or multistage signal predistorter includes an input coupled to receive an information signal comprising input samples and an output coupled to the high power amplifier, the signal predistorter configured to receive an input sample, generate a distortion sample based on an estimate of nonlinearity of the high power amplifier at an operating saturation level, modify the input sample with a correction term to generate a predistortion signal, wherein the correction term is proportional to the distortion sample, and further wherein the predistortion signal comprises the information signal modified to account for nonlinearities in the high power amplifier.

Abstract: A circuit includes a differential input stage amplifier that receives a differential input voltage and generates an output voltage based on a difference in the differential input voltage. A feedback loop provides feedback from an output of the differential input stage amplifier to input tail current of the differential input stage amplifier. The feedback loop enables class AB operation of the differential input stage amplifier. At least one gain reducer is operatively coupled to the feedback loop to reduce the gain of the feedback loop. The gain reducer has a resistance value that varies inversely proportional to loop current in the feedback loop to reduce the gain of the feedback loop as loop current increases.

Abstract: A direct current (DC)-DC converter, which includes a charge pump buck power supply and a buck power supply is disclosed. The charge pump buck power supply includes a charge pump buck converter, a first inductive element, and an energy storage element. The charge pump buck converter and the first inductive element are coupled in series between a DC power supply, such as a battery, and the energy storage element. The buck power supply includes a buck converter, a second inductive element, and the energy storage element. The buck converter and the second inductive element are coupled in series between the DC power supply and the energy storage element. As such, the charge pump buck power supply and the buck power supply share the energy storage element.

Abstract: A differential power amplifier has at least an input stage and an output stage. A first output stage amplifier is configured to receive a first portion of a differential signal from the input stage at a first output stage input and provide a first amplified signal at a first output stage output. The second output stage amplifier is configured to receive a second portion of the differential signal from the input stage at a second output stage input and provide a second amplified signal at a second output stage output. Power limiter circuitry is connected to the first and/or output stage inputs and is configured to limit a power level of the differential signal prior to being received at the output stage, such that the differential power amplifier and associated filters are not damaged, while the nominal performance of the differential power amplifier at rated power is not significantly affected.

Abstract: There is disclosed a method for controlling a power amplifier capable of utilizing nonlinearity correction in a nearly steady operation status of non-linearity correction, in a periodical fast switching system in time domain. The method may comprise receiving a periodic switch signal indicating switch time of the periodical fast switching system; and providing, based on the periodic switch signal, a pre-bias signal with a pre-determined voltage amplitude to the power amplifier for a pre-determined time period before each downlink time slot to preheat a transistor of the power amplifier so as to compensate a temperature change of a die inside the transistor.

Abstract: Disclosed are systems implementing an implicit Feed-Forward Compensated (FFC) op-amp, where the main FFC port is realized by the P-side of the CMOS input structure of the 2nd and 3rd stages of the op-amp, while the main signal path is through the N-side. According to some embodiments, to balance the relative strengths of the main path and feed-forward paths, the 2nd-stage NMOS input pair is split into two pairs, one is used to route the main path while the other is used for auxiliary FFC. The disclosed implicit FCC op-amp is unconditionally stable with adequate phase lead. According to some embodiments, the disclosed op-amp, which may be a wide-band op-amp, can be used in highly linear applications operative at intermediate frequency (IF), such as signal buffers for high-performance data converters or radio-frequency (RF) modulators and demodulators, continuous-time (CT) filters or sigma-delta data converters.

Abstract: The present invention provides a method and an apparatus for exchanging control functions of volume control units, and a terminal, which relate to the field of communications technologies and can make it more convenient for a user to adjust volume. The method includes: obtaining current placement status information of the terminal, where the placement status information is used to indicate a current placement status of the terminal, and at least two volume control units are disposed in the terminal; and exchanging volume control functions of the at least two volume control units when the current placement status of the terminal deviates from a normal placement status of the terminal, where the at least two volume control units include a volume control unit whose volume control function is to control volume to increase and a volume control unit whose volume control function is to control volume to decrease.

Abstract: The present technique relates to a sound processing apparatus, a sound processing method, and a program which are configured to obtain higher quality sound. In order to obtain an objective characteristic, the sound processing apparatus previously holds a characteristic of the sound processing apparatus, generates an inverse characteristic filter of the characteristic of the sound processing apparatus, and generates a correction filter from the obtained filter and a filter having the objective characteristic. The sound processing apparatus uses the generated correction filter to subject a sound signal to be reproduced to filter processing, and reproduces sound based on the obtained sound signal. Therefore, a characteristic to be originally obtained can be achieved. The present technique can be applied to the sound processing apparatus.

Abstract: The invention is directed to synthesizing a personalized audio equalization filter based on an individual's hearing profile when listening to audio signals using a preferred electronic means of transduction and production of the audio signals through headphones, earphones, or loudspeakers and is presented in two steps. In the first step, the deviation of the listener's hearing profile, when the preferred listening device is donned, is measured and recorded relative to predetermined equal-loudness contours (e.g., ISO standard equal-loudness contours). The hearing profile is used to compute an equalization filter such that when the audio signal to be reproduced is played through the filter, the equal-loudness contour for a specified phon level is restored. Thus, the invention compensates for deviations of the user's listening device, the user's own hearing profile from a standard hearing profile that represents natural hearing, and other factors.

Abstract: Provided is an LC composite component having a multi-layer substrate, a pattern coil, and a chip capacitive element. The multi-layer substrate is configured such that insulating layers are stacked. The pattern coil forms a coiled shape of which the coil axis extends along a stacking direction of the multi-layer substrate, and includes a coil conductor disposed between the insulating layers. The chip capacitive element includes a ceramic body having a relative permittivity higher than that of the insulating layers and counter electrodes. The chip capacitive element is at least partially disposed within the pattern coil.

Abstract: Disclosed herein is a thin film type common mode filter including: a base substrate made of an insulating material; a first insulating layer formed on the base substrate; a coil-shaped internal electrode formed on the first insulating layer; a second insulating layer formed on the internal electrode; an external electrode terminal having a vertical section connected to a side surface of the internal electrode and a horizontal section extended from an upper end of the vertical section toward a horizontal direction to thereby form a parallel surface spaced apart from the internal electrode by a predetermined distance; and a ferrite resin layer formed between the horizontal section of the external electrode terminal and the internal electrode.

Abstract: A filter device for filtering electrical currents or electromagnetic interference, particularly common-mode interference. The filter device has a soft-magnetic core with a passage, a printed circuit board with a plurality of electronic components, and a holding section. The holding section of the printed circuit board can be put through the core passage wherein the passage is designed such that the holding section and the electronic components arranged on the holding section can be put through the passage.

Abstract: Methods and systems for phase shifting include a hybrid quadrature coupler having an input, an output, and two termination loads. Each termination load includes multiple terminations, each termination having a varactor; and one or more transmission lines separating the terminations. A control module is configured to determine a phase shift and gain to apply to the input and to independently control a capacitance of each varactor such that the output of the hybrid quadrature coupler is shifted by the determined phase shift relative to the input with the determined gain.

Abstract: A subsea broadcast serial bus system includes a broadcast serial bus having a first signal line and a second signal line. One or more nodes are connected in parallel to the first signal line and the second signal line of the broadcast serial bus. Each node connects the first signal line to the second signal line via a node impedance. A subsea node connected to the broadcast serial bus includes an adjustable impedance that may be adjusted based on the number of nodes connected to the broadcast serial bus.

Abstract: An antenna system including a signal source, at least one antenna coupled to the signal source, a matching circuit connected to the signal source at a first port and to the at least one antenna at a second port and operative to match the at least one antenna to the signal source, the matching circuit having a characteristic impedance with respect to the first port and the second port, real and imaginary parts of the characteristic impedance not being defined by the Hilbert transform.

Abstract: A solidly mounted resonator (SMR) includes an acoustic resonator on a substrate, the acoustic resonator having multiple acoustic impedance layers having different acoustic impedances, respectively. The SMR further includes a bottom electrode on a top acoustic impedance layer of the plurality of acoustic impedance layers, a piezoelectric layer on the bottom electrode, a top electrode on the piezoelectric layer, and multiple lateral features on a surface of the top electrode. The lateral features include multiple stepped structures.

Abstract: An electronic component includes: an oscillation circuit that is electrically connected to a resonator element; and a substrate that includes a first surface on which the oscillation circuit and wiring that is electrically connected with the resonator element and the oscillation circuit to form an oscillation loop are disposed, and a second surface opposite to the first surface. The substrate includes a conductor layer between the first surface and the second surface. The conductor layer overlaps the wiring in a plan view. A distance between the wiring and the conductor layer in a thickness direction as a direction along a direction intersecting the first surface and the second surface is from 0.35 mm to 0.7 mm.

Abstract: An RF component can have a reduced electromagnetic internal coupling and may be suitable for miniaturization as a result. The component includes a micro acoustic filter of ladder-type design in a housing and a double coil having a first coil segment and a second coil segment. The two coil segments are oriented in opposite directions. The two coil segments are arranged without crossover in one layer and the double coil is arranged in proximity to a parallel branch resonator of the ladder-type filter structure.

Abstract: A duplexer includes an antenna terminal, a transmission amplifier terminal and a reception amplifier terminal. The transmission amplifier terminal is coupled to the antenna terminal via a transmission filter. The reception amplifier terminal is coupled to a reception filter and the reception filter is coupled to the antenna terminal via a band-stop filter.

Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.

Abstract: A discrete time (DT) lowpass filter having various advantages is described. In an exemplary design, the DT lowpass filter includes a decimating DT filter (which may include a passive DT FIR filter and/or a passive DT IIR filter) and an active DT filter. The decimating DT filter receives a first DT signal at a first sample rate, filters and decimates the first DT signal by a factor of N, and provides a second DT signal at a second sample rate lower than the first sample rate. N may be greater than one. The active DT filter filters the second DT signal and provides a third DT signal at the second sample rate. A sampler samples a continuous time signal and provides the first DT signal. The sampler may further double the voltage of the first DT signal relative to the voltage of the continuous time signal.

Abstract: A method of operating a single-tuner radio includes tuning into a first frequency. A pause in a first signal associated with the first frequency is detected. Tuning is switched from the first frequency to a second frequency. A signal quality metric for the second frequency is measured. Tuning is switched from the second frequency to the first frequency.

Abstract: An active clamp current sink is used to voltage protect a low voltage rated, high power current sink that drives illumination current through a string of serially connected LEDs. When the LEDs are turned off as part of a PWM configuration, the forward voltage on the LEDs falls, and the voltage presented to the low voltage rated, high power current sink rises. The active clamp current sink monitors the voltage across the high power current sink and ensures that an adequate current flows through the LEDs. This minimally adequate current maintains a sufficiently large forward voltage through the LEDs, and therefore a sufficiently small voltage is presented to the high power current sink.

Abstract: An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles Of the clock signal, the buffer is automatically powered up.

Abstract: A power converter driver that is supplied with two different voltages.

Abstract: A voltage regulator includes a pass element, a buffer, and an error amplifier. The voltage regulator further includes a fast push-pull driver that has an inverter type amplification structure, is connected between a power output and a control input of the pass element, and reduces positive and negative peaks of the power output at a speed faster than a speed of a main feedback loop.

Abstract: The invention detects the difference between the maximum signal and the minimum signal at each of a plurality of cycles separately when a sine wave is received. All differences are summed for generating a single detected signal for suppressing the interference of low-frequency noise. No synchronization with the sine wave is necessary and the detection can start at any phase of the sine wave.

Abstract: A circuit for reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is described. The circuit also comprises a plurality of circuit elements that enable the routing of data generated at outputs of the circuit elements; a plurality of register circuits that store data at outputs of the plurality of circuit elements; a clock circuit routing a clock signal to clock inputs of the plurality of register circuits; and a pulsed-controlled register circuit coupled to an output of a circuit element and generating a pulsed output coupled to a clock input of a register of the pulse-controlled register circuit; wherein the pulsed output is coupled to the clock input of the register to enable the pulse-controlled register circuit to store data at a time that is different than an edge of the clock signal. A method of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is also described.

Abstract: An exemplary level shifter includes a clock level shifter configured to generate a level shifted clock signal from an input clock signal; and a switched capacitor logic controller coupled to the clock level shifter. The switched capacitor logic controller is configured to steer the level shifted clock signal based on a data signal and the input clock signal, providing a level shifted version of the data signal.

Abstract: The present invention provides a level conversion circuit. The circuit is as follows: A cathode of a first equivalent diode is connected to a reference voltage, and an anode of the first equivalent diode is separately connected to a gate of a first switching transistor and a first end of a first capacitor; a second end of the first switching transistor and a first end of a second switching transistor are connected together; a second end of the second capacitor is separately connected to a cathode of a second equivalent diode and a gate of the second switching transistor; and a second end of the second switching transistor is grounded, and an anode of the second equivalent diode is connected to a reference voltage.

Abstract: Apparatus, computer readable medium, circuits, and method of reducing power in sending signals over two or more wires are disclosed. The method includes receiving two or more signals at a first end of the two or more wires. The method includes determining that the two or more signals should be encoded based at least on a previously received two or more signals. The method includes encoding the two or more signals. Additionally, the method includes sending the encoded two or more signals over the two or more wires. The method may include receiving the sent two or more signals at a second end of the two or more wires, and if the sent two or more signals were encoded, then decoding the two or more signals back to the values of the received two or more signals.

Abstract: Provided are an output buffer circuit having an amplifier offset compensation function and a source driving circuit including the output buffer circuit. The output buffer circuit may include a plurality of channel amplifiers, each of which is configured to adjust an amount of current flowing through transistors connected to at least one of a non-inverted input terminal and an inverted input terminal of a differential input unit to compensate an amplifier offset, and adjust buffer input voltage signals to generate output voltage signals.

Abstract: In various embodiments, a printed circuit arrangement may be provided. The printed circuit arrangement may include a processor circuit. The printed circuit arrangement may further include a printed main circuit arrangement in electrical connection with a first input node of the processor circuit. The printed main circuit arrangement may be configured to receive at least one input signal and generate a main circuit signal based on the at least one input signal after a first delay from receiving the at least one input signal. The printed circuit arrangement may further include a printed reference circuit arrangement in electrical connection with a second input node of the processor circuit. The printed reference circuit arrangement may be configured to receive a further input signal, may have a second delay and may be configured such that the second delay adapts to the first delay.

Abstract: Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.