Abstract: A capacitive parametric zero crossing detection circuit has a nonlinear voltage controlled capacitive device coupled to an input voltage to convert a zero crossing current pulse into zero crossing voltage signal.

Abstract: A power supply apparatus including: a boost converter configured to generate a power supply voltage to drive to a load circuit from a voltage received from a voltage generation unit; an oscillator configured to receive the minute voltage, and to generate an alternating current signal; and a signal conversion circuit which further includes a half-wave generation circuit configured to receive the alternating current signal, and to generate a half-wave signal of a high potential side or a low potential side, and at least one inverter configured to receive the generated half-wave signal, and to generate a pulse signal; wherein the boost converter is driven by the pulse signal output from the signal conversion circuit in order to generate the power supply voltage.

Abstract: A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.

Abstract: Apparatus and methods for controlling radio frequency (RF) switches are disclosed. Provided herein are apparatus and methods for controlling RF switches. In certain configurations, an RF system includes a charge pump for generating a charge pump voltage, an RF switch, a level shifter for turning on or off the RF switch, and a level shifter control circuit for controlling the level shifter. The charge pump receives a mode signal used to enable or disable the charge pump. Additionally, the level shifter receives power in part from the charge pump voltage, and controls the RF switch based on a switch enable signal. The level shifter control circuit receives the mode signal and biases the level shifter with a bias voltage that changes based on a state of the mode signal.

Abstract: First and second external terminals are connected to high-voltage and low-voltage terminals, respectively, of a direct-current voltage source circuit in which first and second direct-current voltage sources are connected in series. A third external terminal is connected to a connecting point between the first and second direct-current voltage sources. A first switching element is connected between the first and fourth external terminals. A second switching element is connected between the fourth and second external terminals. A first AC switch unit includes third and fourth switching elements connected in inverse series between the third and fourth external terminals. A second AC switch unit includes fifth and sixth switching elements connected in inverse series between the third and fourth external terminals. The first and second AC switch units are connected in parallel. The first and second switching elements and the first and second AC switch units are incorporated in one module.

Abstract: A gate pulsing gate ladder circuit includes a series connected resistor ladder with bond pads connected to the resistor ladder between adjacent resistors. An electrical node is positioned between a first and second resistor of the resistor ladder. The electrical node is electrically connected to a gate electrode of a field effect transistor (FET). A power supply produces a constant power voltage that is applied to a pre-selected bond pad to produce a desired bias voltage at the gate electrode of the FET. A selectable gate enable voltage source is connected to an and of the resistor ladder at the first resistor and is configured to produce a first and second voltage level that when combined with the constant power voltage produces a voltage level that causes the FET to be in a conducting state or non-conducting state, respectively.

Abstract: Embodiments of the invention relate to a circuit for an active diode, a method for operating an active diode, and, based thereon, an integrated active diode system, a rectifier, and a system for voltage conversion and/or regulation, comprising at least one transistor by which a current defined as positive from a first connection to a second connection of the transistor can be controlled, and at least one measuring/control circuit (for determining the current by means of which the at least one transistor can be switched on for currents under and at most up to a predetermined, non-positive threshold value (i1<=ith<=0), and can otherwise be switched off.

Abstract: An electronic device that includes a power on reset, a variable power supply filter coupled to the power on reset, and control logic coupled to the power on reset and the variable power supply filter. The control logic is configured to activate the variable power supply filter based on a core domain of the electronic device being active.

Abstract: A single-pole multi-throw switch includes a set of selection switches. The set of selection switches includes a set of primary switches, a first set and a second set of secondary switches. The primary set of switches includes a plurality of primary transistors coupled in series for transmitting radio frequency signals. The first set of secondary switches is coupled to the primary set of switches and includes a plurality of first secondary transistors coupled in series for transmitting the radio frequency signals when the primary transistors and the first secondary transistors are turned on. The second set of secondary switches is coupled to the primary set of switches and includes a plurality of second secondary transistors coupled in series for transmitting the radio frequency signals when the primary transistors and the second secondary transistors are turned on.

Abstract: A wireless switching circuit includes a charging capacitor, a voltage converter, an infrared sensor unit, a single chip microcomputer (SCM), a zero trigger circuit, and a thyristor. The charging capacitor is used to store and supply power. The voltage converter is used to convert alternating current (AC) voltage into direct current (DC) voltage to charge the charging capacitor. The infrared sensor unit is used to output control signals according to sensed infrared signals. The SCM outputs a trigger signal according to the control signals from the infrared sensor unit. Input ends of the zero trigger circuit are connected to the SCM to receive the trigger signal. An anode and a cathode of the thyristor is connected to a power supply line for the socket. A control end of the thyristor is connected to an output end of the zero trigger circuit.

Abstract: A DC voltage supply provides voltage. A time domain switched inertial capacitive sensor provides a thresholding variable capacitance based on the voltage. A second voltage supply provides a voltage, VDD. A logic inverter circuit has a logic inverter input and a logic inverter output, wherein the logic inverter circuit is supplied with VDD. A third voltage supply provides a second voltage, VCC. A time domain switched inertial capacitive sensor and the capacitor are arranged as a capacitive voltage divider between the DC voltage supply and the logic inverter circuit and so as to provide an input voltage Vin as an input signal to the logic inverter circuit. The logic inverter circuit outputs an output voltage, Vout, based on the input signal. The switch provides a bias voltage, Vbias, to the logic inverter circuit based on Vout such that the input signal is based on Vin and Vbias.

Abstract: Described is an apparatus (e.g., a router) which comprises: multiple ports; and a plurality of crossbar circuits arranged such that at least one crossbar circuit receives all interconnects associated with a data bit of the multiple ports and is operable to re-route signals on those interconnects.

Abstract: A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ?C, where E is the internal enable node and C is the clock.

Abstract: A semiconductor device may be provided. The semiconductor device may include a first switching control signal generation circuit configured to generate a first switching control signal which is enabled in synchronization with a time when a first delay period has passed from a time when a power-down mode is entered. The semiconductor device may include a second switching control signal generation circuit configured to generate a second switching control signal which is enabled during a period from a time when a read operation mode or a write operation mode is entered to a time when a second delay period has passed.

Abstract: A Physically Unclonable Function circuit may include precharge circuitry that precharges an output. The precharge circuitry may include transistors of a first type such as N-type or P-type. Circuitry having only transistors of a second, different type may be coupled to the output. The circuitry may produce a signal at the output based on variations between the transistors of the second type. The circuitry may include first and second circuits such as first and second transistors of the second type that are cross-coupled. While the circuitry is producing the signal at the output, the precharge circuitry or any transistors not of the second type may be disabled or electrically disconnected from the output. In this way, the stability over time of the Physically Unclonable Function circuit may be improved, because only variations associated with transistors of the second type may be used in producing the signal.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.

Abstract: Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. In other aspects, ESD circuitry is provided at corners of the IC layout and optionally within selected I/O slots. Decap circuitry is provided at an outer edge of the IC layout and is scalable in order to meet different requirements.

Abstract: Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.

Abstract: A method to form a 3D integrated circuit, the method including: fabricating two or more devices; connecting the devices together to form the 3D integrated circuit, where at least one of the devices has at least one unused designated dice line and at least one of the devices is a configurable device; and interconnecting at least two of the devices using Through Silicon Vias.

Abstract: Systems and methods for partially reconfiguring a programmable IC device are presented. Processing circuitry on the programmable IC device may identify a first region of the IC device to be reconfigured from a received bitstream. The processing circuitry may read a configuration bit associated with the identified first region, and determine, based on the configuration bit, whether to permit the received bitstream to reconfigure the identified first region. The received bitstream may be authenticated using an authentication key from a first set of authentication keys. The processing circuitry may determine whether to permit the received bitstream to reconfigure the identified first region based on the authentication key and the configuration bit.

Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies. The dies may include a memory cell die configured to store data in a random access fashion. The dies may also include a look-up table die comprising a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may be configured to perform a logic function. The reconfigurable look-up table may include a plurality of random access memory cells configured to store a look-up table to perform a logic function, and a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals. The look-up table stored in the plurality of memory cells may be configured to be dynamically altered via a memory write operation to the random access memory array.

Abstract: A driver circuit outputs a result of classifying and counting photons based on one or more energy levels to a column line. The driver circuit includes a multiplexer for receiving the result from a counter, a driving inverter for receiving a signal from the multiplexer and a power supply, and a switch connected between the power supply and an input terminal of the driving inverter.

Abstract: In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

Abstract: A voltage controlled oscillator arrangement is disclosed. The arrangement includes a voltage controlled oscillator and a bypass component. The voltage controlled oscillator has an output and a tuning port. The output provides an output signal at an operating frequency. The tuning port is configured to select the operating frequency according to an applied voltage. The voltage controlled oscillator has active portions and inactive portions. During the active portions, the output signal is at a non-zero value. The bypass component is configured to apply a bypass compensating signal to the tuning port during the active portions of the voltage controlled oscillator. The bypass compensating signal compensates for an oscillator temperature of the voltage controlled oscillator.

Abstract: A clock synchronization circuit has a clock sync detector. A first variable delay circuit is coupled to a first input of the clock sync detector. A controller is coupled to a digital output of the clock sync detector and a control input of the first variable delay circuit. A first clock signal is coupled to the first variable delay circuit. A second clock signal is coupled to a second input of the clock sync detector. The clock sync detector includes a first flip-flop and a first delay element coupled between the first variable delay circuit and a data input of the first flip-flop. A second variable delay circuit is coupled to a second input of the clock sync detector. A multiplexer is coupled between the first variable delay circuit and the first input of the clock sync detector. An offset compensation calibrates the clock sync detector.

Abstract: Integrated circuits with clock distribution circuitry are provided. The clock distribution circuitry may include a clock source, a clock distribution network, a frequency encoder placed at the output of the clock source, and one or more frequency decoders placed at the destinations of the clock distribution network. The frequency encoder can be used to obtain calibrated delay settings proportional to a reference clock generated by the clock source. Each frequency decoder can be placed in a closed loop configuration and can use the calibrated delay settings to locally self-generate a recovered clock at the destination during a locked state. During the locked state, clock buffers in the clock distribution network can be powered down to save power.

Abstract: A lock-on detection circuit for a phase-locked loop includes circuitry configured to receive first up and down outputs and second up and down outputs from one or more phase detectors and to determine from the first up and down outputs and the second up and down outputs how well the phase-locked loop is locked on to a reference clock.

Abstract: A circuit to generate a sweep frequency signal that includes a reference frequency source to generate a reference frequency signal, a first frequency combination circuit coupled to the reference frequency source, and operative to generate a sweep frequency signal in a first frequency band based on the reference frequency signal, a second frequency combination circuit coupled to the reference frequency source, and operative to generate a sweep frequency signal in a second frequency band different from the first frequency band based on the reference frequency signal, a multiple-level switch coupled to outputs of the first frequency combination circuit and the second frequency combination circuit, and a control circuit controlling the first and second frequency combination circuits and the multiple-level switch to output the sweep frequency signal in the first frequency band and the sweep frequency signal in the second frequency band at an output of the multiple-level switch alternately.

Abstract: An atomic resonance transition device includes a gas cell having an internal space that seals an alkali metal, a light emitter that emits excitation light containing a resonance light pair that causes the alkali metal to resonate toward the alkali metal, and a magnetic field generator that applies a magnetic field to the alkali metal. The excitation light diverges in a width direction in the internal space as the light travels from a side where the excitation light is incident toward a side where the excitation light exits, and the magnetic field from the magnetic field generator has a portion where the intensity of the magnetic field increases in the internal space with distance from the side where the excitation light is incident toward the side where the excitation light exits.

Abstract: Techniques, systems, and devices are disclosed for implementing a quasi-linear spin-torque nano-oscillator based on exertion of a spin-transfer torque on the local magnetic moments in the magnetic layer and precession of the magnetic moments in the magnetic layer within a spin valve. Examples of spin-torque nano-oscillators (STNOs) are disclosed to use spin polarized currents to excite nano magnets that undergo persistent oscillations at RF or microwave frequencies. The spin currents are applied in a non-uniform manner to both excite the nano magnets into oscillations and generate dynamic damping at large amplitude as a feedback to reduce the nonlinearity associated with mixing amplitude and phase fluctuations.

Abstract: In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is configured to output a differential voltage between a reference voltage and a voltage of an analog signal. The comparator is configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Abstract: A method, including receiving an input analog signal containing noise at a specific noise frequency and digitizing the input analog signal to form a digitized signal. The method also includes recovering a first amplitude and a first phase of the noise from the digitized signal, and generating an analog correction signal at the specific noise frequency. The analog correction signal has a second amplitude equal to the first amplitude and a second phase opposite to the first phase. The method further includes summing the input analog signal with the analog correction signal to generate an output analog signal.

Abstract: A digital to analog converter (DAC) maps a digital word to an analog output. The DAC bits may have amplitude and timing errors. These errors (or sometimes referred herein as “non-idealities”) result in distortion and degradation of the dynamic range in DACs. To reduce these negative effects, delta-sigma patterns can be provided to two bit cells, a reference bit cell and a bit cell under calibration, to perform, e.g., amplitude calibration and timing skew calibration. Delta-sigma patterns are particularly advantageous over square wave signals, which cannot be scaled to perform amplitude calibration between bit cells having different bit weights and are limited in frequency to integer fractions of the sampling clock.

Abstract: An analog-to-digital converter includes comparator modules and an encoder module. Each of the comparator modules is configured to compare a reference voltage with an input signal according to a first clock signal to generate a first comparison signal and a second comparison signal, and to generate a detection signal according to a second clock signal, the first comparison signal, and the second comparison signal. A delay duration is present between the first clock signal and the second clock signal. The encoder module is configured to generate a first bit of digital data according to the first comparison signals from the comparator modules, and to generate a second bit of the digital data according to the detection signals from the comparator modules and the first bit.

Abstract: An amplifier circuit has a sampling circuit to comprise a sampling capacitor which samples an input voltage and a plurality of switches, a quantizer to quantize an output voltage of the sampling circuit, a DA converter to output an analog signal depending on a quantization signal by the quantizer, and a feedback capacitor to feed the analog signal back to the output voltage of the sampling circuit.

Abstract: Successive approximation ADC includes a digital-to-analog converter, a comparator, a comparison unit, a timing unit and a control logic circuit. The digital-to-analog converter converts a digital signal to a reference analog signal. The comparator compares an analog input signal with a reference analog voltage and generates a comparing signal. The comparison unit generates a comparison result signal according to the comparing signal. The timing unit generates a clock signal, and sequentially enables N supplementary clock signals corresponding to N bits when the comparison result signal is enabled. The control logic circuit updates the digital signal according to the comparing signal, and generates N bits of digital value sequentially from the most significant bit to the least significant bit, and then determines whether the digital value is valid according to whether the Nth supplementary clock signal corresponding to the least significant bit is enabled.

Abstract: A voltage-controlled oscillator includes a voltage-current converter, a first ring oscillator and a second ring oscillator. The voltage-current converter includes a first transistor for receiving a first control voltage at its gate terminal, a second transistor for receiving a second control voltage at its gate terminal, a third transistor connected to the first transistor in series and has a gate terminal connected to a drain terminal of the first transistor, a fourth transistor connected to the second transistor in series and has a gate terminal connected to a drain terminal of the second transistor, a resistor connected to a source terminal of the first transistor and a source terminal of the second transistor, a fifth transistor having a gate terminal connected to the drain terminal of the first transistor, and a sixth transistor having a gate terminal connected to the drain terminal of the second transistor.

Abstract: A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.

Abstract: A digitized system operates to receive one or more analog signals from a sensor or other component and convert the analog signals to one or more digital signals. An analog-to-digital converter comprises a loop filter, a quantizer and one or more feedback digital-to-analog converters. A gain component provides coefficients along different points of a signal processing path to extend a bandwidth of the analog-to-digital converter. The gain component can modify a signal transfer function of the analog-to-digital converter while preserving a noise transfer function in order to process a signal in a higher frequency band in an extended mode of operation than other signals being processed in a normal operating mode.

Abstract: Circuits that are matched to balanced codes may recover transmitted information in a noise resilient and power efficient manner. Circuit components for processing a balanced code may include one or more of: matched amplification of the signals representing the balanced code, matched equalization and/or filtering on the signals representing the balanced code, matched non-linear filtering on the signaling representing the balanced code to detect the presence of particular symbols and matched latching of the signals representing the balanced code. Such matched circuits and circuit components may be achieved at least in part by incorporating suitable common circuit nodes and/or a single energy source into circuit topologies.

Abstract: A compression algorithm replaces duplicative strings with a copy pair indicating a location and length of a preceding identical string that is within a window from the duplicative string. Rather than a replacing a longest matching string within a window from a given point with a copy pair, the longest matching string may be used provide it is at least two bytes larger than the next longest matching string or is at a distance that is less than some multiple of a distance to the next longest matching string. In another aspect, the length of the window in which a matching string may be found is dependent on a length of the matching string. In yet another aspect, rather than labeling each literal and copy pair to indicate what it is, strings of non-duplicative literals are represented by a label and a length of the string.

Abstract: A method includes: setting a first and a second storage regions; first creating a first compression code of a compression target data in a file using a identifier indicating the data in the first storage region when a predetermined first consistency between the compression target data and the data in the first storage region is detected; comparing the compression target data with data in the second storage region when the predetermined first consistency between the compression target data and the data in the first storage region is not detected, the compression target data being moved to the second storage region after the comparing; and storing the compression target data into the first storage region associated with a identifier indicating the data in the first storage region when a predetermined second consistency between the compression target data and the data in the second storage region is detected.

Abstract: An arithmetic encoder is provided for converting an event sequence comprised of a plurality of events to an information sequence comprised of at least one information piece, and includes a core engine for receiving an event of the event sequence, and a probability estimate from a probability estimator, and generating zero or more pieces of the information sequence responsive to the received event and the probability estimate by bounding the ratio of events to information pieces. An arithmetic encoder is provided that is capable of constraining a number of events in at least one event sequence as a function of the number of generated information pieces in at least one information sequence.

Abstract: Apparatuses, systems, and computer program products that encode and/or decode information of a video stream, such as an MPEG-4 video stream, are disclosed. Some embodiments comprise an apparatus having a binarizer module to create a plurality of bins for a syntax element for information of the video stream, a context selection module to generate an index value and a most probable symbol (MPS) value for encoding the plurality of bins, and an arithmetic coding module to encode a first and a second bin of the plurality of bins based on a first probability value and a second probability value, respectively, wherein the first and second probability values are determined via the generated index value and MPS value. Examples of some embodiments are high definition personal video recorders, transcoders, computers, personal digital assistants, cellular telephones, portable video players, high definition digital versatile disc (HD-DVD) devices, and Blu-ray disc-read only memory (BD-ROM) devices.

Abstract: Methods, systems, and computer readable media for optimized message decoding are disclosed. According to one exemplary method, the method includes receiving a message containing one or more information elements (IEs). The method also includes determining a length associated with the message. The method further includes determining, using the length associated with message, whether the message can be accurately decoded using a mask stored in a memory. The method also includes in response to determining that the message can be accurately decoded using the mask, decoding the message using the mask.

Abstract: This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.

Abstract: A parity check circuit may include a first signal combination unit for generating first to Nth combination signals by combining first to Nth signals, wherein a Kth (K is a natural number of 2?K?N) combination signal of the first to Nth combination signals is obtained by combining the first to Kth signals of the first to Nth signals, a parity check unit for detecting whether an error is present in the first to Nth signals in response to the Nth combination signal, a second signal combination unit for generating first to Nth reconstruction signals by combining the first to Nth combination signals, wherein a Kth reconstruction signal of the first to Nth reconstruction signals is obtained by combining a (K?1)th combination signal and the Kth combination signal of the first to Nth combination signals, and a signal storage unit for storing the first to Nth reconstruction signals.

Abstract: The present disclosure illustrates a low density parity-check code decoder adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes k calculation units and n shift units, and the memory includes n memory units. The memory is coupled to the calculation module. Each shift unit is one-to-many coupled to the k calculation units. The n memory units are coupled to the n shift units. The calculation module operatively divides the coding data into n first-bit-strings. The ith calculation unit operatively generates a second-bit-string by calculating ith bits of the n first-bit-strings. The jth shift unit operatively generates a third-bit-string upon receiving jth bits of the k second-bit-strings, and shifts the third-bit-string. The memory units are configured for storing the n shifted third-bit-strings respectively.