Patents Issued in March 2, 2017
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Publication number: 20170060427Abstract: A method for scheduling read and write commands, performed by a processing unit, including at least the following steps: the processing unit obtains more than one read commands from a read queue successively and executes the obtained read commands until a first condition is met. After the first condition is met, the processing unit obtains more than one write commands from a write queue successively and executes the obtained write commands until a second condition is met.Type: ApplicationFiled: July 27, 2016Publication date: March 2, 2017Inventor: Yang-Chih Shen
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Publication number: 20170060428Abstract: Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (WA) value of a first, current window, comparing the WA value for the first window with a previous WA value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold.Type: ApplicationFiled: August 31, 2016Publication date: March 2, 2017Inventors: Frederick K.H. Lee, Xiangyu Tang, Lingqi Zeng
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Publication number: 20170060429Abstract: The present invention facilitates efficient and effective utilization of storage management features. In one embodiment, a system comprises: a storage component, a memory controller, and a communication link. The storage component stores information. The memory controller controls the storage component. The communication link communicatively couples the storage component and the memory controller. In one embodiment, the communication link communicates storage system management information between the memory storage component and memory controller, and communication of the storage system management information does not interfere with command/address information communication and data information communication.Type: ApplicationFiled: September 2, 2016Publication date: March 2, 2017Inventors: Alok Gupta, David Reed
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Publication number: 20170060430Abstract: A plurality of memory allocators are initialized within a computing system. At least a first memory allocator and a second memory allocator in the plurality of memory allocators are each customizable to efficiently handle a set of different memory request size distributions. The first memory allocator is configured to handle a first memory request size distribution. The second memory allocator is configured to handle a second memory request size distribution. The second memory request size distribution is different than the first memory request size distribution. At least the first memory allocator and the second memory allocator that have been configured are deployed within the computing system in support of at least one application. Deploying at least the first memory allocator and the second memory allocator within the computing system improves at least one of performance and memory utilization of the at least one application.Type: ApplicationFiled: November 4, 2016Publication date: March 2, 2017Inventor: Arun IYENGAR
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Publication number: 20170060431Abstract: Systems and methods for migrating stored backup data between magnetic disks (e.g., from an existing magnetic disk to another disk), such as a new or different magnetic disk in a magnetic storage library, without interrupting or otherwise affecting secondary copy operations (e.g., operations currently writing data to the storage library) utilizing the magnetic storage library, are described. In some embodiments, the systems and methods mark one or more mount paths as full when a running secondary copy operation associated with the mount path has completed a job (regardless of the actual current capacity or intended use of the mount path), and migrate each of the one or more data volumes to a second magnetic disk of the magnetic library when the mount path associated with the data volume is marked as full.Type: ApplicationFiled: September 2, 2015Publication date: March 2, 2017Inventors: Jaidev O. Kochunni, Michael F. Klose
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Publication number: 20170060432Abstract: System and method for managing storage metadata utilize a metadata data structure containing allocation information of storage blocks of a storage system in which a portion of the metadata data structure that corresponds to a group of the storage blocks can be reserved to a requesting client, which then manages the portion of the metadata data structure using a copy of the portion of the metadata data structure.Type: ApplicationFiled: August 28, 2015Publication date: March 2, 2017Applicant: VMWARE, INC.Inventors: Wenguang Wang, Yunshan Lu
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Publication number: 20170060433Abstract: Techniques for improving flash memory flushing are disclosed. In some embodiments, the techniques may be realized as a method for improving flash memory flushing including receiving a request to write to flash memory, writing data associated with the request to the flash memory, identifying a pointer to a region bitmap corresponding to a write region for the write request, marking a bit of the region bitmap corresponding to the request as dirty, and updating the pointer, using a pointer management component, to the region bitmap to contain a dirty block count.Type: ApplicationFiled: August 24, 2015Publication date: March 2, 2017Inventor: Daniel Peter NOÉ
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Publication number: 20170060434Abstract: A hybrid memory module includes a dynamic random access memory (DRAM) cache, a flash storage, and a memory controller. The DRAM cache includes one or more DRAM devices and a DRAM controller, and the flash storage includes one or more flash devices and a flash controller. The memory controller interfaces with the DRAM controller and the flash controller.Type: ApplicationFiled: November 20, 2015Publication date: March 2, 2017Inventors: Mu-Tien CHANG, Hongzhong ZHENG, Dimin NIU
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Publication number: 20170060435Abstract: In a case where a removable recording medium on which complete erasure has not been performed is accidentally removed from an information processing apparatus, information may be at risk of leaking out from the removed recording medium. In a case where physical removal of the recording medium from the information processing apparatus is detected, the information processing apparatus determines whether the removed recording medium is a recording medium on which complete erasure processing of data recorded thereon has been performed. Then, in a case where it is determined that the complete erasure processing of the data has not been performed, a user is notified of a prompt for the complete erasure processing.Type: ApplicationFiled: August 1, 2016Publication date: March 2, 2017Inventor: Mitsugu Yamauchi
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Publication number: 20170060436Abstract: Technologies for establishing and managing a high-performance memory region of a solid state drive include reserving a region of a volatile memory of the solid state drive for storage of host data. Memory accesses received from a host may be directed toward the reserved region of the volatile memory or toward a non-volatile memory of the solid state drive. Due to the structure of the volatile memory, memory accesses to the reserved region may exhibit lower access timing relative to memory accesses to the non-volatile memory. As such, the reserved region may be utilized as storage space for journaling and logging of data and/or other applications. Upon shutdown or a power failure event, data stored in the reserved region of the volatile memory is copied to the non-volatile memory and subsequently reinstated to the volatile memory upon the next initialization event.Type: ApplicationFiled: September 2, 2015Publication date: March 2, 2017Inventors: Sanjeev N. Trika, Knut S. Grimsrud, Piotr Wysocki
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Publication number: 20170060437Abstract: A method for reducing disk read rate by managing dataset mapping of virtual machine (VM) guest memory, comprising: monitoring a plurality of disk read write operations of a VM guest; updating a dataset mapping between disk blocks allocated to the VM guest and corresponding physical addresses of memory pages of the VM guest containing replica of data stored in the disk blocks, based on the plurality of disk read write operations; when identifying writing to one of the memory pages, removing a mapping of corresponding disk block and corresponding physical address of memory page; when reclaiming a mapped memory page of the VM guest by a host of the VM guest, discarding data contained in the memory page; and when the data is requested by the VM guest after it was reclaimed by said host, retrieving the data from corresponding disk block according to the mapping.Type: ApplicationFiled: February 16, 2015Publication date: March 2, 2017Inventors: Assaf SCHUSTER, Nadav AMIT, Dan TSAFRIR
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Publication number: 20170060438Abstract: The present invention makes it possible to form a circuit configuration that is capable of executing a keyword search at an increased speed while suppressing an increase in the memory capacity of a content-addressable memory. A semiconductor device according to an aspect of the present invention searches an input data string for a predesignated keyword, and includes a first content-addressable memory that stores a partial keyword corresponding to a predetermined number of data beginning with the first data of the keyword, a second content-addressable memory that stores the entirety of the keyword, and a control circuit that is coupled to the first content-addressable memory and to the second content-addressable memory. When a portion matching the partial keyword is detected in the input data string by a search in the first content-addressable memory, the second content-addressable memory executes a search on search data extracted from the input data string.Type: ApplicationFiled: August 4, 2016Publication date: March 2, 2017Inventors: Futoshi IGAUE, Kenji YOSHINAGA, Naoya WATANABE, Mihoko AKIYAMA
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Publication number: 20170060439Abstract: A memory system includes a first buffer memory, a second buffer memory having a higher memory performance rating than the first buffer memory, a nonvolatile semiconductor memory unit including an array of memory cell regions, and a control unit configured to cause data to be buffered in one of the first and second buffer memories before the data are written in the nonvolatile semiconductor memory unit, according to characteristics of the data.Type: ApplicationFiled: August 8, 2016Publication date: March 2, 2017Inventors: Akinori HARASAWA, Yoshihisa KOJIMA
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Publication number: 20170060440Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. For example, the computing device monitors storage unit (SU)-based write transfer rates and SU-based write failure rates associated with each of the SUs for a write request of encoded data slices (EDSs) to the SUs within the DSN. The computing device generates and maintains a SU write performance distribution based on monitoring of the SU-based write transfer rates and the SU-based write failure rates and adaptively adjusts a trimmed write threshold number of EDSs and/or a target width of EDSs for write requests of sets of EDSs to the SUs within the DSN.Type: ApplicationFiled: August 26, 2016Publication date: March 2, 2017Inventors: Greg R. Dhuse, Jason K. Resch, Ethan S. Wozniak
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Publication number: 20170060441Abstract: A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization.Type: ApplicationFiled: November 10, 2016Publication date: March 2, 2017Inventors: Hao Wang, Nam Sung Kim
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Publication number: 20170060442Abstract: To provide enhanced operation of data storage devices and systems, various systems, apparatuses, methods, and software are provided herein. In a first example, a data storage system is presented. The data storage system includes data storage devices comprising media for storage and retrieval of data. The data storage system includes a host interface configured to receive service level selections indicated by a host system for service level control of the one or more data storage devices. The data storage system includes a storage control system configured to operate the one or more data storage devices according to the service level selections.Type: ApplicationFiled: September 1, 2015Publication date: March 2, 2017Inventor: Paul Dunn
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Publication number: 20170060443Abstract: Provided are a storage device and a method for controlling thereof. Some embodiments include a method, comprising: receiving target performance information by a storage device; comparing the target performance information with maximum performance information by the storage device; and adjusting an incremental step pulse program (ISPP) operation performed on a memory cell of the storage device in response to the comparing of the target performance information with maximum performance information.Type: ApplicationFiled: July 22, 2016Publication date: March 2, 2017Inventor: Kangho ROH
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Publication number: 20170060444Abstract: Placing data within a storage device, including: receiving, by a storage device, information describing an expected longevity of data stored on the storage device; determining, by the storage device, a location for storing the data in dependence upon the expected longevity of the data; adjusting a garbage collection schedule in dependence upon data placement; and providing, to a storage array controller, garbage collection statistics.Type: ApplicationFiled: August 24, 2015Publication date: March 2, 2017Inventors: JOHN COLGROVE, ETHAN MILLER
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Publication number: 20170060445Abstract: The various implementations described herein include systems, methods and/or devices used to enable multi-phase erasure in a storage device. The method includes performing an erase operation on a portion of one or more non-volatile memory devices, by performing a sequence of erase phase operations until an erase operation stop condition is satisfied. Each erase phase operation includes: performing an erase phase on the portion of the non-volatile memory devices using an erase voltage, and determining an erase phase statistic for the erase phase. For each erase phase operation in the sequence of erase phase operations, other than a first erase phase operation, the erase voltage used when performing the erase phase operation is equal to the erase voltage used when performing a prior erase phase operation in the sequence of erase phase operations plus an erase voltage increment based on the erase phase statistic for the prior erase phase operation.Type: ApplicationFiled: October 30, 2015Publication date: March 2, 2017Inventors: Nian Niles Yang, Alexandra Bauche
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Publication number: 20170060446Abstract: A storage device includes a flash memory and a memory controller. The flash memory includes a plurality of memory blocks. The memory controller is configured to determine a fast cycle weight corresponding to a reuse period of a selected memory block among the plurality of memory blocks, and to manage wear leveling of the selected memory block using the fast cycle weight.Type: ApplicationFiled: July 5, 2016Publication date: March 2, 2017Inventors: SANGKWON MOON, CHUL LEE, HYUN JIN CHOI
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Publication number: 20170060447Abstract: Embodiments include a method of operating a storage device including a flash memory, comprising: calculating a reuse period of a selected memory block in the flash memory; determining a set of wordlines of the selected memory block for writing data based on the reuse period of the selected memory block; and writing the data into the set of wordlines.Type: ApplicationFiled: August 23, 2016Publication date: March 2, 2017Inventors: SANGKWON MOON, HEEWON LEE, SEONGJUN AHN
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Publication number: 20170060448Abstract: Systems and methods suitable for assisting data storage on a solid-state mass storage device by furthering interaction between a host and the solid-state mass storage device. The method includes providing data in a target block from a solid-state mass storage device to a host computer system, analyzing the data to identify valid and invalid data of the data in the target block with the host computer system, removing the invalid data, reformatting the valid data into a new data structure with the host computer system, writing the new data structure to the mass storage device, and marking the data in the target block as invalid.Type: ApplicationFiled: August 26, 2015Publication date: March 2, 2017Inventors: Michael Chaim Schnarch, Oded Ilan, Yaron Klein
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Publication number: 20170060449Abstract: A method for restoring a data volume using incremental snapshots of the data volume includes creating a first series of incremental snapshots according to a first predefined interval. The method further includes creating a second series of incremental snapshots according to a second predefined interval that is an integer multiple of the first predefined interval. The method also includes receiving a request to restore the data volume to a point-in-time. The method further includes restoring the data volume to the point-in-time using none or some of the snapshots in the first series that were created at or prior to the point-in-time, and all of the snapshots in the second series that were created at or prior to the point-in-time.Type: ApplicationFiled: August 28, 2015Publication date: March 2, 2017Inventors: Michael ZUCCA, Keith FARKAS, Joanne REN, Mayank RAWAT, Christos KARAMANOLIS
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Publication number: 20170060450Abstract: Systems, apparatuses, and methods for utilizing a programmable memory command sequencer to generate multiple commands from a single memory request. A sequencer receives requests from a host processor and utilizes any of a plurality of programmable routines in response to determining that a given request meets specific criteria. A given programmable routine generates a plurality of memory commands which are then conveyed to a local memory controller and/or one or more remote memory controllers. The host processor programs the sequencer at boot time and updates the sequencer at runtime in response to changing application behavior. In various embodiments, the sequencer generates a variety of error correction routines in response to different requests received from the host processor.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventor: David A. Roberts
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Publication number: 20170060451Abstract: A method for erasure detection in a storage cluster is provided. The method includes establishing a connection, via a network, of a storage unit to one of a plurality of storage nodes of a storage cluster and determining, for at least one page of a storage memory of the storage unit, that the at least one page is erased. The storage unit is one of a plurality of storage units configured to store user data in memory of the storage units in accordance with direction from the plurality of storage nodes. The method includes communicating from the storage unit to the one of the plurality of storage nodes that the at least one page is erased.Type: ApplicationFiled: September 1, 2015Publication date: March 2, 2017Inventors: John Martin Hayes, Hari Kannan, Nenad Miladinovic
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Publication number: 20170060452Abstract: A memory controller includes a current information storage unit storing information about various current amounts of a memory system, a current management unit controlling an output time of an operation execution signal by calculating the information about the various current amounts, and a command controller outputting a command to operate a memory device in response to the operation execution signal.Type: ApplicationFiled: January 12, 2016Publication date: March 2, 2017Inventors: Jae Hyeong JEONG, Kwang Hyun KIM, Jae Woo KIM
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Publication number: 20170060453Abstract: A memory system includes a semiconductor memory device including a plurality of memory blocks, including a first block storing data and a second block storing backup data, a plurality of pins, and a controller configured to output a control signal to the semiconductor memory in accordance with the command. When the controller receives from outside of the memory system, a read command for the data in the first block, and the data in the first block are available, the controller is configured to transmit the data in the first block to the outside of the memory system. When the controller receives from outside of the memory system, a read command for the data in the first block, and the data in the first block are not available, the controller is configured to transmit the backup data in the second block to the outside of the memory system.Type: ApplicationFiled: March 4, 2016Publication date: March 2, 2017Inventors: Shunsuke KODERA, Yoshio FURUYAMA
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Publication number: 20170060454Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes generating storage unit performance data based on a performance threshold value and storage unit performance values of storage units in a storage unit write set. Storage unit write set data indicating a new storage unit write set based on the storage unit performance data is generated, where at least one slow-performing storage unit is removed from the storage unit write set to create the new storage unit write set when the at least one slow-performing storage unit has a storage unit performance value that compares unfavorably to the performance threshold value. A plurality of write requests are generated for transmission to the new storage unit write set via a network, each including a data slices to be written to a corresponding storage unit of the new storage unit write set.Type: ApplicationFiled: July 29, 2016Publication date: March 2, 2017Inventor: Jason K. Resch
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Publication number: 20170060455Abstract: This specification describes methods, systems, and computer program products for maintaining data representing where each data block of multiple data blocks are stored among multiple computing nodes. Each computing node generates a respective locality summary based on locally stored data blocks, and submits the locality summary to a controlling computing node.Type: ApplicationFiled: August 26, 2016Publication date: March 2, 2017Inventors: Harshad Deshmukh, Adalbert Gerald Soosai Raj, Jignesh M. Patel
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Publication number: 20170060456Abstract: A data storage area of a data storage device can be used to communicate information between the data storage device and an external device or software. In some examples, configuration data stored within the data storage area can be used to determine a subset of data to copy or move from a first data storage medium to a second data storage medium. The data storage area can be a unique partition and the data storage device can locate partition information to determine a location of the partition. The data storage device can then use the partition to store data for two-way communication between the data storage device and an external system, device, or software.Type: ApplicationFiled: September 5, 2016Publication date: March 2, 2017Applicant: Seagate Technology LLCInventors: John Edward Moon, Robert Dale Murphy, Michael Habinsky, David A. Hitch, Thomas Dale Hosman
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Publication number: 20170060457Abstract: A method includes dispersed storage error encoding a data object into a plurality of sets of encoded data slices. The method further includes determining a local slice storage number, a local area network (LAN) slice storage number, and a wide area network (WAN) slice storage number, wherein a sum of the local slice number, the LAN slice storage number, and the WAN slice storage number equals the pillar width number. For at least some sets of encoded data slices, the method further includes sending the local slice storage number of encoded data slices to the local slice storage number of local memory devices; sending the LAN slice storage number of encoded data slices to the LAN slice storage number of LAN storage units of the DSN; and sending the WAN slice storage number of encoded data slices to the WAN slice storage number of WAN storage units of the DSN.Type: ApplicationFiled: November 14, 2016Publication date: March 2, 2017Inventors: Jason K. Resch, Gary W. Grube, Timothy W. Markison
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Publication number: 20170060458Abstract: A system and method are provided for pooling storage devices in a virtual library for performing a storage operation. A storage management device determines a storage characteristic of a plurality of storage devices with respect to performing a storage operation. Based on a storage characteristic relating to performing the storage operation, the storage management device associates at least two storage devices in a virtual library. The storage management device may continuously monitor the virtual library and detect a change in storage characteristics of the storage devices. When changes in storage characteristics are detected, the storage management device may change associations of the storage device in the virtual library.Type: ApplicationFiled: November 16, 2016Publication date: March 2, 2017Inventors: Rajiv KOTTOMTHARAYIL, Ho-Chi CHEN
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Publication number: 20170060459Abstract: A method for execution by a dispersed storage and task (DST) execution unit that includes a processor includes receiving an access request that includes an authorization token from a computing device via a network. Authorization data is generated based on the access request. The access request is executed and a result of the access request is transmitted to the computing device via the network when the authorization data includes a verification indicator. An invalid token notification is generated for transmission to the computing device when the authorization data includes an invalid token indicator.Type: ApplicationFiled: July 25, 2016Publication date: March 2, 2017Inventors: Joseph M. Kaczmarek, Ravi V. Khadiwala, Jason K. Resch
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Publication number: 20170060460Abstract: An object of the present invention is to provide a technique that makes it difficult to fabricate an illegal duplicate of a semiconductor storage apparatus. In a memory controller, an address acquisition unit acquires a latency-related designated address. The latency-related designated address is an address in the semiconductor memory storing data to be transmitted with the minimum latency upon reception of a read command, and is identical with an address held by a host. A pre-acquisition unit reads the data for the latency-related designated address from the semiconductor memory and stores it in the buffer. A comparator compares the address included in the read command to the latency-related designated address. Depending on the result of the comparison by the comparator, a transmission control unit transmits the data stored in the buffer to the host at the time point of completion of a minimum latency.Type: ApplicationFiled: August 22, 2016Publication date: March 2, 2017Applicant: MegaChips CorporationInventors: Takahiko Sugahara, Hiromu Yutani, Hajime Yoshimura
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Publication number: 20170060461Abstract: A memory system and method for reducing peak current consumption. In one embodiment, a method is provided that is performed in a memory system comprising a memory with a plurality of blocks, wherein each block has a peak current consumption. In this method, a plurality of metablocks is created, wherein each metablock is created by grouping together blocks with complementary peak current consumption. Next, the metablocks are programmed. Because each of the metablocks has blocks with complementary peak current consumption, each of the metablocks has similar peak current consumption when programmed. Other embodiments are provided.Type: ApplicationFiled: August 24, 2015Publication date: March 2, 2017Applicant: SanDisk Technologies Inc.Inventors: Eran Erez, Jonathan H. Hsu, Ken Q. Nguyen
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Publication number: 20170060462Abstract: A power supply voltage control circuit device includes a power supply control circuit, a memory, and an arithmetic processing circuit. The power supply control circuit is configured to control a power supply voltage to be applied to a target circuit, and the memory is configured to store a first processing result when the target circuit is operated by setting the power supply voltage to a first voltage and a second processing result when the target circuit is operated by setting the power supply voltage to a second voltage different from the first voltage. The arithmetic processing circuit is configured to perform verify by reading the first processing result and the second processing result from the memory and output a result of the verify to the power supply control circuit, and wherein the power supply control circuit controls the power supply voltage based on the result of the verify.Type: ApplicationFiled: April 22, 2016Publication date: March 2, 2017Inventors: Hiroshi FUKUDA, Hiroshi NARITOMI
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Publication number: 20170060463Abstract: Methods of programming firmware in a data storage device include pre-programming memory cells included in at least one nonvolatile memory of a plurality of nonvolatile memories using a first verification voltage higher than a first reference voltage before a surface mounting technology is applied to the nonvolatile memories.Type: ApplicationFiled: July 8, 2016Publication date: March 2, 2017Inventors: In Bo Shim, Jae-Sang Yun, Doo-Jin Yi, Young Joon Jang
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Publication number: 20170060464Abstract: Techniques are disclosed for memory management in a streams processing environment. Certain aspects of the present disclosure provide a method generally including monitoring, via a streams manager for a distributed application, an amount of memory used by a group of executing processes, and for each group, comparing the amount of memory used by the group against a memory threshold, and determining whether the memory used by the group exceeds a first threshold, and reducing memory usage by the group when the memory used by the group exceeds the first threshold.Type: ApplicationFiled: August 24, 2015Publication date: March 2, 2017Inventors: Michael J. BRANSON, Jay S. BRYANT, James E. CAREY, John M. SANTOSUOSSO
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Publication number: 20170060465Abstract: Techniques are disclosed for memory management in a streams processing environment. Certain aspects of the present disclosure provide a method generally including monitoring, via a streams manager for a distributed application, an amount of memory used by a group of executing processes, and for each group, comparing the amount of memory used by the group against a memory threshold, and determining whether the memory used by the group exceeds a first threshold, and reducing memory usage by the group when the memory used by the group exceeds the first threshold.Type: ApplicationFiled: August 25, 2015Publication date: March 2, 2017Inventors: Michael J. BRANSON, Jay S. BRYANT, James E. CAREY, John M. SANTOSUOSSO
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Publication number: 20170060466Abstract: A method includes issuing, by a managing unit of a dispersed storage network (DSN), a vault access restriction to a set of storage units of the DSN regarding a logical storage vault supported by the set of storage units. While the vault access restriction is active, the method continues by receiving, by a storage unit of the set of storage units, a data access request to the vault. The method continues by determining, by the storage unit, whether the data access request is regarding a rebuilding operation. When the data access request is regarding a rebuilding operation, the method continues by processing, by the storage unit, the data access request. When data access request is not regarding a rebuilding operation, the method continues by denying, by the storage unit, the data access request.Type: ApplicationFiled: November 14, 2016Publication date: March 2, 2017Inventors: Wesley B. Leggette, Jason K. Resch, Sebastien Vas
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Publication number: 20170060467Abstract: A signal interface has a compression unit and a data memory. The compression unit is configured to input an input datum from signal data generated by at least one sensor and further configured to identify the presence or absence of at least one repetition condition in the input datum. If the presence of the at least one repetition condition of the input datum is identified, the compression unit encodes the input datum in a compressed way to generate a compressed datum and saves the compressed datum in the data memory. If the presence of the at least one repetition condition of the input datum is not identified, the compression unit saves the uncompressed input datum in the data memory.Type: ApplicationFiled: June 28, 2016Publication date: March 2, 2017Inventors: Marco Leo, Paolo Rosingana, Marco Castellano, Alessandro Giuliano Locardi
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Publication number: 20170060468Abstract: A method, system, and computer program product for managing data sets of a storage facility is disclosed. The method, system, and computer program product include determining, by analyzing a first data set, that the first data set includes a first record having padded data. To identify the padded data, the method, system, and computer program product include comparing at least a portion of the first record of the first data set with a second record of a second data set. Next, the method, system, and computer program product include removing, from the first record of the first data set, the padded data.Type: ApplicationFiled: November 15, 2016Publication date: March 2, 2017Inventors: Philip R. Chauvet, Franklin E. McCune, David C. Reed, Max D. Smith
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Publication number: 20170060469Abstract: Systems and methods which implement one or more data organization techniques that facilitate efficient access to source data stored by a storage system are disclosed. Data organization techniques implemented according to embodiments are adapted to optimize (e.g., maximize) input/output efficiency and/or (e.g., minimize) storage overhead, while maintaining mean time to data loss, repair efficiency, and/or traffic efficiency. Data organization techniques as may be implemented by embodiments include blob based organization techniques, grouped symbols organization techniques, data ordering organization techniques, and combinations thereof.Type: ApplicationFiled: November 30, 2015Publication date: March 2, 2017Inventors: Michael George Luby, Thomas Joseph Richardson
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Publication number: 20170060470Abstract: A memory system may include: a memory device including: a plurality of pages each including a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host; a plurality of memory blocks each including the pages; a plurality of planes each including the memory blocks; and a plurality of memory chips each including the planes; and a controller suitable for checking the write data corresponding to a command received from the host, programming the write data to pages of memory blocks included in planes of a first memory chip, and programming first data for the write data to pages of memory blocks included in planes of a second memory chip.Type: ApplicationFiled: January 28, 2016Publication date: March 2, 2017Inventor: Hoe-Seung JUNG
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Publication number: 20170060471Abstract: A work apparatus in one aspect of the present disclosure comprises a control unit, a volatile memory and a rewritable non-volatile memory. The control unit comprises an update processing unit and a writing processing unit. The writing processing unit writes history information in the volatile memory into the non-volatile memory when the writing processing unit predicts a suspension of supply of an electric power to the control unit.Type: ApplicationFiled: August 23, 2016Publication date: March 2, 2017Applicant: MAKITA CORPORATIONInventors: Hirokatsu YAMAMOTO, Yoshitaka ICHIKAWA
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Publication number: 20170060472Abstract: A system, method, and apparatus are provided for performing a transparent hybrid data storage scheme in which data are stored as blocks distributed among one or more flash-based storage devices (e.g., solid state drives) and one or more magnetic storage devices (e.g., magnetic disk drives). Files larger than a given size (e.g., 1 MB) are segmented into blocks of that size and stored on one or more devices; blocks of one file may be stored on devices of different types. Periodically, a utility function calculates utility values for each of some or all stored blocks based on frequency of access to the block, frequency of access of a particular type (e.g., random, sequential), a preference regarding where to store the block or the corresponding file, and/or other factors. Blocks having the highest utility values are subject to migration between devices of different types and/or the same type (e.g., for load-balancing).Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Applicant: LinkedIn CorporationInventors: Zhenyun Zhuang, Sergiy Zhuk, Haricharan K. Ramachandra, Cuong H. Tran, Badrinath K. Sridharan
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Publication number: 20170060473Abstract: Provided are systems and methods for garbage collection of objects in storage. An example method may include providing a monotonically increasing logical clock. Each object is associated with a first number and a second number. The second number is a minimum of the first numbers of objects in a subtree to which the object refers. When the logical clock increases, objects with the first number less than the logical clock from the storage are deleted. When a new object is added to the storage, the first number of the new object is set to a new first number. The new first number is equal to or greater than the logical clock. The first number of each object in a subtree to which the new object is referring is updated. The updated first number is a function of a previous first number and a previous logical clock.Type: ApplicationFiled: August 18, 2016Publication date: March 2, 2017Inventor: Jeremy Fitzhardinge
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Publication number: 20170060474Abstract: A data erasing method of the present disclosure is a data erasing method for erasing data stripe-recorded in a plurality of write-once optical discs constituting a redundant arrays of inexpensive disks (RAID) system and each including a plurality of data recording blocks and a redundant data block. In the data erasing method, alternate recording of at least one target block and the redundant data block is performed in a predetermined alternate area. The target block is one of the data recording blocks in which target data as erase target data is recorded. The target block is overwritten such that the target data is not correctly read.Type: ApplicationFiled: August 26, 2016Publication date: March 2, 2017Inventors: Takeharu YAMAMOTO, Yoshihisa TAKAHASHI, Toshiaki TAKASU
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Publication number: 20170060475Abstract: A semiconductor system may include a plurality of memory devices corresponding to a plurality of channels, an address mapping unit suitable for converting addresses corresponding to provided external requests according to a selected address map among a plurality of address maps; a monitoring unit suitable for monitoring the external requests provided to each of the plurality of channels, and a control unit suitable for providing a control signal for controlling the address mapping unit to select an address map according to a result of the monitoring.Type: ApplicationFiled: December 29, 2015Publication date: March 2, 2017Inventors: Kyung-Min LEE, Young-Suk MOON
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Publication number: 20170060476Abstract: A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Srinivas B. Purushotham