Patents Issued in March 2, 2017
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Publication number: 20170060577Abstract: In one implementation, a record associated with an element of an application is maintained and a notification is generated when the record indicates a lack of documentation.Type: ApplicationFiled: June 25, 2014Publication date: March 2, 2017Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Daniel Schreiber, Shimon Cherny, Effi Bar-Shean
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Publication number: 20170060578Abstract: The present disclosure discloses system and method for evaluating a human resource in a software development environment. At first, historical performance data and profile data associated with a plurality of human resources involved in a software project is received. From such data (historical performance data and profile data), a plurality of attributes is extracted. Further, Bayesian classification technique is implemented on the plurality of attributes in order to classify the plurality of attributes, of each human resource, into a plurality of classes. The plurality of attributes are classified in such a manner that at least one attribute corresponding to at least one human resource and at least one other human resource is classified into a class and another class respectively. Further, based on the classification of each attribute associated with the human resource, a grade is assigned to the human resource.Type: ApplicationFiled: August 19, 2016Publication date: March 2, 2017Inventors: Ashutosh SHUKLA, Satya Sai Prakash KANAKADANDI, S U M Prasad DHANYAMRAJU
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Publication number: 20170060579Abstract: Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.Type: ApplicationFiled: March 11, 2016Publication date: March 2, 2017Inventors: John Edward VINCENT, Peter Man Kin SINN, Benton WATSON
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Publication number: 20170060580Abstract: In various implementations, an abstraction is generated from an asset associated with an asset-modifying workflow. The abstraction can be embedded into an activity stream generated from an asset-modification application and communicated to a remote server device for collection and analysis. The remote server device, upon receiving at least the abstraction, can determine a contextual identifier for association with the abstraction and the asset associated with the asset-modifying workflow. The remote server device can conduct usage analysis on data received from the activity stream in association with the contextual identifier, and further send a signal to the asset-modification application to customize the workflow based on the contextual identifier determined to be associated with the abstraction and asset.Type: ApplicationFiled: August 25, 2015Publication date: March 2, 2017Inventor: JONATHAN BRANDT
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Publication number: 20170060581Abstract: An arbiter that performs accelerated arbitration by approximating relative ages including a memory, blur logic, and grant logic. Multiple entries arbitrate for one or more resources. The memory stores age values each providing a relative age between each pair of entries, and further stores blurred age values. The entries are divided into subsets in which each entry belongs to only one subset. The blur logic determines each blurred age value to indicate a relative age between an entry of a first subset and an entry of a different subset for each pair of subsets. The grant logic grants access by an entry to a resource based on relative age using corresponding age values when comparing relative age between entries within a common subset, and using corresponding blurred age values when comparing relative age between entries in different subsets. Each blurred age value represents multiple age values to simplify arbitration.Type: ApplicationFiled: August 19, 2016Publication date: March 2, 2017Inventor: NIKHIL A. PATIL
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Publication number: 20170060582Abstract: Arbitrary instruction execution from context memory. In some embodiments, an integrated circuit includes a processor core; a context management circuit coupled to the processor core; and a debug support circuit coupled to the context management circuit, where: the context management circuit is configured to halt a thread running on the processor core and save a halted thread context for that thread into a context memory distinct from the processor core, where the halted thread context comprises a fetched instruction as the next instruction in the execution pipeline; the debug support circuit is configured instruct the context management circuit to modify the halted thread context in the context memory by replacing the fetched instruction with an arbitrary instruction; and the context management circuit is further configured to cause the thread to resume using the modified thread context to execute the arbitrary instruction.Type: ApplicationFiled: September 1, 2015Publication date: March 2, 2017Inventors: Celso Fernando Veras Brites, Alex Rocha Prado
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Publication number: 20170060583Abstract: The method can be performed in a processor integrated circuit having an instruction decoder and a plurality of shared resources, a resource tracker having a plurality of credit units associated to corresponding ones of the shared resources in a manner to be updatable based on availability of the shared resources, a resource matcher connected to receive a resource requirement signal from the decoder and connected to receive a resource availability signal from the resource tracker. The method can include: performing a determination of whether or not the resource requirement signal matches the resource availability signal, and, upon a positive determination, dispatching a corresponding instruction data, updating the status of a corresponding one or more of the credit units, and preventing the resource matcher from performing a subsequent determination for given period of time after the positive determination.Type: ApplicationFiled: January 25, 2016Publication date: March 2, 2017Inventors: LOUIS-PHILIPPE HAMELIN, PETER MAN-KIN SINN, CHANG LEE, PAUL ALEPIN, GUY-ARMAND KAMENDJE TCHOKOBOU, OLIVIER DARCY, JOHN EDWARD VINCENT
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Publication number: 20170060584Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.Type: ApplicationFiled: September 6, 2016Publication date: March 2, 2017Inventors: GILBERT M. WOLRICH, KIRK S. YAP, JAMES D. GUILFORD, ERDINC OZTURK, VINODH GOPAL, WAJDI K. FEGHALI, SEAN M. GULLEY, MARTIN G. DIXON
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Publication number: 20170060585Abstract: Instructions and logic provide SIMD vector population count functionality. Some embodiments store in each data field of a portion of n data fields of a vector register or memory vector, at least two bits of data. In a processor, a SIMD instruction for a vector population count is executed, such that for that portion of the n data fields in the vector register or memory vector, the occurrences of binary values equal to each of a first one or more predetermined binary values, are counted and the counted occurrences are stored, in a portion of a destination register corresponding to the portion of the n data fields in the vector register or memory vector, as a first one or more counts corresponding to the first one or more predetermined binary values.Type: ApplicationFiled: November 14, 2016Publication date: March 2, 2017Applicant: INTEL CORPORATIONInventors: Terence Sych, Elmoustapha Ould-Ahmed-Vall
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Publication number: 20170060586Abstract: Described examples include integrated circuits such as microcontrollers with a low energy accelerator processor circuit or other application specific integrated processor circuit including a load store circuit operative to perform load and store operations associated with at least one register and a low gate count shift circuit to selectively shift the data of the register by only an integer number bits less than the register data width without using a barrel shifter for low power operation to support vector operations for FFT or filtering functions.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Applicant: Texas Instruments IncorporatedInventors: Srinivas Lingam, Seok-Jun Lee
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Publication number: 20170060587Abstract: Methods and apparatuses for determining set-membership using Single Instruction Multiple Data (“SIMD”) architecture are presented herein. Specifically, methods and apparatuses are discussed for compressing or packing, in parallel, multiple fixed-length values into a stream of multiple variable-length values using SIMD architecture.Type: ApplicationFiled: July 15, 2016Publication date: March 2, 2017Inventors: SHASANK K. CHAVAN, PHUMPONG WATANAPRAKORNKUL, VICTOR CHEN
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Publication number: 20170060588Abstract: A computing system includes a host processor configured to process operations and a memory configured to include an internal processor and store host instructions to be processed by the host processor. The host processor offloads processing of a predetermined operation to the internal processor. The internal processor possibly provides specialized hardware designed to process the operation efficiently, improving the efficiency and performance of the computing system.Type: ApplicationFiled: March 11, 2016Publication date: March 2, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Yoonseo CHOI
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Publication number: 20170060589Abstract: A method and systems generate a control flow graph including an edge of the control flow graph from a branch instruction to a target address of the branch instruction in an abstract interpretation for an assignment instruction to a branch target variable of a program. The program allocates a particular branch target variable to a branch instruction having a plurality of branch targets. The branch target address is loaded from the branch target variable upon branching, a branch address of a branch instruction having one branch target as well as the address assigned by the assignment instruction to the branch target variable being determined as certain constant values determined by compiling the program. The target address assigned by the assignment instruction is added to an object of the abstract interpretation. A current abstract interpretation is terminated if the abstract interpretation reaches an instruction already subjected to the abstract interpretation.Type: ApplicationFiled: August 24, 2015Publication date: March 2, 2017Inventors: REID T. COPELAND, TOSHIHIKO KOJU
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Publication number: 20170060590Abstract: Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.Type: ApplicationFiled: November 2, 2016Publication date: March 2, 2017Inventors: Prathiba Kumar, Satish K. Sadasivam
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Publication number: 20170060591Abstract: A system and method for multi-branch switching are provided. A memory has stored therein a program comprising at least one sequence of instructions, the at least one sequence of instructions comprising a plurality of branch instructions, at least one branch of the program reached upon execution of each one of the plurality of branch instructions. The processor is configured for fetching the plurality of branch instructions from the memory, separately buffering each branch of the program associated with each one of the fetched branch instructions, evaluating the fetched branch instructions in parallel, and executing the evaluated branch instructions in parallel.Type: ApplicationFiled: November 23, 2015Publication date: March 2, 2017Inventors: Peter Man-Kin SINN, Chang LEE, Louis-Philippe HAMELIN
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Publication number: 20170060592Abstract: The processor chip can have a pre-execution pipeline sharing a plurality of resources including at least one resource of interest, a resource tracker having more than one credit unit associated to each one of said at least one resource of interest. The method can include: decoding the instruction data to determine a resource requirement including a quantity of virtual credits required from the credit units for the at least one resource of interest, checking the resource tracker for an availability of said quantity of virtual credits and, if the availability of the amount of said virtual credits is established, i) dispatching the instruction data, and ii) subtracting the quantity of said credits from the resource tracker.Type: ApplicationFiled: November 25, 2015Publication date: March 2, 2017Inventors: Chang Lee, Louis-Philippe Hamelin, Peter Man-Kin Sinn
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Publication number: 20170060593Abstract: Systems and methods relate to a hierarchical register file system including a level 1 physical register file (L1 PRF) and a backing physical register file (PRF). A subset of productions of instructions executed in an instruction pipeline of a processor which have a high likelihood of use for one or more future instructions are identified. The subset of productions are stored in the L1 PRF, while all productions are stored in the backing PRF.Type: ApplicationFiled: September 2, 2015Publication date: March 2, 2017Inventors: Anil KRISHNA, Rodney Wayne SMITH, Sandeep Suresh NAVADA, Shivam PRIYADARSHI, Niket Kumar CHOUDHARY, Raguram DAMODARAN
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Publication number: 20170060594Abstract: A method for combining instructions, performed by a compiler, containing at least the following steps. First instructions are obtained, where each performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated mathematics operation. The first instructions are combined as one combined instruction according to data dependencies between the first instructions. The combined instruction is sent to a SP (Stream Processor).Type: ApplicationFiled: September 16, 2015Publication date: March 2, 2017Inventors: Huaisheng ZHANG, Zhou HONG, Heng QI
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Publication number: 20170060595Abstract: Disclosed is an apparatus and method to securely activate or revoke a key. For example, the apparatus may comprise: a storage device to store a plurality of pre-stored keys; a communication interface to receive an activate key command and a certificate associated with one of the pre-stored keys; and a processor. The processor may be coupled to the storage device and the communication interface and may be configured to: implement the activate key command to reboot the apparatus with the pre-stored key and the certificate; and determine if the reboot is successful.Type: ApplicationFiled: August 26, 2015Publication date: March 2, 2017Inventors: Ron Keidar, Yau Chu, Xu Guo
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Publication number: 20170060596Abstract: A controller initializing device and method is configured to initialize controllers. When a device is powered on, a basic input and output system of the device initializes a first chip of the device. The basic input and output system starts a power on self test and initializes a first controller of the device. The basic input and output system outputs a trigger signal when the power on self test of the basic input and output system ends. A baseboard management controller of the device accesses the first controller when the baseboard management receives the trigger signal.Type: ApplicationFiled: September 21, 2015Publication date: March 2, 2017Inventor: FANG-CING SU
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Publication number: 20170060597Abstract: A method of booting a production computer system includes establishing a connection between a key computer system and the production computer system, gathering information about system data of the production computer system, transmitting the information about the system data of the production computer system to the key computer system, comparing the gathered information with comparison information stored in the key computer system, automated transmitting of a passphrase from the key computer system to the production computer system to decrypt encrypted file system date on a medium within the production computer system if the comparison is successful, decrypting the encrypted file system data on the medium by the passphrase, and loading the decrypted file system data and booting the production computer system.Type: ApplicationFiled: January 27, 2015Publication date: March 2, 2017Inventor: Heinz-Josef Claes
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Publication number: 20170060598Abstract: A managed boot process system includes a management device coupled to a networking device through a network. The networking device includes a storage system with an assured boot image, a plurality of runtime images, and a plurality of session data, and a memory system having boot instructions. A processing system in the networking device stores the plurality of session details in the storage system during a management session with the management device and prior to a reboot. The processing system then performs a reboot and executes the boot instructions to load the assured boot image. The networking device then uses the session details to restart the management session without reauthorization subsequent to loading the assured boot image and prior to loading a runtime image. The networking device then provides a graphical user interface over the network to the management device and uses it to receive a management instruction for execution.Type: ApplicationFiled: September 2, 2015Publication date: March 2, 2017Inventors: Kevin Allen Hughes, Jason Garth Pearce
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Publication number: 20170060599Abstract: A method and an apparatus for awakening an electronic device are provided. The method includes: receiving a user instruction for awakening an electronic device from its hibernation state and determining an intermediate device. The intermediate device is a device running in a normal operation mode and accessing a same target local area network as the electronic device. The method further includes: sending an awakening instruction to the intermediate device, such that the intermediate device broadcasts in the target local area network an awakening message for awakening the electronic device.Type: ApplicationFiled: April 25, 2016Publication date: March 2, 2017Inventors: Hong Chen, Yi Ding, Feiyun Li
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Publication number: 20170060600Abstract: A visitor guidance computing device for navigating a user between digital assets is provided. The visitor guidance computing device includes a processor and a memory. The processor is programmed to receive a request message to view a digital asset, wherein the request includes device data from a requesting user computing device, and to filter digital asset analytics using the device data to determine topics and sub-topics responsive to the device data. The processor is further programmed to store a hierarchical shell in the memory, the hierarchical shell having multiple layers of nodes, each node configured to store data relating to the topics and sub-topics, and to populate the layers with content for display as a guidance tool. The processor is also programmed to provide a widget that causes the guidance tool to be displayed, and to cause the widget and hierarchical shell to be provided with the requested digital asset.Type: ApplicationFiled: August 26, 2015Publication date: March 2, 2017Inventors: Bryan Niehaus, Corey Hively, Jennifer Rosa, Suman Rausaria, Tricia Nance, Karen Randell, Matthew Thomas Holton, Christopher Mullen
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Publication number: 20170060601Abstract: The present invention relates to a simplified system and method thereof for creating video guided application workflows where a plurality of users can interact directly with a plurality of application input controls that are displayed on at least one screen area of at least one screen, wherein the plurality of application input controls are displayed on the same screen as the video and in sequence with the timeline so that the video content can direct the user actions.Type: ApplicationFiled: August 24, 2016Publication date: March 2, 2017Inventors: Vikas JOSHI, Roger WOEHL
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Publication number: 20170060602Abstract: Apparatuses, methods, and computer program products are provided for automatically internationalizing grammatical output for presentation to a user of a program based on the user's locale. In particular, AST transformations are described that cause a compiler to generate a programming method during compilation of a portion of source code containing a predefined token, where the programming method is incorporated (by the compiler) into a file produced by the compiler and serves to call an instance of a message bundle file that provides translation of grammatical output without requiring the programmer/developer to manually incorporate individual message bundles into each portion of source code to be internationalized.Type: ApplicationFiled: August 26, 2015Publication date: March 2, 2017Inventors: Bryan Self, Preston Prewett, Josh Turner
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Publication number: 20170060603Abstract: A computer supports an operation by an operator of a target device. The computer stores a first topology indicating dependency relationship of a plurality of device types including a device type of the target device. The computer generates a second topology indicating dependency relationship of a plurality of devices including the target device, by performing, based on the first topology, a topology discovery for the plurality of devices. Each of the plurality of devices has any one of the plurality of device types. The computer provides an operation sequence of the plurality of devices to the operator. The operation sequence is generated based on the second topology.Type: ApplicationFiled: August 27, 2015Publication date: March 2, 2017Inventors: Taku Aratsu, Toshiyuki Komoda, Yohei Umehara, Satoshi Yokoyama
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Publication number: 20170060604Abstract: Embodiments of the present invention provide efficient systems and methods for scaling past the Java Virtual Machine (JVM) thread limit in a Java Virtual Machine. Embodiments of the present invention can be used to ensure that a received workload is executed, even if the workload is greater than a JVM thread limit of the system, by spawning a reduced number of threads from a main process, in order to provide enough resources for the effective execution of a received workload.Type: ApplicationFiled: August 24, 2015Publication date: March 2, 2017Inventor: Russell I. Wilson
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Publication number: 20170060605Abstract: Embodiments provide for application-specific provisioning of files or registry keys. As applications are installed or launched, data is recorded by an application virtualization engine, and an index is created linking the recorded data to both the application and the underlying files or registry keys. As applications are requested (e.g., launched, updated, or the like), the application virtualization engine reveals various copies of file or registry keys to the application on demand or in accordance with a policy.Type: ApplicationFiled: June 9, 2016Publication date: March 2, 2017Inventors: Fei Huang, Daniel James Beveridge
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Publication number: 20170060606Abstract: A coherent computer system includes a memory shared by a processor and a coherent accelerator device (CAD). The memory includes a work queue directly accessible by the accelerator functional unit (AFU) within the CAD and by the processor utilizing the same effective addresses. The coherent computer system provides accelerator functionality when the accelerator is unavailable by implementing a virtual AFU to carryout accelerator function while the AFU is unavailable. The virtual AFU is a functional logical equivalent of the AFU and is coherent with the processor. When the AFU becomes available, the virtual AFU is disabled and the accelerator is enabled to allow the accelerator to carryout accelerator functionality.Type: ApplicationFiled: September 29, 2015Publication date: March 2, 2017Inventor: Michael C. Hollinger
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Publication number: 20170060607Abstract: A coherent computer system includes a memory shared by a processor and a coherent accelerator device (CAD). The memory includes a work queue directly accessible by the accelerator functional unit (AFU) within the CAD and by the processor utilizing the same effective addresses. The coherent computer system provides accelerator functionality when the accelerator is unavailable by implementing a virtual AFU to carryout accelerator function while the AFU is unavailable. The virtual AFU is a functional logical equivalent of the AFU and is coherent with the processor. When the AFU becomes available, the virtual AFU is disabled and the accelerator is enabled to allow the accelerator to carryout accelerator functionality.Type: ApplicationFiled: August 26, 2015Publication date: March 2, 2017Inventor: Michael C. Hollinger
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Publication number: 20170060608Abstract: Assessing the need for disaster recovery (DR) protection for a virtual application may include accessing resource consumption history for constituent VMs that support the virtual application. The resource consumption history may include usage metrics corresponding to resources used by each VM. A change in a cost of downtime of the given virtual application may be produced and used to assess criteria or rules. The given virtual application may be designated for DR protection based on an assessment of the criteria. DR protection may be activated for the designated virtual applications. The DR protection may automatically expire after a period of time.Type: ApplicationFiled: August 27, 2015Publication date: March 2, 2017Inventors: Amarnath Raghunathan, Yanislav Genkov Yankov
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Publication number: 20170060609Abstract: A shared pool of configurable computing resources is managed. The shared pool of configurable computing resources has a set of physical hosts, a set of virtual machines, and a set of containers. A set of resource usage data for the set of containers is monitored to detect a triggering event which corresponds to the set of resource usage data. Using the set of resource usage data, a container arrangement is determined. The container arrangement indicates a relationship with respect to the set of containers, the set of virtual machines, and the set of physical hosts. In response to both determining the container arrangement and detecting the triggering event, the container arrangement is established.Type: ApplicationFiled: August 28, 2015Publication date: March 2, 2017Inventors: Joseph W. Cropper, Jeffrey W. Tenner
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Publication number: 20170060610Abstract: A dynamic content disk for a virtual computing instance is created as a thinly-provisioned virtual disk having a file system that is synthesized in accordance with a set of applications that are provisioned for a virtual machine (VM). To limit the allocated size of the dynamic content disk, a filter is attached to the dynamic content disk to intercept input-output operations (IOs) directed to the dynamic content disk and convert them to IOs directed to an application virtual disk that stores the actual files of the applications that are provisioned for the VM. The application virtual disk may be stored on different back-ends, such as storage area network (SAN), network file system, virtual SAN, cloud storage, or local storage.Type: ApplicationFiled: August 28, 2015Publication date: March 2, 2017Inventors: Christoph KLEE, Aman NIJHAWAN
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Publication number: 20170060611Abstract: Optimized placement of virtual machines in a cloud environment is based on factors that include processor-memory affinity. A smart migration mechanism (SMM) predicts an optimization score for multiple permutations of placing virtual machines on a target system to create an optimal move list. The optimization score is a theoretical score calculated using dynamic platform optimization (DPO). The SMM may allow the user to set initial parameters and change the parameters to create potential changes lists. The move lists are ranked to allow the user to select the optimal change list to provide the best affinity, quickest fulfillment of requirements and least disruption for a given set of parameters.Type: ApplicationFiled: August 29, 2015Publication date: March 2, 2017Inventors: Daniel C. Birkestrand, Peter J. Heyrman, Edward C. Prosser
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Publication number: 20170060612Abstract: A method for controlling a virtual machine, on a terminal device, the method includes receiving a request to create a virtual machine sent by a terminal device via an instant communication software and granting the terminal device an authority to create the virtual machine in response to the received request to create the virtual machine, receiving setting information of the virtual machine sent by the terminal device via the instant communication software when the server grants the terminal device the authority to create the virtual machine, and creating the virtual machine according to the received setting information of the virtual machine.Type: ApplicationFiled: October 23, 2015Publication date: March 2, 2017Inventors: MING-CHIN HO, CHIH-YUAN HUANG
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Publication number: 20170060613Abstract: In an example, a computer system includes a hardware platform and a hypervisor executing on the hardware platform. The hypervisor includes a kernel and a plurality of user-space instances within a user-space above the kernel. Each user-space instance is isolated from each other user-space instance through namespaces. Each user-space instance includes resources confined by hierarchical resource groups. The computer system includes a plurality of virtual hypervisors, where each virtual hypervisor executes in a respective user-space instance of the plurality of user-space instances.Type: ApplicationFiled: December 29, 2015Publication date: March 2, 2017Inventors: Andrei WARKENTIN, Harvey TUCH, Cyprien LAPLACE, Alexander FAINKICHEN
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Publication number: 20170060614Abstract: A virtual computer system includes an external event acquisition controller, an external event storing unit, and a snap shot creating unit. The external event acquisition controller performs control for acquiring an event regarding an external device provided outside a virtual computer which mounts a guest operating system in which an application program is installed. The external event storing unit stores the external event acquired by the external event acquisition controller. The snap shot creating unit creates a snap shot of the guest operating system including the application program after the external event is stored in the external event storing unit.Type: ApplicationFiled: January 21, 2016Publication date: March 2, 2017Applicant: FUJI XEROX CO., LTD.Inventors: Toshiaki YOSHINARI, Koji NISHIYAMA
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Publication number: 20170060615Abstract: Techniques are disclosed for deploying and maintaining appliances in a hybrid cloud computing system which includes an on-premise data center and a public cloud computing system configured to provide a common platform for managing and executing virtual workloads. Appliances to be deployed may include those required (or useful) for hybrid operations, including a cloud gateway appliance, a wide area network (WAN) optimizer, a layer 2 (L2) concentrator, and a mobility agent that handles virtual machine (VM) migration traffic. Such appliances are deployed first on the on-premise data center, and remote jobs are then sent to the public cloud to deploy the same appliances thereon. After deployment, the appliances deployed on the on-premise data center and corresponding appliances on the public cloud share configuration states and may further be wired together to communicate via secure encrypted tunnels.Type: ApplicationFiled: April 25, 2016Publication date: March 2, 2017Inventors: SACHIN THAKKAR, Debashis Basak, Abhinav Vijay Bhagwat, Narendra Kumar Basur Shankarappa, Serge Maskalik
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Publication number: 20170060616Abstract: A migration controlling method includes reading state information indicating stats of virtual machines and physical machines, reading migration information corresponding to information of virtual machines, physical machine of migration source, and physical machine of migration destination, instructing migration of a first virtual machine to the second physical machine designated on the basis of the state information and migration information, instructing migration of a second virtual machine not instructed to migrate to the second physical machine to a third physical machine except of the second physical machine, and updating the state information on the basis of the state of the plurality of virtual machines and the plurality of physical machines after migration of the first and second virtual machines.Type: ApplicationFiled: August 24, 2016Publication date: March 2, 2017Applicant: FUJITSU LIMITEDInventor: Koichi Onoue
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Publication number: 20170060617Abstract: Embodiments of the present invention provide efficient systems and methods for scaling past the Java Virtual Machine (JVM) thread limit in a Java Virtual Machine. Embodiments of the present invention can be used to ensure that a received workload is executed, even if the workload is greater than a JVM thread limit of the system, by spawning a reduced number of threads from a main process, in order to provide enough resources for the effective execution of a received workload.Type: ApplicationFiled: September 7, 2016Publication date: March 2, 2017Inventor: Russell I. Wilson
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Publication number: 20170060618Abstract: Embodiments of the present invention provide efficient systems and methods for scaling past the Java Virtual Machine (JVM) thread limit in a Java Virtual Machine. Embodiments of the present invention can be used to ensure that a received workload is executed, even if the workload is greater than a JVM thread limit of the system, by spawning a reduced number of threads from a main process, in order to provide enough resources for the effective execution of a received workload.Type: ApplicationFiled: September 7, 2016Publication date: March 2, 2017Inventor: Russell I. Wilson
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Publication number: 20170060619Abstract: In an exemplary embodiment, a virtual disk file can be assigned an identifier and a virtual disk files that is dependent on the virtual disk file can include a copy of the identifier. In the instance that the virtual disk file is opened and data is modified that causes the contents of a virtual disk extent to change the identifier can be changed. If the virtual disk file and the dependent virtual disk file are used to instantiate a virtual disk the difference between identifiers can be detected, which is indicative of the fact that the virtual disk may be corrupted. Other techniques are described in the detailed description, claims, and figures that form a part of this document.Type: ApplicationFiled: November 10, 2016Publication date: March 2, 2017Inventors: John A. Starks, Dustin L. Green, Todd William Harris, Mathew John, Senthil Rajaram, Eric Traut
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Publication number: 20170060620Abstract: Techniques are disclosed for maintaining high availability (HA) for virtual machines (VMs) running on host systems of a host cluster, where each host system executes a HA module in a plurality of HA modules and a storage module in a plurality of storage modules, where the host cluster aggregates, via the plurality of storage modules, locally-attached storage resources of the host systems to provide an object store, where persistent data for the VMs is stored as per-VM storage objects across the locally-attached storage resources comprising the object store, and where a failure causes the plurality of storage modules to observe a network partition in the host cluster that the plurality of HA modules do not. In one embodiment, a host system in the host cluster executing a first HA module invokes an API exposed by the plurality of storage modules for persisting metadata for a VM to the object store.Type: ApplicationFiled: November 15, 2016Publication date: March 2, 2017Inventors: Marc Sevigny, Keith Farkas, Christos Karamanolis
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Publication number: 20170060621Abstract: Techniques for executing jobs in a hybrid cloud computing system. A job defines multiple states and tasks for transitioning between states. Jobs are passed between systems that execute different tasks via a message bus, so that the different tasks may be executed. A job manager controls execution flow of jobs based on a job descriptor that describes the job.Type: ApplicationFiled: August 28, 2015Publication date: March 2, 2017Inventors: Mark Bryan WHIPPLE, Sachin THAKKAR, Debashis BASAK, Serge MASKALIK, Narendra Kumar BASUR SHANKARAPPA
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Publication number: 20170060622Abstract: A data processing system and method integrates speed or transactional sensor data processing with batch level processing of sensor data using a hybrid-Lambda network architecture. In such a hybrid-Lambda network architecture, speed or transactional processing is performed, batch level processing is performed, and batch level processing results can be combined and integrated with the transactional processing events, and visa-versa, such that real time results can be influenced by long term analytics, and long term analytics can be influenced by real time events. For such processing, both speed or transactional and batch level, can occur as result of any type of sensor data being received, processed, and substantially immediately stored in immutable storage locations, for later retrieval and analysis.Type: ApplicationFiled: February 29, 2016Publication date: March 2, 2017Applicant: Savi Technology, Inc.Inventors: James Haughwout, Michael Souders
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Publication number: 20170060623Abstract: A method determines a schedule indicator value for each of a plurality of schedule data entries based on whether each of a set of recorded tasks has been allocated to one or more identifier data names in one or more of a set of time periods in accordance with the first schedule data to generate schedule portion data. A hard constraint indicator value is determined for each of a plurality of hard constraint data entries based on whether at least one hard constraint has been violated by the allocation of the set of recorded tasks to one or more of the identifier data names in one or more of the time periods in accordance with the schedule data to generate hard constraint portion data. The data structure is generated based on the determined schedule portion and hard constraint portion data encoding the schedule data into a data structure.Type: ApplicationFiled: March 10, 2016Publication date: March 2, 2017Inventors: Alex Syrichas, Alan Cripsin
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Publication number: 20170060624Abstract: A method for migration of operations between CPU cores, the method includes: processing, by a source core, one or more tasks and one or more interrupt service routines; accessing a mapping corresponding to a task of the one or more tasks and an interrupt service routine of the one or more interrupt service routines; identifying, based on the mapping, a target core that corresponds to the task and the interrupt service routine; blocking the task from being processed by the source core in response to identifying the target core; in response to identifying the target core, disabling an interrupt corresponding to the interrupt service routine; in response to identifying the target core, assigning the task and the interrupt to the target core; after assigning the interrupt to the target core, enabling the interrupt; and after assigning the task to the target core, processing the task by the target core.Type: ApplicationFiled: August 26, 2015Publication date: March 2, 2017Inventors: Kent Prosch, Matthew Weber, Arindam Banerjee, Ben McDavitt
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Publication number: 20170060625Abstract: An electronic device includes a plurality of processes, an interrupt waiting unit for each of the processes, and an interrupt handler. The interrupt handler processes the interrupt. The interrupt waiting unit sets an interrupt waiting flag to wait for an occurrence of the interrupt. The interrupt handler, when the interrupt occurred, sets an interrupt style of the occurred interrupt and releases the interrupt waiting flag from the set state. The interrupt waiting unit, when the interrupt waiting flag was released from the set state, sets the interrupt waiting flag if the interrupt style set by the interrupt handler is not an interrupt style matched with the process, and operates the process if the interrupt style set by the interrupt hander is the interrupt style matched with the one of the processes. The interrupt waiting flag is located to each of the processes.Type: ApplicationFiled: July 8, 2016Publication date: March 2, 2017Applicant: KYOCERA Document Solutions Inc.Inventor: Shuntaro TSUJI
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Publication number: 20170060626Abstract: A method for enhanced restart of a core dumping application is provided. The method includes stopping a plurality of threads in an address space, except for the thread performing the core dump. Computational segments are remapped to client segments. Each open file descriptor in the address space is closed. The application is terminated and the client segments are flushed to external storage.Type: ApplicationFiled: November 10, 2016Publication date: March 2, 2017Inventors: Anand T. Desai, Andrew Dunshea, Antonio Garcia, Douglas Griffith, Anil Kalavakolanu