Abstract: Embodiments provide a solidly-mounted bulk acoustic wave (BAW) resonator and method of making same. In embodiments, the BAW resonator may include a first resonator and a second resonator that are coupled with one another via a top electrode layer. A capacitive element may be included in the BAW resonator in parallel with the first resonator. Other embodiments may be described and claimed.

Abstract: Described embodiments include a surface acoustic wave device, method, and apparatus. The device includes a piezoelectric substrate and a configurable electrode assembly. The configurable electrode assembly includes a plurality of spaced-apart elongated electrode elements electromechanically coupled with the piezoelectric substrate. The assembly includes a first signal bus crossing each of the plurality of electrode elements and electrically isolated therefrom. The assembly includes a first matrix of addressable switches. Each addressable switch of the first matrix configured to electrically couple a respective electrode element of the plurality of electrode elements with the first signal bus. The assembly includes a second signal bus crossing each of the plurality of electrode elements and electrically isolated therefrom. The assembly includes a second matrix of addressable switches.

Abstract: A high-frequency module includes a filter unit and first and second external connection terminals. The filter unit includes first and second terminals and a plurality of SAW resonators. The plurality of SAW resonators are connected to one another by connection conductors. A matching element is connected between the first terminal and the first external connection terminal, and a matching element is connected between the second terminal and the second external connection terminal. At least one of the matching elements is inductively coupled or capacitively coupled to at least one of the connection conductors located at a position such that at least one of the SAW resonators is interposed between the matching element and the connection conductor.

Abstract: In an exemplary embodiment, the communication device including an analog filter, where a digital signal processor sets the gain of the analog filter and the pole location of the filter simultaneously in order to maintain the filter pole location at a desired value or within a desired range. In further exemplary embodiments, the methodology to simultaneously set the gain and the pole location of the filters.

Abstract: Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the dock signals output from the push-pull buffers.

Abstract: A method of operating a single-tuner radio includes tuning into a first frequency. A pause in a first signal associated with the first frequency is detected. Tuning is switched from the first frequency to a second frequency during the pause. Fieldstrength, multipath, adjacent channel energy, frequency offset and FM modulation for the second frequency are measured. Tuning is switched from the second frequency to the first frequency. Tuning is switched from the first frequency to the second frequency dependent upon the measuring step.

Abstract: Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit.

Abstract: Clock generation circuit that track critical path across process, voltage and temperature variation. In accordance with a first embodiment of the present invention, an integrated circuit device includes an oscillator electronic circuit on the integrated circuit device configured to produce an oscillating signal and a receiving electronic circuit configured to use the oscillating signal as a system clock. The oscillating signal tracks a frequency-voltage characteristic of the receiving electronic circuit across process, voltage and temperature variations. The oscillating signal may be independent of any off-chip oscillating reference signal.

Abstract: Frequency detector and oscillator circuits are disclosed. Example frequency detector and oscillator circuits disclosed herein include a current approximation circuit coupled to an external clock operating at a target frequency. In some examples, the current approximation circuit is configured to determine a magnitude of a first current to charge a capacitor to reach a reference voltage during a first set of clock cycles generated by the external clock. In some examples, the current approximation circuit is further configured to generate an output current based on the magnitude of the first current and to use the output current to produce a comparator output. In some examples, the frequency detector and oscillator circuits further include a latching circuit coupled to receive the comparator output from the current approximation circuit. In some such examples, the latching circuit is configured to generate oscillating signals at the target frequency based on the comparator output.

Abstract: A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT1) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input signal (DATA) in relation to a second threshold level (TP2). The second threshold level (TP2) is distinct from the first threshold level (TP1). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUT1 , DOUT2) have the same logical state, and with a second logical state they have different logical states.

Abstract: A double half latch circuit includes a first stage coupled to receive a local input enable signal on an input of a second logic gate, and a complement of the clock signal on an input of a third logic gate, and further includes a fourth logic gate coupled to generate an intermediate enable signal based on states of the local input enable signal the complement of the clock signal. A second stage includes a fifth logic gate coupled to receive the complement of the clock signal, and a sixth logic gate coupled to receive the intermediate enable signal, and is configured to generate the output enable signal. The double half-latch circuit is transparent to the state changes of the local input enable signal when the clock signal is low and opaque to state changes of the local input enable signal when the clock signal is high.

Abstract: A linear transformer driver includes at least one ferrite ring positioned to accept a load. The linear transformer driver also includes a first, second, and third power delivery module. The first power delivery module sends a first energy in the form of a first pulse to the load. The second power delivery module sends a second energy in the form of a second pulse to the load. The third power delivery module sends a third energy in the form of a third pulse to the load. The linear transformer driver is configured to form a flat-top pulse by the superposition of the first, second, and third pulses. The first, second, and third pulses have different frequencies.

Abstract: Methods and apparatus for minimizing average quiescent current for a desire voltage error in a comparator are disclosed. An example method includes receiving a first voltage and a reference voltage, outputting a second voltage when the first voltage is lower than the reference voltage, wherein the outputting of the second voltage increases the first voltage, counting a number of clock cycles while the first voltage is higher than the reference voltage, comparing the number of clock cycles to a maximum number of clock cycles and a minimum number of clock cycles, when the number of clock cycles is above the maximum number of clock cycles, decreasing a frequency of a clock associated with the number of clock cycles, and when the number of clock cycles is below the minimum number of clock cycles increase the frequency of the clock.

Abstract: A state wherein offset voltage is reduced can be maintained regardless of environmental fluctuation. A differential amplification unit has differential pair transistors, and amplifies a difference between input voltages. An offset voltage measurement unit samples offset voltage generated due to an imbalance in the current drive capacities of the differential pair transistors in a first mode, and determines the polarity of the sampled offset voltage in a second mode. A control unit switches the operating mode between the first mode and second mode, and outputs a control signal for correcting the offset voltage in accordance with the polarity determination result when in the second mode. An offset voltage correction unit corrects the offset voltage based on the control signal.

Abstract: First to N-th selection signals each instantaneously having a first logic level when representing selection and a second logic level when representing deselection are generated based on selection designation data. The first to N-th selection signals are individually latched, and first to N-th delayed selection signals are generated by individually delaying the first to N-th selection signals by a greater amount of delay when the latched selection signals transition from the first logic level to the second logic level than when the latched selection signals transition from the second logic level to the first logic level. A delayed data signal is selected corresponding to a delayed selection signal having the first logic level among the first to N-th delayed selection signals. The selected delayed data signal is output.

Abstract: A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state. A low phase shift attenuation at high RF frequencies can be achieved by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to provide broadband operation, distribute parasitic influences, and improve isolation to achieve higher attenuation at higher frequencies while still maintaining low phase shift operational characteristics. In an alternative embodiment, extension to even higher frequencies can be achieved by utilizing a quarter-wave transmission line element at the signal interfaces of each signal path, thereby improving insertion loss and power handling.

Abstract: Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may be configured to monitor a voltage level of a power supply coupled to the custom circuit or memory. A delay amount of a delay unit within the custom circuit or memory may be changed in response to a determination that the voltage level of the power supply has changed.

Abstract: A zero-crossing voltage detection circuit for detecting a phase voltage of a converter includes a comparator, a first transistor and a second transistor. The first transistor has a first base, a first collector and a first emitter. The first base couples with the first collector. The first emitter receives the phase voltage. The first collector provides a first voltage to a first terminal of the comparator. The second transistor has a second base, a second collector and a second emitter. The second base couples with the first base. The second base couples with the second collector. The second emitter receives a ground voltage. The second collector provides a second voltage to a second terminal of the comparator. The comparator compares the first voltage with the second voltage to generate a zero-crossing voltage signal.

Abstract: A decoding circuit may include a section information generation unit suitable for generating section information corresponding to a section in which an input signal has a first value, a period information generation unit suitable for generating period information corresponding to a period of the input signal, a reference information generation unit suitable for generating reference information by dividing a value of the period information by a given value, and a comparison unit suitable for determining a logic value of the input signal by comparing the section information with the reference information.

Abstract: In a multiplexer circuit which loads N data segments (N is an integer of N<M) led by an arbitrary data segment from a first register storing M data segments (M is an integer equal to or larger than two) to a second register, an intermediate register is disposed between the first register and the second register. A first selection circuit between the first register and the intermediate register and a second selection circuit between the intermediate register and the second register are designed based on a value of L for minimizing a circuit amount of the first selection circuit and the second selection circuit. The value of L for minimizing the circuit amount is calculated based on values of the M and the N. Therefore, it is possible to reduce the circuit amount of the multiplexer circuit capable of performing data access with respect to large-volume data.

Abstract: A power electronic device includes first and second electronic switches, each integrated on a package having a low parasitic inductance, a supply terminal and a ground terminal. The first conduction terminal of the first switch may be coupled with the supply terminal, and the second conduction terminal of the second electronic switch may be coupled with the ground terminal. The corresponding control terminals of the switches may be coupled to corresponding pilot drivers. The package may include first and second electric terminals, wherein the second conduction terminal of the first switch is coupled to the first electric terminal, and the first conduction terminal of the second switch is coupled to the second electric terminal. A first inductance may be interposed between the first electric terminal and the output terminal and/or a second inductance interposed between the second electric terminal and the output terminal.

Abstract: An electronic switch is connected in series with a load dependent on an input signal. The electronic switch is operated in a first operation mode for a first time period after a signal level of the input signal has changed from an off-level to an on-level. The first operation mode includes driving the electronic switch dependent on a voltage across the load and dependent on a temperature of the electronic switch. The electronic switch is operated in a second operation mode after the first time period. The second operation mode includes driving the electronic switch dependent on the temperature according to a hysteresis curve.

Abstract: An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in an in-circuit mode or in a bypass mode. Embodiments of the invention allow for both a single switch in the series input path while still having the ability to isolate the bypass path from an input matching network. In both modes, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.

Abstract: An adaptive duo-gate MOSFET includes a trench MOSFET and an adaptive element. The trench MOSFET includes a source, a drain, a first gate, a second gate, and a dielectric layer between the first and second gates. Herein, the first gate may generate charge-coupling in blocking operation, and the second gate may form channel in the trench MOSFET when in conduction operation. The adaptive element is electrically coupled to the first gate, the second gate, and the source respectively. When a potential difference between the second gate and the source is larger than a predetermined value, the first gate and the source are electrically disconnected and then the first gate and the second gate are electrically connected. After a predetermined time, the first gate and the second gate are electrically disconnected and then the first gate and the source are electrically connected.

Abstract: The invention relates generally to downhole measurement tools having a regulated voltage power supply and methods of use thereof. The downhole measurement tools are associated with electrical submersible pumps for providing a stabilization technique for a five (5) volt power supply over a wide temperature range. A voltage regulator circuit for the downhole measurement tools has a temperature dependent resistance to adjust the feedback of the regulated voltage to compensate for the temperature coefficient effects of the other components in the regulator circuit.

Abstract: A method for controlling a configuration in an integrated circuit device with at least one controllable input/output port having a data output driver, a data input driver, a controllable pull-up resistor, a controllable pull-down resistor, each connected with an external pin of the integrated circuit device, has the steps of: enabling only the pull-up resistor and reading the associated input through the data input driver as a first bit; enabling only the pull-down resistor and reading the associated input through the data input driver as a second bit; tri-stating the first port and reading the associated input through the data input driver as another bit; encoding a value from the read bits; and determining a firmware operation form the encoded value.

Abstract: One embodiment provides a magnetic logic device including: a first conductive thin wire; a second conductive thin wire; and a third conductive thin wire that electrically connects the first conductive thin wire and the second conductive thin wire. The first to third conductive thin wires commonly includes: a first non-magnetic metal layer; a second non-magnetic metal layer; and a magnetic metal layer sandwiched between the first non-magnetic metal layer and the second non-magnetic metal layer.

Abstract: As a technique for attaining a reduction in power consumption, there is a technique for reducing power consumption using a spin wave. No specific proposal concerning spin wave generation, spin wave detection, and a latch technique for information has been made. A device applies an electric field to a first electrode of a nonmagnetic material using a thin line-shaped stacked body including a first ferromagnetic layer and a nonmagnetic layer to thereby generate a spin wave in the first ferromagnetic layer, and detects a phase or amplitude of the spin wave propagated in the first ferromagnetic layer using a second electrode of a ferromagnetic material with a magnetoresistance effect.

Abstract: An output buffer with an offset cancellation structure for an LCD source driver includes an operational amplifier, for driving an output signal of the output buffer according to a data signal from a data input terminal of the output buffer; a reference voltage generator, for generating a reference voltage and inputting the reference voltage to the operational amplifier; and a sampling capacitor, coupled between a second input terminal of the operational amplifier and the data input terminal of the output buffer in a first phase, and coupled between the second input terminal of the operational amplifier and an output terminal of the operational amplifier in a second phase, wherein the second input terminal of the operational amplifier is further coupled to the output terminal of the operational amplifier in the first phase. The output signal outputs the data signal where the offset voltage is cancelled in the second phase.

Abstract: A circuit comprising a first injection BJT in a common-base configuration and configured to output a first injection current at its collector. A first multiple-collector BJT is in an open collector configuration, is electrically coupled to the first injection BJT, and is arranged to receive the first injection current at its base. The first multiple-collector BJT has a capacitance load at one of its collectors. A first supply voltage is electrically coupled to the first injection BJT. The first supply voltage is configured to dynamically adjust during operation of the circuit in response to a change in the capacitance load of the first multiple-collector BJT.

Abstract: An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

Abstract: A circuit includes a state capture device to capture a logic state of a reset selection cell in response to a logic state input. A cell reset node defines a reset state of the reset selection cell. A selection device passes the captured logic state from the state capture device or the reset state from the cell reset node to an output of the reset selection cell based on a state of a control input to the selection device.

Abstract: In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT in the programmable IC. The LUT further includes LUT logic having a plurality of LUTs each coupled to a common set of the input terminals. The LUT further includes a plurality of multiplexers having inputs coupled to outputs of the plurality of LUTs, and an output multiplexer having inputs coupled to outputs of the plurality of multiplexers. The LUT further includes a plurality of cascading multiplexers each having an output coupled to a control input of a respective one of the plurality of multiplexers, each of the plurality of cascading multiplexers comprising a plurality of inputs, at least one of the plurality of inputs coupled to the cascading input.

Abstract: A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out.

Abstract: An oscillator amplifier biasing technique configures an oscillator amplifier to operate at a bias point causing loading on a tank circuit to have reduced or negligible dependence on amplifier bias conditions or device characteristics. The bias signal level may vary with variation in temperature. The oscillator amplifier biasing technique includes determining a bias signal level that has a minimum sensitivity of the frequency of oscillation as a function of temperature. The technique may store associated data in non-volatile memory to describe the bias signal level dependence on temperature. A digital-to-analog converter may drive the bias signal of the oscillator to the minimum sensitivity point as a function of temperature. The technique may substantially reduce effects of up-conversion of flicker noise in the oscillator output signal as well as improve frequency accuracy in the presence of effects such as mechanical strain and/or aging.

Abstract: An asynchronous digital logic is used to provide a pulse. A pulse train is filtered to determine an analog measurement based at least in part on the duty cycle of the pulse. The analog measurement is compared with a tunable reference associated with a programmable locked delay for the DLL. A digital code is sequenced based at least in part on the comparison. A digitally controlled delay line is programmed based at least in part on the digital code.

Abstract: Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time.

Abstract: Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device. Aspects of the present disclosure present a method and apparatus for operating in an open loop control (OLC) mode of the PLL device for generating a periodic signal. During the OLC mode, clocking of circuitry interfaced with a digitally-controlled oscillator (DCO) of the PLL device can be disabled. A PLL output frequency associated with the periodic signal generated by the DCO can be controlled directly through a digital control word input into the DCO.

Abstract: A design method for a phase-locked loop comprises: a controlled-frequency oscillator; a phase comparator, to determine a phase difference between an output signal of the controlled-frequency oscillator and a reference signal; a corrector to receive as input a signal representative of the phase difference and to generate at its output a first correction signal; at least one second corrector, to receive as input a signal representative of or affected by a phase noise of the reference signal or of the output signal of the controlled-frequency oscillator and to generate at its output a second correction signal; and a circuit for generating a slaving signal for the controlled-frequency oscillator on the basis of the first and second correction signals; the method using the H-infinity method. Method for fabricating such a loop comprising a design step implementing this method. Phase-locked loop thus obtained.

Abstract: A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes a delay line having a length extending beyond a predetermined length required for operation of the phase-locked loop. The device further includes a tap tuning logic circuit coupled to the delay line. The delay line receives an input signal and a tuning voltage from the phase frequency detector, charge pump and loop filter circuits and generates a plurality of tapped output signals. The plurality of tapped output signals is received by the integrated digital multi-rate clock generator configured to create a plurality of clock signals.

Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

Abstract: A detection device includes a driving circuit and a detection circuit. The detection circuit includes first and second electric charge-voltage conversion circuits to which first and second detection signals are input, first and second gain adjustment amplifiers that amplify output signals of the circuits, a switching mixer that has first and second input nodes to which the output signals of the first and second gain adjustment amplifiers are input, and performs differential synchronous detection thereon on the basis of a synchronization signal from the driving circuit, so as to output first and second output signals to first and second output nodes, first and second filters that receive the first and second output signals from the first and second output nodes of the switching mixer, and an A/D conversion circuit that receives output signals from the first and second filters so as to perform differential A/D conversion thereon.

Abstract: A dual delta-sigma modulator includes a first modulator, a second modulator, and a shared amplifier coupled to the first and second modulators. The first modulator includes an integrator configured to generate a first modulator output signal. The second modulator includes a second integrator configured to generate a second modulator output signal. The shared amplifier is configured to assist the first integrator integrating a difference between a first analog input signal and a first modulator output signal from the first modulator during a first period of time and to assist the second integrator integrate a difference between a second analog input signal and a second modulator output signal from the second modulator during a second period of time.

Abstract: Various aspects facilitate gain adjustment associated with an analog to digital converter. A capacitor array comprises a plurality binary-weighted capacitors and generates an output voltage received by a comparator based on an input voltage and a reference voltage. A gain calibration component receives the input voltage and applies a modified input voltage that corresponds to a portion of the input voltage to the output voltage generated by the capacitor array component.

Abstract: An analog to digital converter contain a plurality of comparators, each having a plurality of positive input voltage transistors and a plurality of negative input voltage transistors. Each positive input transistor is in communication with a positive input voltage, and each negative input transistor is in communication with a negative input voltage. Each comparator is configured to adjust a positive reference voltage and a negative reference voltage used to generate a binary comparator output for each comparator indicating a result of a comparison between a voltage differential defined by the positive input voltage and the negative input voltage and a unique voltage range indicated by a unique digital reference signal communicated to each comparator.

Abstract: A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset.

Abstract: A process variable transmitter, includes an analog-to-digital (A/D) converter that receives a sensor signal provided by a sensor that senses a process variable and converts the sensor signal to a digital signal. A processor receives the digital signal and provides a measurement output indicative of the digital signal. A noise detector receives the sensor signal and generates a first value indicative of a number of positive noise events relative to a positive threshold value and a second value indicative of a number of negative noise events relative to a negative threshold value. The processor evaluates the noise count and generates a noise output, indicative of detected noise, based on the first and second values.

Abstract: A cognitive signal converter adapted to produce a digital output signal based on an analog input signal comprises an analog-to-digital converter (ADC) and a cognitive network. The ADC is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample based on the process clock signal. The cognitive network is adapted to receive the digital converted signal of the ADC, control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source, and produce the digital output signal based on the received digital converted signal. Corresponding integrated circuit, electronic device and method are also disclosed.

Abstract: An A/D conversion device includes: a level shifter circuit configured to level-shift an analog voltage of an input voltage signal to generate a conversion signal; an A/D converter configured to A/D-convert a voltage of the conversion signal supplied from the level shifter circuit. The level shifter circuit subtracts an instantaneous voltage value of the input voltage signal from a reference voltage so as to output a signal value as the conversion signal.

Abstract: A digital-to-analog converter (DAC) including a DAC core circuit having a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits. The DAC also includes a clock circuit responsive to a clock input signal at one frequency and outputting a clock output signal at another frequency. The DAC also includes a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, where the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material.