Patents Issued in March 21, 2017
  • Patent number: 9599655
    Abstract: A semiconductor device capable of simplifying wiring work is provided. A semiconductor device includes a semiconductor element (insulated gate bipolar transistor IGBT) provided with an emitter main electrode and an emitter sense electrode, an integrated circuit having a detection terminal and a mold resin body that seals the semiconductor element and the integrated circuit, and a lead. The lead is provided with an inner lead part sealed in the mold resin body and electrically connected to the emitter sense electrode, an inner lead part sealed in the mold resin body and electrically connected to the emitter main electrode, and an outer lead part connected to the lead part on one side, connected to the inner lead part on the other side and exposed outside the mold resin body.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 21, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroyuki Nakamura
  • Patent number: 9599656
    Abstract: At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: March 21, 2017
    Assignees: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Suresh Uppal, Andreas Kerber, William McMahon, Eduard A. Cartier
  • Patent number: 9599657
    Abstract: Approaches for performing in line wafer testing are provided. An approach includes a method that includes generating a radio frequency (RF) test signal, and applying the RF test signal to a device under test (DUT) in a wafer using a buckling beam probe set with a predefined pitch. The method also includes detecting an output RF signal from the DUT in response to the applying the RF test signal to the DUT, and sensing at least one frequency component of the detected output RF signal.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: March 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hanyi Ding, John Ferrario, Barton E. Green, Stephen Moss, Mustapha Slamani
  • Patent number: 9599658
    Abstract: The disclosure relates to a method for signaling partial shadowing within a PV generator including at least two partial PV generators connected in parallel. The method includes performing a reference impedance measurement on each of the at least two partial PV generators in a state of uniform irradiation of the PV generator, and determining at least one reference resonant property of each of the at least two partial PV generators from the reference impedance measurement. Furthermore, impedance measurements are carried out on the at least two partial PV generators at a first operating point of the PV generator during operation of the PV generator. Resonant properties of the partial PV generators are determined from the impedance measurements. Partial shadowing within the PV generator is detected and signaled if a difference between the resonant properties of the partial PV generators at the first operating point differs from a difference between the reference resonant properties of the partial PV generators.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: March 21, 2017
    Assignee: SMA SOLAR TECHNOLOGY AG
    Inventors: Christopher Merz, Sebastian Bieniek, Markus Hopf, Felix Eger
  • Patent number: 9599659
    Abstract: An inspection device is provided including a light emitting element configured to emit light, a light receiving element arranged so as to face the light emitting element and configured to receive the light, where one of the light emitting element and the light receiving element is used as a to-be-inspected element, and the other one of the light emitting element and the light receiving element is used as an inspection element that inspects the to-be-inspected element, a housing configured to accommodate the inspection element, and a lid configured to be detachable from the housing. In the inspection device, one of the housing and the lid is provided with an arrangement unit to which the to-be-inspected element is set in a detachable manner, and the lid includes a contact unit that electrically contacts the to-be-inspected element by touching and detaching from the to-be-inspected element.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: March 21, 2017
    Assignee: Ricoh Company, Ltd.
    Inventor: Keiji Tsuda
  • Patent number: 9599660
    Abstract: Disclosed are advances in the arts with novel methods and apparatus for detecting faulty connections in an electrical system. Exemplary preferred embodiments include basic, ASIC, AC, DC, and RF monitoring techniques and systems for monitoring signals at one or more device loads and analyzing the monitored signals for determining fault conditions at the device loads and/or at the main transmission lines. The invention preferably provides the capability to test and monitor electrical interconnections without fully activating the host system.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: March 21, 2017
    Assignee: TRIUNE IP, LLC
    Inventors: Ross E Teggatz, Wayne T Chen, Brett Smith
  • Patent number: 9599661
    Abstract: Embodiments of the invention describe apparatuses, systems and method for utilizing testing instruments having electrical interconnects formed from High Density Interconnect (HDI) multi-layer substrates. Electrical signals may be routed between devices mounted on HDI substrates by way of conductive interconnects formed within their multiple layers. The conductive interconnects are generally comprised of metal interconnects and vias, where each via penetrates between layers to couple a metal interconnect from one layer to a metal interconnect from another layer. By utilizing HDI substrates, embodiments of the invention enable “breaking out” the signal pins on multiple layers, perhaps double or triple the routing layers of the package channel; however, the geometry of the transmission lines and other factors may be chosen to ensure channel parameters such as impedance and crosstalk closely emulate the final device package.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventor: Timothy D. Wig
  • Patent number: 9599662
    Abstract: The present invention provides a device for conditioning semiconductor chips and a corresponding test method. The device comprises a chip temperature control means for receiving a semiconductor chip or a plurality of semiconductor chips and comprises a base body which can be flushed with a fluid for temperature control and which comprises a corresponding number of recesses which extend from a front face to a rear face of the base body; a corresponding number of chip bonding pedestals which are inserted, in thermal contact with the base body, into the recesses which comprise a chip receiving region on the front face and a wiring means on the inside which is constructed for supplying electrical signals from and/or to the semiconductor chip inserted in the respective chip receiving region; and a motherboard attached to the rear face in such a way that the wiring means of the chip bonding pedestals is electrically connected to a wiring means of the motherboard.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: March 21, 2017
    Assignee: ERS Electronic GmbH
    Inventor: Klemens Reitinger
  • Patent number: 9599663
    Abstract: A probe method includes setting an allowable temperature range, the allowable temperature range including a test temperature and ensuring contact between a pad of a circuit substrate and a needle of a probe card, providing the probe card with a temperature within the allowable temperature range, contacting the needle of the probe card to the pad of the circuit substrate, and supplying a test current to the pad through the needle to test the circuit substrate.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: March 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Boo Kang, Ki-Sub Lim
  • Patent number: 9599664
    Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke D. Lacroix, Mark C. H. Lamorey, Steven F. Oakland, Janak G. Patel, Kerry P. Pfarr, Peter Slota, Jr., David B. Stone
  • Patent number: 9599665
    Abstract: A method for testing a semiconductor device is disclosed. The method comprises positioning a probe card comprising a plurality of probes above the semiconductor device and moving the probe card in a vertical direction towards the semiconductor device. The plurality of probes are moving in a vertical direction towards a plurality of electrical structures of the semiconductor device until each probe of the plurality of probes has made mechanical contact with a corresponding electrical structure of the plurality of electrical structures with a minimum quantity of force. The each probe of the plurality of probes absorbs a portion of vertical overdrive after contacting their corresponding electrical structures. The probe card absorbs any remaining vertical overdrive. The vertical overdrive is a continuing vertical movement of the plurality of probes after a first probe of the plurality of probes mechanically contacts a first corresponding electrical structure.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: March 21, 2017
    Assignee: ADVANTEST CORPORATION
    Inventors: Ting Hu, Lakshmikanth Namburi
  • Patent number: 9599666
    Abstract: A method and apparatus for mapping an electronic device. The electronic device is loaded into a test fixture, which may be an automated test equipment (ATE). A laser beam is stepped across locations of interest. At each location of interest a minimum voltage and/or maximum frequency are computed. A contour map of the changes in minimum voltage and maximum frequency across a field of view of the electronic device is generated. Additional embodiments provide signaling a laser scan module during the rising edge of a synchronization pulse to indicate that minimum voltage (Vmin) and maximum frequency (Fmax) specification search data is provided to a laser voltage probe. A Vmin/Fmax module compares the specification search data with the data read from the laser voltage probe and computes a parameter shift value. The laser beam is moved to another location when the falling edge of the synchronization pulse occurs.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: March 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Lavakumar Ranganathan, Martin Villafana, Lesly Zaren Venturina Endrinal
  • Patent number: 9599667
    Abstract: The various technologies presented herein relate to utilizing visible light in conjunction with a thinned structure to enable characterization of operation of one or more features included in an integrated circuit (IC). Short wavelength illumination (e.g., visible light) is applied to thinned samples (e.g., ultra-thinned samples) to achieve a spatial resolution for laser voltage probing (LVP) analysis to be performed on smaller technology node silicon-on-insulator (SOI) and bulk devices. Thinning of a semiconductor material included in the IC (e.g., backside material) can be controlled such that the thinned semiconductor material has sufficient thickness to enable operation of one or more features comprising the IC during LVP investigation.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: March 21, 2017
    Assignee: Sandia Corporation
    Inventors: Joshua Beutler, John Joseph Clement, Mary A. Miller, Jeffrey Stevens, Edward I. Cole, Jr.
  • Patent number: 9599668
    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: March 21, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9599669
    Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: March 21, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9599670
    Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) path delay test circuit and at least a portion of a critical path in one of its layers. The test circuit includes a plurality of inputs, outputs, a flip-flop coupled to the at least a portion of the critical path and a multiplexer coupled to the flip-flop and to a second layer of the IC. The test circuit further includes a control element such that path delay testing of the IC may be conducted on a layer-by-layer basis.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd
    Inventor: Sandeep Kumar Goel
  • Patent number: 9599671
    Abstract: Exemplary method, computer-accessible medium, test architecture, and system can be provided for a partial-scan test of at least one integrated circuit. For example, it is possible to obtain a plurality of test cubes using a first combinational automatic test pattern generation (ATPG) and identify at least one flip-flop of the integrated circuit using the test cubes to convert to a non-scan flip-flop and facilitate the partial-scan test to utilize the cubes without a utilization of a sequential ATPG or a second combinational ATPG.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 21, 2017
    Assignee: New York University
    Inventor: Ozgur Sinanoglu
  • Patent number: 9599672
    Abstract: An integrated circuit includes a scan chain, a clock divider circuit, and clock selection circuitry. The scan chain includes a plurality of dual edge flip flops, wherein each dual edge flip flop includes a data input, a scan input, a clock input, and data output. The clock divider circuit is coupled to receive a test clock and is configured to divide the test clock to provide a divided test clock. The clock selection circuitry has a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock inputs of the scan chain based on the scan enable signal.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 21, 2017
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Anurag Jindal, Nishant Madan, Mayank Tutwani
  • Patent number: 9599673
    Abstract: An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: March 21, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Anurag Jindal, Nipun Mahajan
  • Patent number: 9599674
    Abstract: A switch failure detector, configured to be installed in an electric system including an electric storage device, includes at least one electronic switch connected in a path in which a charging current to the electric storage device and a discharging current from the electric storage device flow, at least one rectifier for passing a discharging current by bypassing the electronic switch when the electronic switch is turned off, and a controller for sending an on-command signal to the at least one electronic switch to turn on the electronic switch, and determining whether a switch failure detection process is executable based on a voltage of the electric storage device.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 21, 2017
    Assignee: GS YUASA INTERNATIONAL LTD.
    Inventors: Takeyuki Shiraishi, Takeshi Itagaki
  • Patent number: 9599675
    Abstract: An apparatus for controlling a battery pack and an energy storage system including the apparatus are disclosed. In one embodiment, the battery pack includes at least one battery tray each including one or more battery cells. The apparatus may include an open circuit voltage (OCV) calculator and a state of charge (SOC) estimator. The OCV calculator may receive OCV measurement values of the battery cells of each battery tray when the power of the battery pack is turned on, and calculate a final OCV of the battery cells based at least in part on the OCV measurement values. The SOC estimator may extract an SOC value corresponding to the final OCV from an SOC table and estimate the extracted SOC value as an initial SOC.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: March 21, 2017
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Han-Seok Yun, Jong-Woon Yang
  • Patent number: 9599676
    Abstract: Switches change the resistance value of a charge/discharge circuit in a period from starting a discharging at an upper limit voltage until the voltage reaches a lower limit voltage. An electric charge estimator computes electric charge by time-integrating current from a start of the discharging to an arbitrarily determined time, and computes a relationship between electric charge and voltage of a power storage device. An internal resistance estimator computes internal resistance based on voltages and currents of the storage device at times when resistance values are different. An electric energy estimator computes a relationship between electric charge and open voltage based on electric charge, voltage, current and internal resistance of the storage device. During charging or discharging of the storage device, the electric energy estimator estimates the electric energy of the power storage device based on the electric charge, the open voltage, the internal resistance, and the charge/discharge current.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 21, 2017
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuruki Okada, Sho Shiraga, Toshihiro Wada, Shoji Yoshioka
  • Patent number: 9599677
    Abstract: Provided is an efficient method for determining the completion of discharging waste batteries, the method being capable of accurately identifying the discharging states of the charge remaining in the waste batteries and appropriately determining the completion of discharging without measuring the residual voltage of each of the waste batteries. The method for determining the completion of discharging waste batteries according to the present invention is characterized in that after immersing the waste batteries in a conductive liquid, the concentration of hydrogen gas produced from the liquid is measured, thereby determining the completion of discharging the charge remaining in the waste batteries.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: March 21, 2017
    Assignee: SUMITOMO METAL MINING CO., LTD.
    Inventors: Kazunari Maeba, Ryozo Ushio
  • Patent number: 9599678
    Abstract: A testing circuit for backlight source is provided. The testing circuit includes: a power module; a first ON/OFF module; a second ON/OFF module, the power module, the first ON/OFF module and the second ON/OFF module being connected in series; a control module electrically connected to the first ON/OFF module and the second ON/OFF module respectively; and a parallel branch connected in parallel with the second ON/OFF module. The backlight source is connected in the parallel branch, and the control module is configured to control the first ON/OFF module to switched to an ON state from an OFF state when the control module receives a control signal, and to control the second ON/OFF module to be switched to an OFF state from an ON state after a predetermined time delay.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: March 21, 2017
    Assignees: BOE Technology Group Co., Ltd., BOE Optical Science and Technology Co., Ltd.
    Inventors: Zhenghe Gu, Chunlei Cao
  • Patent number: 9599679
    Abstract: A chute assembly (10) to deliver product to a former (11) of a packaging assembly. The chute assembly (10) includes a chute (14) that converges downwardly. Located adjacent the chute (14) is a metal detector (21) having a transmitting and receiving coils (22) of different diameters. The receiving coils (22) being adapted to provide a signal when metal is detected.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: March 21, 2017
    Assignee: TNA Australia Pty Limited
    Inventors: Alfred Alexander Taylor, Darren Ken Alchin
  • Patent number: 9599680
    Abstract: According to one aspect, a portable electronic device sized and shaped to be received within a holster having a magnetic element. The portable electronic device includes an electronic compass adapted to measure a magnetic field of the magnetic element in at least two axes. When the measured pattern corresponds to a first pattern, the portable electronic device is adapted to determine that the portable electronic device is in the holster.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: March 21, 2017
    Assignee: BlackBerry Limited
    Inventors: Michael Joseph Pertuit, Jace William Files, Marc Edward Holbein
  • Patent number: 9599681
    Abstract: The present invention relates to a magnetic sensor and a magnetic detecting method. A first arrangement pattern includes: a first magnetic detection unit (201) including a magnetic sensitivity material (201a) and a magnetic convergence material (201b) having a length different from a length of the magnetic sensitivity unit on a substrate, and being arranged to be parallel to the substrate and arranged horizontally so that a median line (Ma) passing through a midpoint of the magnetic sensitivity material in a longitudinal direction and a median line (Mb) of the magnetic convergence material in the longitudinal direction do not cross with each other; a second magnetic detection unit (202) having the structure same as the structure of the first magnetic detection unit; and a connecting unit electrically connecting the magnetic sensitivity material of the first magnetic detection unit in series with a magnetic sensitivity material of the second magnetic detection unit.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: March 21, 2017
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Hironori Ishii, Hiromi Fujita
  • Patent number: 9599682
    Abstract: Provided is a highly sensitive vertical Hall element without increasing a chip area. In the vertical Hall element, trenches each filled with an insulating film are formed between a first current supply end and voltage output ends, respectively, which enables the restriction of current flow into the voltage output ends to increase the ratio of a current component perpendicular to a substrate surface, resulting in enhanced sensitivity.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: March 21, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Satoshi Suzuki, Mika Ebihara, Takaaki Hioka
  • Patent number: 9599683
    Abstract: A camera assembly for use in a MRI machine. The camera assembly includes a Faraday cage defining a shielded cavity and an optical path mount constructed of a highly stiff, dense, and non-electrically-conductive material in the shielded cavity. The camera imager and lens are mounted to the optical path mount. The camera assembly includes a capacitor-based power regulation circuit. The optical path mount is not subject to eddy currents because it is non-electrically-conductive. The capacitor-based power regulation circuit includes very little ferrous material and is within the shielded cavity, to reduce eddy currents. The resulting camera assembly reduces vibrations and shaking in the magnetic field environment of the MRI machine.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: March 21, 2017
    Assignee: UWM Research Foundation, Inc.
    Inventors: Brian S. R. Armstrong, Todd P. Kusik, Robert T. Barrows
  • Patent number: 9599684
    Abstract: Mounting for a body coil of a magnetic resonance device is provided. A reversible and universal mounting device for a body coil in the magnetic resonance device is provided. The mounting device includes at least one expanding ring for creating a way of retaining the body coil in a tunnel-shaped magnetic opening of the magnetic resonance device. The mounting device also includes at least one expander that is configured to enable the expanding ring to be mounted on the inside of the tunnel-shaped magnetic opening of the magnetic resonance device by spreading. The mounting device includes at least one mounting element for mechanically supporting the body coil on the expanding ring.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: March 21, 2017
    Assignee: Siemens Aktiengesellschaft
    Inventors: Razvan Lazar, Martin Schramm
  • Patent number: 9599685
    Abstract: There is provided a technique for suppressing increase of SAR without sacrificing sensitivity in RF coils used in MRI apparatuses. The present invention provides an antenna device comprising a sheet-shaped conductor and a ribbon-shaped conductor disposed on the subject side with respect to the sheet-shaped conductor with a predetermined distance from the sheet-shaped conductor. The ribbon-shaped conductor has a meandering shape, and is adjusted so as to resonate at transmission and reception frequencies, and it is constituted so that distance to the sheet-shaped conductor becomes smaller at both end part thereof along the static magnetic field direction compared with the distance to the sheet-shaped conductor at the center thereof. Moreover, the ribbon-shaped conductor is constituted so as to have a smaller width, as the distance to the sheet-shaped conductor becomes smaller.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: March 21, 2017
    Assignee: HITACHI, LTD.
    Inventors: Hideta Habara, Yoshitaka Bito, Hisaaki Ochi, Yoshihisa Soutome, Masayoshi Dohata, Tetsuhiko Takahashi, Hiroyuki Takeuchi
  • Patent number: 9599686
    Abstract: Systems and methods for coil arrangements in Magnetic Resonance Imaging (MRI) are provided. One coil arrangement includes a magnet bore, a radio-frequency (RF) transmit coil coupled to the magnet bore, and at least one RF receive coil coupled to the magnet bore. The RF receive coil is movable within the magnet bore.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: March 21, 2017
    Assignee: General Electric Company
    Inventors: Victor Taracila, Fraser Robb, Robert Steven Stormont
  • Patent number: 9599687
    Abstract: Active resistive shim coil assemblies may be used in magnetic resonance imaging (MRI) systems to reduce in-homogeneity of the magnetic field in the imaging volume. Disclosed embodiments may be used with continuous systems, gapped cylindrical systems, or vertically gapped systems. Disclosed embodiments may also be used with an open MRI system and can be used with an instrument placed in the gap of the MRI system. An exemplary embodiment of the active resistive shim coil assembly of the present disclosure includes active resistive shim coils each operable to be energized by separate currents through a plurality of power channels. In some embodiments, the disclosed active resistive shim coil assemblies allow for various degrees of freedom to shim out field in-homogeneity.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: March 21, 2017
    Assignee: ViewRay Technologies, Inc.
    Inventors: Shmaryu M. Shvartsman, James F. Dempsey
  • Patent number: 9599688
    Abstract: NMR relaxation time estimation methods and corresponding apparatus generate two or more alternating current transmit pulses with arbitrary amplitudes, time delays, and relative phases; apply a surface NMR acquisition scheme in which initial preparatory pulses, the properties of which may be fixed across a set of multiple acquisition sequence, are transmitted at the start of each acquisition sequence and are followed by one or more depth sensitive pulses, the pulse moments of which are varied across the set of multiple acquisition sequences; and apply processing techniques in which recorded NMR response data are used to estimate NMR properties and the relaxation times T1 and T2* as a function of position as well as one-dimensional and two-dimension distributions of T1 versus T2* as a function of subsurface position.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: March 21, 2017
    Assignee: VISTA CLARA INC.
    Inventors: Elliot D. Grunewald, David O. Walsh
  • Patent number: 9599689
    Abstract: In a method and apparatus for automatic magnetic resonance imaging of a patient, an MR overall image is composed from several MR partial images. An MR overview image is received by a process that determines several scanning ranges based on the MR overview image. The MR scanning ranges are characterized by a length along a first direction. For all MR scanning ranges: the length along the first direction is set equal to the length of the longest MR scanning range in the first direction.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 21, 2017
    Assignee: Siemens Aktiengesellschaft
    Inventors: Wilhelm Horger, Bernd Kuehn, Andre de Oliveira
  • Patent number: 9599690
    Abstract: In a method for rephasing a first spin system in a first slice with a first coherence curve and a second spin system of a second slice with a second coherence curve, in the generation of MR images with slice multiplexing, a first RF pulse deflects the spin system of the first slice and a second RF pulse deflects the spin system of the second slice. The beginning of the second RF pulse is time-shifted with respect to the beginning of the first RF pulse by a time period that is shorter than the duration of the first RF pulse. A rephasing correction impresses a correction phase on at least one of the spin systems, and signals of the spin systems are respectively detected. The coherence curves are rephased so detection of the signals occurs simultaneously.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 21, 2017
    Assignee: Siemens Aktiengesellschaft
    Inventor: Thorsten Feiweier
  • Patent number: 9599691
    Abstract: In a magnetic resonance apparatus and method for RF excitation with two resonance frequencies to detect the CEST effect, the RF excitation is achieved with the use of a first RF antenna and a second RF antenna of the magnetic resonance apparatus with a first portion of the RF excitation at a first resonance frequency of the two resonance frequencies being implemented with the first RF antenna, and a second portion of the RF excitation at a second resonance frequency of the two resonance frequencies is implemented with the second RF antenna.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: March 21, 2017
    Assignee: Siemens Aktiengesellschaft
    Inventors: Dominik Paul, Benjamin Schmitt
  • Patent number: 9599692
    Abstract: In a method and control sequence determination device for determination of a magnetic resonance system control sequence to generate an image series of a defined image region of an examination subject, the control sequence includes a multichannel pulse train with multiple individual RF pulse trains to be emitted in parallel by the magnetic resonance system via different independent radio-frequency transmission channels. The multichannel pulse train includes an excitation pulse to excite the image region and a subsequent number of refocusing pulses in order to respectively excite an echo signal to acquire raw data for an image of the image series. At least one defined marking region in the image region is determined depending on a subject structure to be depicted in the image region, and the multichannel pulse train is determined such that a saturation is achieved at or in the marking regions before the excitation pulse.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: March 21, 2017
    Assignee: Siemens Aktiengesellschaft
    Inventor: Dieter Ritter
  • Patent number: 9599693
    Abstract: The present invention discloses a magnetic field sensing device that utilizes a single coil for calibrating the response of the sensor to compensate for temperature dependent sensitivity drift and also for resetting the magnetic field sensor in order to eliminate hysteresis. The single coil configuration is advantageous since it reduces the size of the sensor chip by decreasing the number of contact pads on the chip and also because it wastes less space, which permits an increase in the density of the magnetoresistive elements on the sensor chip.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: March 21, 2017
    Assignee: MultiDimension Technology Co., Ltd.
    Inventors: James Geza Deak, Weifeng Shen, Xiaofeng Lei, Songsheng Xue
  • Patent number: 9599694
    Abstract: A method for calibrating a magnetometer following a temperature event is described. The magnetometer includes three sensors, including a Hall Effect sensor associated with a first sensing axis and a sensor of another type associated with a second sensing axis. The method includes: maintaining a cache of gyroscope data and magnetometer data representing magnetometer readings obtained from the magnetometer; detecting a temperature event; determining an expected magnetometer reading following the temperature event; comparing the expected magnetometer reading to a magnetometer reading obtained from the magnetometer after the temperature event to determine a calibration correction amount; compare a difference between the magnetometer reading obtained after the temperature event and the expected magnetometer reading for the second sensing axis to a threshold and, based on the comparison to the threshold, generating new calibration data for the magnetometer based on the calibration correction amount.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: March 21, 2017
    Assignee: BlackBerry Limited
    Inventors: Nazih Almalki, Robert George Oliver
  • Patent number: 9599695
    Abstract: A method for tracking an object includes associating a beacon with a responder; transmitting a polling signal from the beacon to the responder; receiving a response from the responder; entering a low power state on the beacon for a predetermined duration; and transmitting an alert from the beacon responsive to a subsequent signal from the beacon failing to result in receiving a subsequent response from the responder. Embodiments also include a system in which the beacon and responder are configured to perform the described functions. In various embodiments, the duration during which the beacon remains in the low power state is predetermined based either on a default factory setting or a user adjustable setting.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: March 21, 2017
    Assignee: Maxwell Forest PTY LTD
    Inventors: Matthew Emmett Cooke, Anthony Mark Schofield
  • Patent number: 9599696
    Abstract: A device, method and system are provide which permits the methodology used to make the position determination to change dynamically in connection with achieving a position fix of a desired accuracy.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: March 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Sanjeev Khushu
  • Patent number: 9599697
    Abstract: A system for detecting and tracking one or more of direction, orientation and position of one or more light sources includes one or more optical fiber sensors configured to receive light from the one or more light sources and to generate a plurality of cones of light according to relative positions of the one or more optical fiber sensors relative to the one or more light sources. The system includes light data processing circuitry configured to detect characteristics of the plurality of cones of light and to determine one or more of direction, orientation, or position of the one or more light sources relative to the one or more optical fibers.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: March 21, 2017
    Assignee: The Johns Hopkins University
    Inventor: Leo R. Gauthier, Jr.
  • Patent number: 9599698
    Abstract: The disclosure generally relates to an enhanced positioning system and method using a combination or hybrid filter. In one embodiment, Time-Of-Flight (ToF) measurements are used to determine an approximate location for a mobile device in relationship to one or more Access Points. The ToF combined with known and unknown variables are then processed through a hybrid filter system to determine location of the mobile device. The hybrid filter system may include a Kalman Filter (KF) for processing linear models and generally Gaussian noise distribution. The KF assumes that the state probability of mobile device location is Gaussian. Such variables include, for example, WiFi ToF bias. The hybrid filter system may include a Bayesian Filter (BF) for processing variables having non-Gaussian noise distribution and non-linear models. Such variables include, for example, the coordinates of the mobile device. A probability determination from each of the KF and BF is then applied to estimate the mobile device location.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Yuval Amizur, Uri Schatzberg
  • Patent number: 9599699
    Abstract: An RSSI positioning method based on frequency-hopping spread spectrum technology, comprising: calibration stage: measuring the RSSI values of a plurality of channels at fixed points, and recording and calculating the ranging parameters in an RSSI ranging model; system preparation: deploying a positioning anchor node, and realizing synchronization between a target node and the anchor node; conducting communication on the target node by respectively utilizing a plurality of channels to obtain the RSSI values; signal processing stage: processing the RSSI into signal strength amplitude and performing optimization; and positioning stage: calculating a distance and the target node position on a positioning server according to each of the signal strength.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: March 21, 2017
    Assignee: SHENYANG INSTITUTE OF AUTOMATION OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Peng Zeng, Jinchao Xiao, Jie He, Haibin Yu
  • Patent number: 9599700
    Abstract: In FIG. 2 (A), a reception beam (102) is formed using a weighting function (112). A position of a peak of the weighting function (112) is set at the position of the reception beam (102). A reception beam (104) is formed using a weighting function (114), and a position of a peak of the weighting function (114) is set at the position of the reception beam (104). A reception beam (106) is formed using a weighting function (116) and a position of a peak of the weighting function (116) is set at a position of the reception beam (106). In this manner, the positions of the peaks of the weighting functions (112, 114, 116) are shifted in the receive aperture, to follow movements of the reception beams (102, 104, 106) caused by electrical scanning.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: March 21, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Jing-Wen Tsao, Masanori Hisatsu
  • Patent number: 9599701
    Abstract: A device for deflecting acoustic waves for an object in a liquid environment includes an electrical power source located in the object. A heating grid is positioned about the object in the liquid environment, and a cooling grid is also positioned about the object in the liquid environment such that the heating grid is located between the object and the cooling grid. A least one Peltier device is joined to the electrical power source and the cooling grid for providing cooling. Resistance heating or the Peltier device can be joined to the heating grid for providing heating.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: March 21, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Anthony A Ruffa, John F Griffin
  • Patent number: 9599702
    Abstract: A radar sensing system for a vehicle includes a transmitter, a receiver, a memory, and a processor. The transmitter transmits a radio signal and the receiver receives a reflected radio signal. The processor samples reflected radio signals during a plurality of time slices. The processor produces samples by correlating reflected radio signals to time-delayed replicas of transmitted radio signals. The processor accumulates the time slices into a first radar data cube and stores the first radar data cube in a memory. The processor combines a portion of the first radar data cube with a portion of a previously stored radar data cube. Based at least in part on the combined portions of the radar data cubes, the processor processes a time series that is a time series of the first radar data cube concatenated with a time series from the previously stored radar data cube.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: March 21, 2017
    Assignee: UHNDER, INC.
    Inventors: Jean P. Bordes, Raghunath K. Rao, Monier Maher
  • Patent number: 9599703
    Abstract: Methods for determining a range rate of a backscatter transponder and readers implementing the methods are described. The reader transmits a continuous wave signal and receives a modulated reflected response signal from the transponder, mixes the modulated reflected response signal with the carrier frequency to produce a downconverted signal, bandpass filters the downconverted signal to pass a bandpass filtered signal containing at least the modulation frequency, applies a non-linear amplitude transfer function to produce a modulation-suppressed signal, and measures the frequency of the modulation-suppressed signal and determines the range rate from the measured frequency.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 21, 2017
    Assignee: Kapsch TrafficCom AG
    Inventors: Lila Vinski, Japjeev Kohli, Alastair Malarky
  • Patent number: 9599704
    Abstract: An all-solid-state marine radar technology based on a non-rotating cylindrical array antenna is described. Multiple transmit and receive modules are used to form the antenna beam, which allows the beam sequencing, the dwell time in each beam position, the resolution, and the beam shape to be varied in order to make best use of the available energy. Waveforms with a high duty ratio can be used on transmit in order to make efficient use of solid-state power amplifiers. High resolution in both range and Doppler provides high measurement accuracy and superior performance in clutter. Alternate embodiments, including continuous waveform embodiments are disclosed.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: March 21, 2017
    Assignee: MARK Resources, Inc.
    Inventor: Richard L. Mitchell