Abstract: Method embodiments are provided herein for dynamically calibrating and adjusting a direct conversion receiver system. One embodiment includes applying one or more gain control signals to one or more gain elements of a receiver system, where the applying one or more gain control signals results in a gain change to the receiver system; in response to the gain change, determining whether the receiver system exhibits a DC (direct conversion) offset; and in response to a determination that the receiver system exhibits the DC offset, applying one or more DC offset correction control signals to one or more gain elements of the receiver system, where the one or more DC offset correction signals are configured to correct the DC offset.

Abstract: A system and method applying Dynamic Range Control/Compression (DRC) to an audio signal. The dynamic range controller presented here differs from conventional DRC techniques by providing a much larger look-ahead time. In particular, the system and method takes advantage of the look-ahead by analyzing macroscopic loudness changes in the order of seconds as opposed to the microscopic changes most conventional DRCs are designed to control. This approach avoids most of the typical DRC distortions associated with conventional DRC techniques and preserves the micro-dynamics of the audio signal. Gain changes are applied at a rate comparable with manual volume adjustments by mixing and mastering engineers to balance a mix. Ideally, the DRC will approach what a professional sound engineer would do to reduce the dynamic range if there were only a volume control to accomplish the task on the final mix.

Abstract: A method of forming an acoustic resonator includes forming a seed layer on a first electrode layer, forming a piezoelectric layer directly on a surface of the seed layer, and forming a second electrode layer on the piezoelectric layer. The piezoelectric layer includes multiple crystals of piezoelectric material, and the seed layer causes crystal axis orientations of the crystals to be substantially perpendicular to the surface of the seed layer.

Abstract: Cable assembly includes a communication cable having first and second insulated wires. Each of the first and second insulated wires has a signal conductor and an insulation layer that surrounds the signal conductor. The cable assembly also includes a circuit carrier that is coupled to the communication cable and has first and second signal pathways. Each of the first and second signal pathways includes a leading conductive surface and a trailing conductive surface that are separated from each other. The signal conductors of the first and second insulated wires are coupled to the trailing conductive surfaces of the first and second signal pathways, respectively. Each of the first and second signal pathways includes a corresponding signal-control component that electrically couples the separated leading and trailing conductive surfaces.

Abstract: The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

Abstract: An acoustic resonator structure comprises: a substrate having a cavity, which has a plurality of sides; a first electrode disposed over the cavity; a piezoelectric layer disposed over a portion of the first electrode and extending over at least one of the sides; and a second electrode disposed over the piezoelectric layer, an overlap of the first electrode, the piezoelectric layer and the second electrode forming an active area of the FBAR. The active area of the FBAR is completely suspended over the cavity.

Abstract: A filter device with a ladder circuit configuration includes series arm resonators and parallel arm resonators, a filter component mounted on a mounting substrate and including a chip substrate and an elastic wave filter chip, a circuit configuration in which a plurality of series arm resonators and parallel arm resonators are defined by the elastic wave filter chip, and inductances are connected between ground-potential-side end portions of the plurality of parallel arm resonators and a ground potential, and in which at least one of the plurality of inductances is provided in the chip substrate and a remaining at least one inductance is provided in the mounting substrate.

Abstract: A bulk acoustic wave (BAW) resonator includes a bottom electrode disposed on a substrate, a piezoelectric layer disposed over the bottom electrode, and a top electrode disposed over the piezoelectric layer. The BAW resonator further includes at least one air-gap and corresponding support structure, where the at least one air-gap separates at least one of the bottom electrode and the top electrode from the piezoelectric layer, respectively.

Abstract: A narrow-band acoustic filter comprises an input and an output, and at least one acoustic resonator pair coupled between the input and the output. Each of the acoustic resonator pair(s) comprises at least one in-line acoustic resonator and in-shunt acoustic resonator that operate together to create a nominal passband. The acoustic filter further comprises at least one capacitive element in parallel with one of the in-line acoustic resonator and the in-shunt acoustic resonator of each of the acoustic resonator pair(s), thereby sharpening one of a lower edge and an upper edge of the nominal passband.

Abstract: An acoustic wave device includes a first longitudinally-coupled acoustic wave filter having interdigital transducer (“IDT”) electrodes arranged in a propagation direction of acoustic wave, and a second longitudinally-coupled acoustic wave filter having IDT electrodes arranged in a propagation direction of acoustic wave. In the IDT electrodes of the first longitudinally-coupled acoustic wave filter, a comb-shaped electrode connected to an input port and another comb-shaped electrode connected to an output port are disposed in an in-phase relation. In the IDT electrodes of the second longitudinally-coupled acoustic wave filter, a comb-shaped electrode connected to an input port and another comb-shaped electrode connected to an output port are disposed in an anti-phase relation. This acoustic wave device has an excellent attenuation characteristic while maintaining a preferable insertion loss.

Abstract: The present invention relates to a digital interpolator, comprising an input to receive an input signal at a first clock frequency and comprising an output to provide an interpolated signal at a second clock frequency larger than the first clock frequency. The interpolator comprises a differentiator connected to the input, an interpolator stage connected to a differentiator output, and an integrator connected to the output and connected to an output of the interpolator stage.

Abstract: The implementation of non-integer sample rate conversion and filtering of data sequences may be improved by performing both operations together with a system that includes a CIC filter and a control block that modifies internal states of the CIC filter. In one embodiment, input data samples provided at a first sample rate may be filtered by a CIC filter that includes a cascade of an integrating stage and a comb filter stage, each stage operating at a different sampling rate. A control block coupled to the CIC filter may modify at least one internal state of at least one of the integrating stage and comb filter stage of the CIC filter, wherein filtering by the CIC filter and modifying the at least one internal state causes the CIC filter to output data samples at a second sample rate unequal to the first sample rate.

Abstract: An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.

Abstract: Apparatus and methods are disclosed related to tuning a resonant frequency of an LC circuit. In some implementations, the LC circuit can be embodied in a low noise amplifier (LNA) of a receiver. The receiver can include a component configured to generate an indicator of received signal strength indication (RSSI) of a radio frequency (RF) signal received by the receiver. A control block can adjust the resonant frequency of the LC circuit based at least in part on the indicator of RSSI. As another example, the receiver can include an oscillator, such as a VCO, separate from the LC circuit that can be used to tune the resonant frequency of the LC circuit. These apparatus can compensate for variation in a zero imaginary component of an impedance across the LC circuit.

Abstract: Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal produced by a first ring oscillator that includes a first interconnect provided in a first interconnect layer of an IC, selecting a first mode of operation for a second ring oscillator circuit that includes a second interconnect disposed in alignment with the first interconnect, selecting a second mode of operation for the second ring oscillator circuit, and determining one or more characteristics of the first interconnect based on a difference in frequency of the first oscillating signal produced when the second ring oscillator circuit is operated in the first mode and frequency of the first oscillating signal when the second ring oscillator circuit is operated in the second mode.

Abstract: A sampling circuit includes a first latch, a second latch and a signal transition detector. The first latch is disposed on an upstream side of a logic circuit. The second latch is disposed on a downstream side of the logic circuit. The first latch and the second latch respectively switch to opposite states of an opaque state or a transparent state according to trigger signals generated by a reference clock and a control clock. The signal transition detector is configured for detecting whether the signal outputted by the logic circuit is in error or not and outputting a corresponding control clock. The above-mentioned sampling circuit can delay switching the second latch to the opaque state and switching the first latch to the transparent state to correct sampling when a timing error occurs.

Abstract: This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

Abstract: A method and apparatus for measuring a voltage are disclosed. In an embodiment a method for controlling a supply voltage includes providing a first periodic signal by providing a reference voltage to an oscillator, providing a second periodic signal by providing the supply voltage (VOUT) of a voltage source to the oscillator, providing a first count by measuring first periods of the first periodic signal, providing a second count by measuring second periods of the second periodic signal and comparing the first count with the second count.

Abstract: A slope control circuit is connected between a replica circuit and a controller area network bus. The replica circuit generates an upper and a lower feedback signal. The slope control circuit receives and is driven by the feedback signals for controlling a voltage slope of a high-level output and a low-level output. The slope control circuit comprises an upper and a lower driving circuit, individually connected between the replica circuit, the high-level output and the low-level output. The upper driving circuit and the lower driving circuit respectively include at least one charging and discharging circuit. By controlling the charging and discharging circuit, the present invention controls decreasing voltage slope of the high-level output to be symmetric to increasing voltage slope of the low-level output, and delay time of the circuit switching between different operating modes to be equivalent.

Abstract: Representative implementations of devices and techniques provide a speed increase to a comparator circuit. An active clamp device may be positioned between an input stage and an output stage of the comparator, limiting the voltage range of the output of the first stage.

Abstract: A power module includes: a base plane; at least one switch chip assembled on the base plane; and a voltage clamping circuit for clamping a voltage spike occurring on the at least one switch chip, comprising components of a charging loop, wherein the components of the charging loop at least comprise a capacitor, wherein a projection of a center point of at least one of the components of the charging loop on the base plane is located within at least one first circle, defined with a center of the first circle being a center point of the at least one switch chip, and with a radius of the first circle being a product of a maximum one of a length and a width of the at least one switch chip and a first coefficient, which is a multiple of 0.5.

Abstract: A semiconductor device includes a transistor, a diode, a sense transistor, a sense diode, a resistor, and a clamp circuit. The diode is connected in inverse parallel to the transistor. The resistor is connected at one end of the resister to an emitter of the sense transistor and an anode of the sense diode, and is connected at the other end of the resister to an emitter of the transistor and an anode of the diode. The clamp circuit is configured to clamp a voltage that is generated in the resistor when a sense diode current flows. A ratio of a sense diode current to a current flowing to the diode is larger than a ratio of a sense current to a current flowing to the transistor.

Abstract: A circuit for controlling a clock signal may include a voltage source that provides a bias voltage, and at least one delay element having a non-linear capacitive load coupled to an output of the delay element. The non-linear capacitive load receives the bias from the voltage source and controls a delay magnitude applied to a plurality of pulses of the clock signal by the delay element. Based on the bias having a first scaled voltage, the delay magnitude that is applied to the plurality of clock pulses is increased in order to generate a frequency correction to the operating frequency of a microprocessor based on a variation to a microprocessor supply voltage. Based on the bias having a second scaled voltage, the delay magnitude that is applied to the clock pulses is maintained to retain the operating frequency of the clock during the variation to the supply voltage.

Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.

Abstract: Provided is a time amplifier. The time amplifier includes: an SR latch providing an output at a timing determined according to a time difference between two inputs; and an operation determination unit connected to a power terminal of the SR latch and configured to determine an operation of the SR latch.

Abstract: This disclosure generally provides a system, active input device, and method for generating an amplified square wave signal based on an input signal. The method comprises generating a pulse signal based on the input signal, and driving a switching signal based on the pulse signal to control a first switch. A pulse width of the pulse signal is adaptively controlled using a control signal generated based on the amplified square wave signal. An output terminal of the first switch is coupled with a second switch, and the switching signal controls current entering into the second switch. The method further comprises driving the input signal to control a third switch coupled with the second switch. The amplified square wave signal is generated at the second output terminal based on the switching signal and on the input signal.

Abstract: A comparator circuit includes a differential circuit unit which detects a difference between two input signals, a current supply unit which supplies a current to the differential circuit unit, and a control unit which detects an operation timing of the differential circuit unit and controls the current supplied to the differential circuit unit by the current supply unit according to a detection result thereof.

Abstract: A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a voltage control circuit coupled to at least one of the first transistor or the second transistor. The voltage control circuit is configured to change a voltage level of at least one of the first transistor or the second transistor to allow voltage domain transition of an output signal in view of a change in state of an input signal without ramping a supply signal of the biasing circuit.

Abstract: A circuit includes a first node having a first supply voltage, a second node having a second supply voltage, and a voltage detector coupled between the first node and the second node, the voltage detector including a first output node. A clamp circuit is coupled between the first node and the second node. The voltage detector is configured to drive the first output node to the first supply voltage in response to a difference between the first supply voltage and the second supply voltage exceeding a predetermined threshold voltage value. The clamp circuit is configured to establish a conduction path between the first node and the second node in response to the first or second output node being driven to the first supply voltage.

Abstract: The present disclosure provides a short circuit protection circuit with small area and less current-consuming. A short circuit protection circuit 14 includes a transistor M11 and a resistor R11, serially connected between a source and a drain of an output transistor 11 (transistor M10); and a transistor M12, connected between the source and a gate of the output transistor 11 and forming a current mirror together with the transistor M11.

Abstract: A temperature detection circuit for detecting a temperature of a switching element, a current source for causing a forward current to flow to the temperature detection circuit, an amplifier circuit for amplifying a forward voltage of the temperature detection circuit, a current adjustment circuit for adjusting a magnitude of a gate current to the switching element on the basis of an output voltage of the amplifier circuit, and a drive circuit for receiving an external signal and turning ON/OFF the switching element, are included. The magnitude of the gate current caused to flow from the current adjustment circuit to the gate electrode of the switching element is adjusted on the basis of a change in a magnitude of the forward voltage corresponding to a change in the temperature of the temperature detection circuit.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: The present invention relates to a control system and control method for controlling a switching device (1) integrated in an electronic converter, the object of which is to extend the working voltage range of the switching devices and thus increase the power of the electronic DC/AC converter which prepares the energy produced by a energy generating system and injects it into the electrical grid. It basically comprises a voltage source (3), a capacitance (7), a first gate resistor (21) and a second gate resistor (22), a first circuit formed by a series resistor (6) with a first diode (5), a second circuit formed by a second diode (4) and a connecting element (8) controlled by a control unit (12) that controls the opening and closing thereof. Another object of the present invention is a switching cell for an electronic converter comprising said control system.

Abstract: Disclosed are a power on reset circuit, a power on reset method and an electric device using the same. In the power on reset circuit and method, a first voltage detecting circuit and a second voltage detecting circuit detect the voltage of a power supply and output a first voltage signal and a second voltage signal respectively. A logic circuit receives the first voltage signal and the second voltage signal to turn no or off the first voltage detecting circuit for detecting the voltage of the power supply. Specifically, merely when the voltage value of the power supply is less than a rising threshold voltage value of the first voltage detecting circuit or a falling threshold voltage value of the second voltage detecting circuit, the first voltage detecting circuit is turned on to detect the voltage value of the power supply.

Abstract: A driver circuit for turning ON and OFF one of two parallel-connected insulated-gate semiconductor elements includes a voltage control circuit that controls a level of a power supply voltage in response to a detected element temperature of the one semiconductor element, a constant current supply section, responsive to a drive signal, for supplying a constant current to a gate of the one semiconductor element to turn the one semiconductor element ON, the power supply voltage being supplied to the constant current supply section from the voltage control circuit, and a discharge circuit, responsive to the drive signal, for discharging an electric charge accumulated in the gate to turn the one semiconductor element OFF.

Abstract: Systems and methods relating to voltage monitoring across isolation barriers are disclosed herein. In one example embodiment, an isolation system includes a low voltage circuit portion including a first control logic portion, and a high voltage circuit portion including a second control logic portion and an analog-to-digital converter portion. The system further includes a first transistor device having a first terminal coupled at least indirectly to a first connection having a first voltage level and a second terminal coupled at least indirectly to a second connection having a second voltage level. The first control logic portion governs provision of an output signal generated based at least indirectly upon the second voltage level. Due to a galvanic barrier, the output signal can be provided for receipt by another device in a manner that avoids exposure of that device to an undesirably high current or power level.

Abstract: An apparatus for performing signal driving with aid of MOSFET and an associated IC are provided, where the apparatus includes a PMOSFET coupled between a predetermined voltage level and a terminal, and further includes an NMOSFET coupled between the predetermined voltage level and the terminal. The PMOSFET is arranged for selectively driving a signal that passes through the terminal. In addition, the NMOSFET is arranged for selectively driving the signal. Additionally, the apparatus further includes another NMOSFET coupled between another predetermined voltage level and the terminal, wherein the other NMOSFET is arranged for selectively driving the signal. More particularly, the PMOSFET, the NMOSFET, and the other NMOSFET does not drive the signal at the same time. For example, each of the PMOSFET, the NMOSFET, and the other NMOSFET selectively drives the signal to have one of a plurality of logical states.

Abstract: According to one embodiment, a semiconductor device includes: a voltage line to which a first voltage is applied; a first circuit configured to operate by using the first voltage; and a second circuit configured to control a connection between the voltage line and the first circuit. The second circuit includes: at least one first switch circuit configured to connect the first circuit and the voltage line based on a first control signal; and a second switch circuit including a plurality of switch sections configured to connect the first circuit and the voltage line based on a plurality of second control signals different from the first control signal.

Abstract: An integrated circuit with precision current source includes a first MOSFET, a second MOSFET, an op-amp and a resistor formed on a common semiconductor substrate. The first MOSFET is characterized by a first multiplier (×M1) and the second MOSFET is characterized by a second multiplier (×M2) where a ratio of ×M2 to ×M1 is greater than one. An inverting input of the op-amp is coupled to a drain of the first MOSFET and an output of the op-amp is coupled to a gate of the first MOSFET. A negative feedback circuit limits a rise in output current under low output voltage conditions.

Abstract: A method of controlling electrical power delivery to a well tool can include transmitting trigger light via an optical waveguide to a circuit in a well, and the circuit delivering the electrical power to the well tool in response to the circuit receiving the trigger light. A circuit for supplying electrical power to at least one well tool can include a photodiode which receives light from an optical waveguide in a well, a voltage increaser which increases a voltage output by the photodiode, and an electrical energy storage device which receives electrical energy via the voltage increaser, whereby the electrical power can be supplied to the downhole well tool from the storage device.

Abstract: The present invention provides a capacitive touch panel and a manufacturing method thereof, wherein the capacitive touch panel includes a first transparent substrate in which an upper transparent electrode and an upper metal interconnect electrode are formed on the lower side thereof; a transparent adhesive portion; and a second transparent substrate in which a lower transparent electrode and a lower metal interconnect electrode are formed on the upper side thereof. More specifically, the invention provides a capacitive touch panel with excellent visibility since an expensive ITO transparent electrode is replaced with conductive materials such as CNT and graphene and the touch panel has an electrode pattern of a specific structure.

Abstract: In the present invention, a capacitance-type switch is provided with an operation plate and an electrode plate. The operation plate forms operation surfaces operated by the touch of a fingertip F (operation body) of a user. The electrode plate is disposed on the side of the operation plate opposite the operation surfaces. Furthermore, the capacitance-type switch is turned on and off in response to the change in capacitance caused between the fingertip F and the electrode plate. In addition, a high-permittivity material is disposed in an outer circumferential section of the electrode plate, the high-permittivity material having a higher permittivity than the operation plate. It is possible to improve the sensitivity of the capacitance-type switch while minimizing malfunctioning.

Abstract: Devices and methods for operating devices are provided, such as those that include a memory device having a reference voltage (Vref) circuit that has substantially similar paths and impedances as an on-die termination (ODT) circuit. One such Vref circuit tracks supply variations and temperature changes in a manner substantially similar to the ODT circuit. In some embodiments an update scheme is provide for the ODT circuit and the Vref circuit to enable simultaneous update of each circuit through the same digital codes.

Abstract: A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.

Abstract: A resistance calibration method for a first resistor of a first module includes performing resistance calibration on a calibration unit of a second module, wherein the first module is connected to the second module via a pad coupled to the first resistor and the calibration unit is coupled to the pad; obtaining a resistance value of the calibration unit after the resistance calibration; and calibrating a resistance value of the first resistor according to the resistance value of the calibration unit.

Abstract: An interface circuit includes a pre-driver that converts the single-ended signal to an intermediate differential signal having a first voltage swing responsive to a first supply voltage supplied to the pre-driver. An output driver is coupled to receive the intermediate differential signal from the pre-driver to convert the intermediate differential signal to an output differential signal coupled to be received by a load coupled to the output driver. The output differential signal has a second voltage swing responsive to a second supply voltage supplied to the output driver. An internal regulator is coupled to receive a variable supply voltage to supply the second voltage to the output driver. The second supply voltage is generated in response to a bias signal. A replica bias circuit is coupled to receive the variable supply voltage to generate the bias signal.

Abstract: A physical unclonable function (PUF) located on a supply item for an imaging device is disclosed. The PUF has a toothed rack configured to mate with a gear. During reading operations, the gear turns and translates the PUF linearly under a magnetic sensor. This configuration is inexpensive and robust. Other devices are disclosed.

Abstract: A digital input circuit includes a series connection of a current limiter and a switch having a switch control input coupled between a signal input and ground, and a logic level shifter coupled to the signal input and having a switch control output coupled to the switch control input and a signal output, where a maximum amplitude at the signal input is greater than a maximum amplitude at the signal output. A digital input method includes coupling an input signal to ground with a current limiter by closing an electronic switch, providing an output signal responsive to the input signal, where a maximum amplitude of the input signal is greater than a maximum amplitude of the output signal, by latching the output signal while the input signal is above a threshold voltage and opening the electronic switch after the output signal is latched.

Abstract: Described is an apparatus comprising a first node to receive signal; a second node to provide an output signal; a voltage limiter circuit operating under a first supply voltage, the voltage limiter coupled to the first and the second nodes; and a bypass circuit operating under the first supply voltage, the bypass circuit coupled to the voltage limiter circuit and is capable of being enabled to electrically short the first node to the second node.

Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.