Abstract: A semiconductor device may include a delay line including a first group of unit delay cells and a second group of unit delay cells. The first group of unit delay cells and the second group of unit delay cells may be configured for delaying a phase of a clock by a unit cycle of a reference frequency. The reference frequency may serve as a reference for distinguishing between a first frequency and a second frequency. The semiconductor device may include a reservoir capacitor located adjacent to one or more of the unit delay cells of the first group. Only the first group of the unit delay cells may be used to delay the phase of the clock.

Abstract: A receiving circuit includes: a detector configured to detect a position at which logics of first data and second data acquired by sampling received data using two clocks having mutually-different phases do not match each other as an edge; and an adjustment circuit configured to perform an adjustment causing an internal clock frequency to be close to a data frequency in the received data based on a first probability that logics of third data in a next cycle of the first data and the second data match each other and a second probability that logics of fourth data in a next cycle of the second data and the third data match each other.

Abstract: An all-digital phase-locked loop (AD-PLL) and related methods and computer readable medium are provided. The AD-PLL comprises a reference phase generator for receiving a digital signal and splitting the digital signal into an integer part and a fractional part, an estimator block for estimating a control signal, and a digital-to-time converter for receiving the estimated control signal and a reference clock signal and for deriving a delayed reference clock signal. The AD-PLL also includes a time-to-digital converter for receiving the delayed reference clock signal and a desired clock signal phase, and for deriving a fractional phase error. The estimator block receives the fractional phase error and determines the estimated control signal by correlating the fractional phase error with the fractional part, yielding a correlated signal, multiplying the correlated signal with its absolute value, and integrating the outcome of the multiplying to obtain the estimated control signal.

Abstract: A delay lock loop including a selection unit, a delay unit, and a phase detection unit is provided. The selection unit receives a non-inverted clock signal and an inverted clock signal and generates a first clock signal and a second clock signal according to an indication signal. The delay unit is coupled to the selection unit. The delay unit includes a delay factor and delays the first clock signal to generate a third clock signal according to the delay factor. The phase detection unit is coupled to the delay unit and the selection unit and generates the indication signal according to a phase difference between the second and third clock signals. The delay unit adjusts the delay factor according to the indication signal.

Abstract: A delay lock loop is provided. A delay unit delays a first clock signal to generate a second clock signal according to the delay factor. An elimination unit delays a third clock signal to generate a fourth clock signal. A phase detection unit generates an indication signal according to a phase difference between the second and fourth clock signals. When a duration of the indication signal being at a first level does not arrive at a pre-determined value and the indication signal is at a second level, the control unit increases the delay factor. When the duration of the indication signal being at the first level arrives at the pre-determined value and the indication signal is at the second level, the control unit reduces the delay factor.

Abstract: An example phase-locked loop (PLL) circuit includes a voltage controlled oscillator (VCO) configured to generate an output clock based on an oscillator control voltage, a sub-sampling phase detector configured to receive a reference clock and the output clock, and a phase frequency detector configured to receive the reference clock and a feedback clock. The PLL circuit includes a charge pump configured to generate a charge pump current, a multiplexer circuit configured to select either output of the sub-sampling phase detector or output of the phase frequency detector to control the charge pump, and a lock detector configured to receive the reference clock, the feedback clock, and the output of the phase frequency detector to control the multiplexer. The PLL circuit includes a loop filter configured to filter the charge pump current and generate the oscillator control voltage, and a frequency divider configured to generate the reference clock from the output clock.

Abstract: In one implementation an output signal of an oscillator is varied to be within a desired frequency band with respect to a reference signal, the output signal having a plurality of phases. The implementation may include comparing the output signal with the reference signal, counting falling edges about each phase of the number of phases in a predetermined time period and summing to define a count output; comparing the count output with a product of the number of phases of the output signal and the factor to define a comparison, generating a control signal based upon the comparison, and inputting the control signal to the oscillator to alter the output signal thereof.

Abstract: A PLL circuit having a desired performance is provided. A PLL circuit (100) includes a phase comparator (11) that detects a phase difference; a voltage control oscillator (12) that generates a signal to be returned to the phase comparator (11); and a loop filter (10) that is disposed between the phase comparator (11) and the voltage control oscillator (12) and includes an adder (50) that adds outputs from a proportional path (20), a first integral path (40), and a second integral path (30). The second integral path (30) and the first integral path (40) each include a cumulative adder, a ?? modulator, and an RC filter. The lock detector (36) detects a lock state, controls a gain of the first cumulative adder (42) and a bandwidth of the first RC filter (45), and switches an input to a second ?? modulator (33) to a fixed value.

Abstract: A system and method for calibrating a Voltage-Controlled Oscillator (VCO) having both fine-tuning control and coarse-tuning control. The VCO frequency can vary monotonically with changes in each of one or more operational conditions. The calibration method determines the coarse-tuning control setting for the VCO at system start-up. The method comprises generating frequency characterization data, generating a polynomial function from the characterization data, calculating the fine-tuning control voltage based on the polynomial function and a measurement of the operational conditions, and sweeping through all the coarse-tuning control settings to determine the coarse-tuning control setting that generates the closest VCO frequency to a target frequency when using the calculated fine-tuning control voltage.

Abstract: A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase input signal, unwraps the wrapped-phase input signal to generate an unwrapped-phase signal, and differentiates the unwrapped-phase signal. The wrapped-phase input signal and the differentiated unwrapped-phase signal are both injected into a feedback loop of the modulator circuit. The feedback loop may include a multi-modulus frequency divider with a frequency divisor that is temporarily incremented or decremented to cancel out abrupt phase jumps associated with the wrapped-phase to unwrapped-phase conversion.

Abstract: An analog phase-locked loop (PLL) is disclosed, comprising a voltage controlled oscillator (VCO); a frequency divider having its input connected to an output of the VCO; a first phase detector arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump connected to an output of the first phase detector and arranged to output a charge per detected phase error based on the output of the first phase detector; and an analog loop filter connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO.

Abstract: The present disclosure provides a single-phase PLL controlling method and a single-phase PLL controlling device. The device includes a first FIR filter, a second FIR filter and a Park converter. The first FIR filter and the second FIR filter are configured to perform FIR filtration on a collected power grid voltage signal so as to acquire filtered signals, and output the filtered signals to the Park converter. A filtered signal V? acquired by the first FIR filter and a filtered signal V? acquired by the second FIR filter form a set of virtual two-phase signals in an ?? coordinate system. The Park converter is configured to perform Park conversion on the filtered signal V? and the filtered signal V?, so as to acquire a set of two-phase signals Vd and Vq in a dq coordinate system.

Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

Abstract: A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels.

Abstract: A device can be used for compensating bandwidth mismatches of time interleaved analog to digital converters. A processor of the device determines, for each original sample stream, an estimated difference between the time constant of a low pass filter representative of the corresponding converter and a reference time constant of a reference low pass filter, and uses this estimated difference and a filtered stream to correct the original stream and deliver a corrected stream of corrected samples.

Abstract: The present invention provides a semiconductor device having a high-speed A/D conversion circuit realizing improvement in noise resistance. A semiconductor device having an A/D conversion circuit includes a sample and hold circuit outputting an analog signal having a value according to a value of an analog signal supplied in a first period, and prediction tables. The prediction tables have reference voltage information designating a reference voltage to be compared with an analog signal output from the sample and hold circuit at a plurality of timings in the first period and bit position information designating a bit position of a digital signal determined by comparison with the reference voltage.

Abstract: An analog-to-digital converter (ADC) system can sample an input voltage for at least a first conversion into a first N1-bit digital value and to use the same input voltage sample for at least a second conversion into a second N2-bit digital value. A difference between a result of the first conversion and a result of the second conversion can be driven toward zero to adjust weights of one or more of the bits to calibrated values for use in one or more subsequent analog-to-digital conversions of subsequent samples of the input voltage. Shuffling, dithering, or the like can help ensure that at least a portion of the decision paths used in the second conversion are different from the decision paths used in the first conversion. Calibration can be performed in the background while the the ADC is converting in a normal mode of operation.

Abstract: Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2n-2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2n-2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.

Abstract: An A/D converter circuit has an amplifier circuit to amplify an input signal and output a first amplification signal and a second amplification signal, the second amplification signal having an amplification error smaller than that in the first amplification signal, a first sampling circuit to sample the first amplification signal, a first A/D converter to perform A/D conversion on the first amplification signal sampled by the first sampling circuit and output a first digital signal, a second sampling circuit to sample the second amplification signal, a D/A converter to perform D/A conversion on the first digital signal and output a first analog signal, a subtracter to subtract the first analog signal from the second amplification signal sampled by the second sampling circuit and output a second analog signal, and a second A/D converter to perform A/D conversion on the second analog signal and output a second digital signal.

Abstract: Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.

Abstract: An A/D conversion circuit includes: first/second pulse circulation circuits delaying an input signal and circulating a pulse signal; a circulation number difference measurement section outputting a difference between circulation time numbers of the pulse signal through the first/second pulse circulation circuits; a conversion control circuit outputting the difference as A/D conversion data when outputting a conversion data output processing signal; and a signal ratio change circuit: outputting, from a first output terminal, a voltage calculated by adding the reference voltage and a voltage obtained by multiplying a differential voltage, obtained by subtracting the reference voltage from the analog input voltage, by a first proportional coefficient; and outputting, from a second output terminal, a voltage calculated by subtracting, from the reference voltage, a voltage obtained by multiplying the differential voltage by a second proportional coefficient.

Abstract: A digital-to-analog converter (DAC) is described. The DAC comprises a resistor having a resistance R and a capacitor having a capacitance C. The DAC comprises a first switching element configured, in response to a first control signal, to couple the capacitor to a first rail via a path having a resistance less than R and a second switching element configured, in response to a second control signal, to couple the capacitor to the first rail through the resistor. The DAC also comprises a third switching element configured, in response to a third control signal, to couple the capacitor to a second rail (8) via a path having a resistance less than R and a fourth switching element configured, in response to a responsive to a fourth control signal, to couple the capacitor to the second through the resistor. The capacitor can be quickly charged or discharged over a period less than RC or less than 0.7 RC.

Abstract: A cellular radio architecture that includes a programmable bandpass sampling radio frequency front-end and an optimized digital baseband. The architecture includes a multiplexer having signal paths that include a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture further includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to analog transmit signals, where the transmitter module includes a power amplifier and a switch for directing the transmit signals to one of the signal paths in the multiplexer.

Abstract: A data processing apparatus has floating-point add circuitry to perform a floating-point addition operation for adding or subtracting two floating-point values. The apparatus also has conversion circuitry to perform a conversion operation to convert a first floating-point value into a second value having a different format. The conversion circuitry is capable of converting to an integer or fixed-point value. The conversion circuitry is physically distinct from the floating-point add circuitry.

Abstract: According to one embodiment of the present invention, a system for compressing data determines a common divisor for a set of values comprising integers. The system divides each value within the set of values by the common divisor to produce reduced values, and represents the set of values in the form of data indicating the common divisor and the reduced values. Embodiments of the present invention further include a method and computer program product for compressing data in substantially the same manners described above.

Abstract: A method of encoding data includes determining a magnitude of change between a first value associated with first data and a second value associated with second data based on a comparison of the first value and the second value. The first value is encoded into a first set of bits having a first number of bits. The method also includes encoding the magnitude of change into a second set of bits utilizing a sign-interspersed two's complement encoding scheme. The second set of bits has a second number of bits that is less than the first number of bits.

Abstract: A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture.

Abstract: A method of decoding a non-binary Low Density Parity Check (LDPC) code is provided. The method includes a plurality of messages to perform hard decision for all messages except for one message, and combines the hard-decided values with the one message that is not hard-decided, to update a final output message.

Abstract: Provided is an error correcting method including: executing, by an error-position detector, a determination process if a received word fails to satisfy a predetermined condition, the received word having a plurality of symbols, the determination process including determining if a determination-target symbol has an error or not, and detecting an error position, the error position being a position of the symbol having an error; changing, by a determination-target changing unit, the position of the determination-target symbol of the received word every time the determination process is executed; detecting, by an undetected-position detector, if the predetermined condition is satisfied, the error position of the symbol, for which the determination process is not executed, based on a relation between the error position and a variable generated from the received word; and correcting, by an error corrector, an error at the error position detected by the error-position detector and the undetected-position detector.

Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.

Abstract: According to one embodiment, a method for processing data includes determining whether a PES is invalid while reading data from a magnetic medium using at least one data channel, determining whether a PES value is above a first predetermined threshold when the PES is valid, injecting error bits into a data stream in place of corresponding bits of decoded data when the PES is invalid and/or the PES value is above the first predetermined threshold, decoding the data using a run-length limited (RLL) decoder to produce the decoded data based on the data from the magnetic medium, and outputting the data stream. Other methods, systems, and tape drives for processing data using error injection are described in more embodiments.

Abstract: An error detection method of a variable-length coding (VLC) code stream includes at least the following steps: decoding a data frame of the VLC code stream; and determining whether the data frame is erroneous according to length information of the data frame and a bit number of decoded data of the data frame. According to the method, the present invention realizes the objective of performing error detection upon data frames during the decoding process.

Abstract: An apparatus for generating base band receive signals includes a first analog-to-digital converter module generating a first digital high frequency receive signal at least by sampling a first analog high frequency receive signal, a first digital signal processing module generating a first base band receive signal based on the first digital high frequency receive signal, a second analog-to-digital converter module generating a second digital high frequency receive signal at least by sampling a second analog high frequency receive signal and a second digital signal processing module generating a second base band receive signal based on the second digital high frequency receive signal. The first analog high frequency receive signal comprises first payload data at a first receive channel associated with a first carrier frequency and the second analog high frequency receive signal comprises second payload data at a second receive channel associated with a second carrier frequency.

Abstract: A transmitter and method are provided for processing a transmission signal. The transmitter includes an FEM that switches a plurality of band signals for a first and second communication scheme, wherein the band signals for the first communication scheme include a first HB signal, a second HB signal, a first LB signal, and a second LB signal, and the band signals for the second communication scheme include a third LB and a third HB signal; a first PAM including a first power amplifier that amplifies the third HB signal, a second power amplifier that amplifies the first HB signal, and a third power amplifier that amplifies the first LB signal; and a second PAM including a fourth power amplifier that amplifies the third LB signal, a fifth power amplifier that amplifies the second HB signal, and a sixth power amplifier that amplifies the second LB signal.

Abstract: Methods and systems for 60 GHz distributed communication are disclosed and may include generating IF signals from baseband signals in a computing device with wireless capability. The IF signals may be communicated to remote RF modules within the computing device via coaxial lines. The IF signals may be up-converted to RF signals and transmitted via the RF modules. The IF signals in the coaxial lines may be tapped via taps coupled to the RF modules. The baseband signals may comprise video data, Internet streamed data, and/or data from a local data source. The RF signals may be communicated to a display device. Control signals for the RF devices may be communicated utilizing the coaxial lines. One or more of the RF devices may be selected based on a direction to a receiving device. The remote RF devices may comprise mixers. The RF signals may comprise 60 GHz signals.

Abstract: Techniques for generating a power tracking supply voltage for a circuit (e.g., a power amplifier) are disclosed. The circuit may process multiple transmit signals being sent simultaneously on multiple carriers at different frequencies. In one exemplary design, an apparatus includes a power tracker and a power supply generator. The power tracker determines a power tracking signal based on inphase (I) and quadrature (Q) components of a plurality of transmit signals being sent simultaneously. The power supply generator generates a power supply voltage based on the power tracking signal. The apparatus may further include a power amplifier (PA) that amplifies a modulated radio frequency (RF) signal based on the power supply voltage and provides an output RF signal.

Abstract: Various digital pre-distortion systems for use in transmitters are disclosed. The digital pre-distortion system comprises an observing path, which performs either undersampling or radio frequency sampling of the output of a power amplifier. Undersampling may be performed at a rate, which causes aliasing to occur in the undersampled frequency domain. Both undersampling and radio frequency sampling reduces the complexity of the digital pre-distortion system by removing any down mixing modules or anti-aliasing modules, while maintaining reasonable performance of the digital pre-distortion systems.

Abstract: An apparatus, system, and method are provided for energy conversion. For example, the apparatus can include a trans-impedance node, a reactive element, and a trans-impedance circuit. The reactive element can be configured to transfer energy to the trans-impedance node. The trans-impedance circuit can be configured to receive one or more control signals and to dynamically adjust an impedance of the trans-impedance node. The trans-impedance node, as a result, can operate as an RF power switching supply based on the one or more control signals.

Abstract: A wireless device including a first receiver and a second receiver. The first receiver is configured to receive a first signal transmitted on a first network using a first communication standard, and generate, in response to a signal strength of the first signal being greater than or equal to a predetermined threshold, first information about the first signal based on a first portion of the first signal. The second receiver is configured to receive a second signal transmitted on a second network using a second communication standard, and suppress interference from the first signal based on the first information about the first signal. The first communication standard is different from the second communication standard. The first receiver and the second receiver are co-located in the wireless device.

Abstract: A very low intermediate frequency (VLIF) receiver and a method of controlling a VLIF receiver. The method comprises estimating energy levels in first and second signals and detecting interference from a first adjacent channel interferer based upon a difference in energy in the first and second signals. The first signal comprising a first on-channel portion and an adjacent channel portion and the second signal comprises an intermediate frequency translation of the first on-channel portion. The energy levels are estimated for corresponding time instances and the adjacent channel interferer is of the adjacent channel portion. The VLIF receiver is then controlled based upon the detected interference.

Abstract: An electronic messaging device includes a receiver configured to receive a message at one of a first operational frequency and second operational frequency. The messaging device can operate using a time synchronous protocol and can receive commands through over-the-internet-programming (OTIP) and over-the-air-programming (OTAP).

Abstract: In one embodiment, an integrated circuit includes: a first input pad to receive a radio frequency (RF) signal; a radio receiver to process the RF signal and output a digitally processed signal; an analog filter to receive a digital signal via an input signal path and output a drive signal via an output signal path; and a first output pad coupled to the output signal path to output a filtered digital signal based on the drive signal.

Abstract: The present invention reduces the degradation in performance of one or more radio signals that are co-transmitted with a first radio signal from the same transmitting antenna in the same frequency channel and received by the same antenna due to multipath or other shared interference, where the one or more radio signals can be separated from the first radio signal. All received signals are coupled to the same adaptive array or adaptive filter to reduce multipath or other shared interference of the first radio signal, which reduces multipath and other shared interference in the other radio signals before they are separated and processed by their respective receivers, or the individual radio signals are separated before the first signal enters the adaptive array and coupled to a slave weighting network slaved to the weights of the adaptive array of the first signal to reduce interference in all the signals.

Abstract: The device includes: a signal generating unit generating a millimeter wave signal by signal processing of an input signal; a coupling circuit transmitting an electromagnetic wave from the millimeter wave signal generated by the signal generating unit to one end of a circuit board; a coupling circuit receiving the electromagnetic wave from the millimeter wave signal from the other end of the circuit board; and a signal generating unit that generates an output signal by signal processing of the millimeter wave signal from the electromagnetic wave received by the coupling circuit. Preferably, the circuit board is constituted by a dielectric material whose the dielectric loss tangent is relatively large, and a transmission line functioning as a millimeter wave transmission path is constituted within this circuit board. With this construction, extremely high-speed signals can be transmitted through a circuit board having a prescribed dielectric constant representing a large loss.

Abstract: Several embodiments of the present technology are related to network-on-chip based integrated circuits, methods of manufacturing or fabricating such integrated circuits, and electronic/computing devices incorporating such integrated circuits. In one embodiment, a computing device includes a substrate, a plurality of computing nodes interconnected by a plurality of interconnects on the substrate to form a wired network. The individual computing nodes include one or more computing processors. The computing device further includes a pair of wireless transceivers individually connected to one of the computing nodes and spaced apart from each other by a network diameter of the wired network.

Abstract: An electronic device that includes a deformable feature designed to seal two or more parts of the electronic device is disclosed. The deformable feature may be designed to deform, in response to a force applied to the deformable feature, with little or no compression. The deformable feature may include a cavity or relief volume extending along the deformable feature to define a space or void in the deformable feature. In response to a force, the deformable feature may deform such that a material (or materials) defining the deformable feature occupies or extends into the space or void, or in a location previously occupied by the space or void. The deformable feature may provide a protective seal between two or more parts that prevents ingress of contaminants, such as a liquid.

Abstract: A case for cooling a portable electronic device, the case including a housing and a cartridge. The housing holds the electronic device and has a cartridge compartment for retaining the cartridge. The cartridge includes sets of compartments for retaining substances configured to generate an endothermic reaction when mixed or combined. Pairs of compartments are separated by a divider configured to be selectively breached. The duration of the cooling effect may be extended by periodically breaching dividers of additional compartment pairs. The magnitude of the cooling effect may be increased by breaching multiple compartment pairs at once. The case may also include electronic components for monitoring the temperature of the electronic device and automatically initiating an endothermic reaction when the temperature reaches a predetermined threshold.

Abstract: The present invention relates to a casing for accommodating a computer based device or an activity board having an input/output port interface and/or an interface in form of a touch sensitive screen, comprising one or more operating means (e.g., levers, handles, buttons, knobs) and/or one or more apertures for interacting with said device, wherein said casing, at least partially, can cover the interface of said device.

Abstract: A first RF diplexer, which includes a first hybrid RF coupler, a second hybrid RF coupler, a first RF filter, and a second RF filter, is disclosed. The first hybrid RF coupler has a first main port, a first in-phase port, a first quadrature-phase port, and a first isolation port, which is coupled to a primary RF antenna. The second hybrid RF coupler has a second main port, a second in-phase port, and a second quadrature-phase port. The first RF filter is coupled between the first in-phase port and the second in-phase port. The second RF filter is coupled between the first quadrature-phase port and the second quadrature-phase port.

Abstract: Methods, systems, and devices are described for triggering an antenna switch. A settling time may be identified, and the antenna switch may be delayed based at least in part on the identified settling time. The settling time may include an estimated delay in reception attributable to settling following the antenna switch.