Abstract: According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In response to receipt of the data prefetch request, the memory controller provides a coherency response indicating an excess number of data prefetch requests. In response to the coherency response, the particular processor core reduces a rate of issuance of data prefetch requests.

Abstract: For on-demand migration of data in a distributed memory storage configuration, an identifier is transformed at a client into a transformed identifier. From a current configuration of a first plurality of servers operating on a server-side at a current time, a current server is identified at the client. From a previous configuration of a second plurality of servers operating on a server-side at a previous time, a previous server is identified at the client. A first request is sent to the current server to perform an operation using the identifier. A second request is sent to the previous server to perform the operation using the identifier. When a first data in response to the first request is invalid and a second data in response to the second request is valid, the second data is migrated to the current server in a migration request from the client to the current server.

Abstract: An electronic device includes a semiconductor memory that includes: a variable resistance element formed over a substrate; and a carbon-containing aluminum nitride layer formed on sidewalls and in an upper portion of the variable resistance element.

Abstract: A system and/or computer program product selectively adjusts a resources addresses cache of addresses of resources used by virtual processors. A first dispatch from a hypervisor dispatches a first virtual processor, and then tracks processes executed by the first virtual processor. The hypervisor caches cache addresses of resources used by the processes after the first dispatch in a resources addresses cache. The hypervisor undispatches the first virtual processor, and then redispatches the first virtual processor as a second virtual processor by issuing a second dispatch. Processes executed by the second virtual processor are compared to processes executed during by the first virtual processor, thus leading to an identification of a level of process utilization consistency. The hypervisor then adjusts the resources addresses cache by selectively clearing resource addresses based on the level of process utilization consistency.

Abstract: An apparatus includes an operand cache for storing operands from a register file for use by execution circuitry. In some embodiments, eviction priority for the operand cache is based on the status of entries (e.g., whether dirty or clean) and the retention priority of entries. In some embodiments, flushes are handled differently based on their retention priority (e.g., low-priority entries may be pre-emptively flushed). In some embodiments, timing for cache clean operations is specified on a per-instruction basis. Disclosed techniques may spread out write backs in time, facilitate cache clean operations, facilitate thread switching, extend the time operands are available in an operand cache, and/or improve the use of compiler hints, in some embodiments.

Abstract: An information processing device includes a main control circuit including a central arithmetic processor that executes first processing through a first program, a sub-control circuit that executes second processing independently of the first processing, a primary storage circuit, and a secondary storage circuit. The secondary storage circuit has a slower access speed than the primary storage circuit. The secondary storage circuit stores a second program used for third processing executed once the first processing and the second processing are both complete. The main control circuit further includes a cache memory having a faster access speed than the secondary storage circuit and a cache controller. In a situation in which the second processing is not yet complete at a completion time of the first processing, the cache controller executes pre-reading of the second program from the secondary storage circuit and stores the second program into the cache memory.

Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

Abstract: For browser cache cleanup, to consider for eviction a data item stored in a cache of a browser application in a device, a probability that the data item will be needed again during a period after the eviction is computed. A type is determined of a network that will be available at the device during the period. A cost is computed of obtaining the data item over a network of the type, from a location of the device during the period. Using the probability and the cost, a weight of the data item is computed. The weight is associated with the data item as a part of associating a set of weights with a set of data items in the cache. The data item is selected for eviction from the cache because the weight is a lowest weight in the set of weights.

Abstract: In one embodiment, a method includes receive a translation vector, selecting a translation entry from a plurality of translation entries, and determining whether the translation entry is associated with a first identifier class or a second identifier class. The translation vector includes a first identifier, a second identifier, and a virtual memory identifier. The first identifier is associated with a first identifier class, and the second identifier is associated with a second identifier class. The translation vector is received from a translation module including a memory configured to store the plurality of translation entries. Each translation entry from the plurality of translation entries including a virtual memory identifier. The translation entry is selected from the plurality of translation entries of the translation module based on the virtual memory identifier of the translation vector.

Abstract: A computer system that is programmed with virtual memory accesses to physical memory employs multi-bit counters associated with its page table entries. When a page walker visits a page table entry, the multi-bit counter associated with that page table entry is incremented by one. The computer operating system uses the counts in the multi-bit counters of different page table entries to determine where large pages can be deployed effectively. In a virtualized computer system having a nested paging system, multi-bit counters associated with both its primary page table entries and its nested page table entries are used. These multi-bit counters are incremented during nested page walks. Subsequently, the guest operating systems and the virtual machine monitors use the counts in the appropriate multi-bit counters to determine where large pages can be deployed effectively.

Abstract: A computer-implemented method for managing memory operations includes reading a first memory page from a storage device responsive to a request for the first memory page. The first memory page is stored to a system memory. Based on a pre-established set of association rules, one or more associated memory pages are identified that are related to the first memory page. The associated memory pages are read from the storage device and compressed to generate corresponding compressed associated memory pages. The compressed associated memory pages are also stored to the system memory to enable memory access to the associated memory pages during processing of the first memory page. The compressed associated memory pages are individually decompressed in response to the particular page being required for use during processing.

Abstract: The translation of virtual guest addresses to host physical addresses in a virtualized computer system provides a compound page table that may simultaneously support nested-paging and shadow-paging for different memory regions. Memory regions with stable address mapping, for example, holding program code, may be treated using shadow-paging while memory regions with dynamic address mapping, for example, variable storage, may be treated using nested-paging thereby obtaining the benefits of both techniques.

Abstract: The present disclosure provides a device comprising a memory translation buffer configured to manage (i) a first request for a first search in a page table, wherein the first request is responsive to a first null result of a search for a first address translation in a translation look-aside buffer (“TLB”) and (ii) a second request for a second search in the page table, wherein the second request is responsive to a second null result of a search for a second address translation in the TLB. The memory translation buffer is also configured to compare a virtual memory address of the first request to a virtual memory address of the second request and, based on a result of the comparing the virtual memory address of the first request to the virtual memory address of the second request, access the page table to perform the second search.

Abstract: A method including creating a transaction object for a transaction identified by a TOI and associated with an object identified by an OID, storing a TE and a MD frag for the transaction object, receiving a write request to write data to the transaction object, storing second TE including a TOI and offset and a data frag including the data, storing an entry including a hash value and a physical address of the data frag, and receiving a commit request to commit the transaction. In response to the commit request storing a third TE and a second MD frag for the transaction object, where the second MD frag identifies the object and specifies that the transaction is committed and updating a second entry including a second hash value and a second physical address for a second data frag to replace the second physical address with the physical address.

Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include defining, in a storage system including receiving, by a processor, metadata describing a first cache configured as a master cache having non-destaged data, and defining, using the received metadata, a second cache configured as a backup cache for the master cache. Subsequent to defining the second cache, the non-destaged data is retrieved from the first cache, and the non-destaged data is stored to the second cache.

Abstract: A device has a protection unit for controlling access to a memory. Indirect memory access requests have control data indicative of a memory access control register to be written to provide indirect access to a target memory and requested address data indicative of at least one memory address of the target memory to be accessed. The protection unit contains protection data defining access rights of source units to access specified address ranges of the target memory, and a system bus interface interfacing to a source unit and a memory bus interface interfacing to the target memory via a controller. The protection unit has a control monitor for detecting an indirect memory access request, and an indirect address monitor for comparing requested address data to specified address ranges and subsequently grant the indirect memory access in accordance with access rights of the respective source unit.

Abstract: A method for handling multiple networked applications using a distributed server system is disclosed. The method can include providing at least one main processor and a plurality of offload processors connected to a memory bus; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch receiving memory read/write data over the memory bus.

Abstract: A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the first memory through a bus (14); a second processor (11) that inputs and outputs processed data from and to the second memory through the bus; and a management unit 32 that deallocates an address range corresponding to the second memory from the first process and allocates the address range to the second processor.

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

Abstract: The present disclosure relates to an interface comprising a memory controller and a memory unit coupled to the memory controller and configured to communicate with the memory controller through a first signal and a second signal. The interface further comprises a determination unit comprising judgment logic configured to send a control signal configured to align the first signal with the second signal. The memory controller further comprises a digitally-controlled delay line (DCDL) coupled to the determination unit and configured to receive the control signal, wherein the determination unit instructs the DCDL to adjust a delay of the first signal to align the first signal with the second signal. The memory controller further comprises a value register configured to store a signal delay value corresponding to alignment between the first signal with the second signal which is contained within the control signal. Other devices and methods are disclosed.

Abstract: A low latency packet switching system comprising a switching device and a processing device. The switching device may include a first plurality of input/output (I/O) ports and a second plurality of I/O ports, wherein each port of the first plurality of ports may be electrically coupled to a pluggable transceiver socket configured to receive a cable connector. The processing device may include a plurality of transceivers electrically coupled to the second plurality of ports. The switching device may be configured to receive a first electric signal encoding one or more incoming data packets. The switching device may be programmed to output the first electric signal to one or more ports, in accordance with a programmable port mapping scheme. The processing device may be configured to receive the first electric signal and to output a second electric signal encoding one or more modified data packets derived from the incoming data packets.

Abstract: Techniques for polling an input/output (I/O) device are described herein. The techniques include polling a device for data from the I/O device, and receiving the data from the I/O device at the host device as a result of the polling. The techniques include determining whether the data received is the same as data received at a previous polling of the I/O device. Upon determining the data received is the same, the techniques include decreasing the polling rate if the data is the same, and if it is not the same. Upon determining the data is not the same, the techniques include increasing the polling rate if the data is not the same.

Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.

Abstract: An improved system and method for deinterleaving a data unit containing chunks of two or more different data types. In an embodiment of the invention, both a device MPU and DMA hardware are used to deinterleave a data unit containing chunks of both compressed data and uncompressed data. The device MPU is used to transfer compressed data from an interleaved data buffer to a compressed data buffer, while the DMA hardware is used to transfer uncompressed data from the interleaved data buffer to a compressed data buffer. By using both the MPU and the DMA hardware, the overall efficiency of the data transfer process is improved.

Abstract: An information handling system includes a processing node, an input/output (I/O) module coupled to the processing node via a high bandwidth interface, and a service processor coupled to the I/O module via a multi-master interface. A transaction between the processing node and the service processor that is targeted to a low pin count (LPC) bus is executed between the processing node and the service processor via the high bandwidth interface and the multi-master interface.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: A managed Universal Serial Bus (USB) service capability is disclosed. The managed USB service capability is configured to use a mobile computing device (e.g., a smartphone or other suitable mobile computing device) to support a set of services for a computer (e.g., a desktop, a laptop, and the like) capable of connecting to the mobile computing device via a USB connection. The managed USB service capability enables local and/or remote control of the mobile computing device to operate in various USB device classes, such that the mobile computing device can provide various managed USB services for the computer via the peripheral connection. In this manner, the mobile computing device may be dynamically configured to operate as one or more of a network interface, a virtual private network (VPN) client, a smart card, a serial console, a mass-storage device, a booting device, and the like.

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring provides a communication path along which an event packet is communicated to each rectangular island along the local event ring. The local event ring involves event ring circuits and event ring segments. Upon each transition of a clock signal, an event packet moves through the ring from event ring segment to event ring segment. Event information and not packet data travels through the ring. The local event ring functions as a source-release ring in that only the event ring circuit that inserted the event packet onto the ring can delete the event packet from the ring.

Abstract: The disclosed embodiments relate to a Flash-based memory module having high-speed serial communication. The Flash-based memory module comprises, among other things, a plurality of I/O modules, each configured to communicate with an external device over one or more external communication links, a plurality of Flash-based memory cards, each comprising a plurality of Flash memory devices, and a plurality of crossbar switching elements, each being connected to a respective one of the Flash-based memory cards and configured to allow each one of the I/O modules to communicate with the respective one of the Flash-based memory cards. Each I/O module is connected to each crossbar switching element by a high-speed serial communication link, and each crossbar switching element is connected to the respective one of the Flash-based memory cards by a plurality of parallel communication links.

Abstract: A system which is configured to enable a vehicle's embedded USB Host system to connect to multiple mobile devices through a USB Hub, regardless of whether the mobile devices are configured to act as USB Hosts or USB Devices, without the need to add or provide OTG controllers in the system or additional vehicle wiring, or inhibiting the functionality of any consumer devices operating in USB Device mode connected to a vehicle system Hub while another consumer device connected to the same Hub operates in USB Host mode. Preferably, the system is configured to provide that no additional cabling is required, and no hardware changes are required to be made to the HU. The system can be employed between a vehicle's embedded USB Host, USB Hub and at least one consumer accessible USB port.

Abstract: A flash memory drive comprising: a male USB connector; a female USB connector; a flash memory chip to store file data; a computing processor, operatively connected to the flash memory chip, to manage transfers of data to and from the flash memory chip; and a changeover switch, operatively connected to the computing processor, to connect the computing processor to one of the male USB connector and the female USB connector; wherein there is no data communication link between the male USB connector and the female USB connector when the changeover switch is connected to one of the male USB connector and the female USB connector.

Abstract: A server system includes a chassis having a plurality of insertion slots that receive a plurality of server plug-in modules; at least one printed circuit board including at least one first microcontroller and arranged in the chassis to contact server plug-in modules received in the insertion slots; and a first server plug-in module including a first system management controller and arranged in a first insertion slot and coupled to the at least one printed circuit board, wherein the first microcontroller and the first system management controller are coupled together via at least one first signal line, and the first microcontroller is arranged to provide the first system management controller with at least one chassis-specific configuration value.

Abstract: Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the content of the addressed message only when the target address matches an address assigned to that logic block.

Abstract: Methods, systems, and devices are described for supporting unknown peripheral function protocols (PFP) with a wireless docking station. A wireless docking station may facilitate connections between a wireless dockee and peripherals employing both recognized and unrecognized PFPs. A docking station may request one or more service discovery parameters from a peripheral having an unrecognized PFP. The docking station may receive service discovery parameters in response, convey the received discovery parameters to a wireless dockee, and facilitate discovery and a connection between the device and the peripheral. The discovery parameters may include various identifiers related to peripheral function, identity, and location.

Abstract: An electronic control unit includes a bus connection for a connection to a bus line of a current-controlled bus, an evaluation device for sampling the current flowing through the bus connection in order to detect a digital message from a sensor which is connectable to the bus line, and a current controller for generating a predefined current pulse through the bus connection in order to induce the sensor to assume a predefined synchronization state. The current controller is set up to control the current through the bus connection in such a way that it corresponds to an operating current through the sensor.

Abstract: An out-of-band to optical conversion component is provided that uses a transmit disable signal and a receive loss of signal (LOS) signal built into optical small form-factor pluggable transceiver and cable to pass the out-of-band protocol between serial attached SCSI enclosures. The transmit disable signal, when asserted, turns off the optical output, while the receive LOS signal detects the loss of signal. The out-of-band to optical conversion component sits in line on the serial attached SCSI data traffic and strips off the out-of-band signals from the serial attached SCSI expander so that only data flows over the optical cable. The out-of-band to optical conversion component sends the out-of-band signals to the other enclosure using the transmit disable pin on the small form-factor pluggable transceiver and cable. The other enclosure receives the message on the receive LOS signal and transmit it back onto the serial attached SCSI receive data pair.

Abstract: A finite state machine is provided that both serializes virtual GPIO signals and messaging signals and that deserializer virtual GPIO signals and the messaging signals. The finite state machine frames the serialized virtual GPIO signals and messaging signals into frames each demarcated by a start bit and an end bit.

Abstract: A graphics processing unit is disclosed, the graphics processing unit having a processor having one or more SIMD processing units, and a local data share corresponding to one of the one or more SIMD processing units, the local data share comprising one or more low latency accessible memory regions for each group of threads assigned to one or more execution wavefronts, and a global data share comprising one or more low latency memory regions for each group of threads.

Abstract: A plurality of performance-based storage nodes and a plurality of capacity-based storage nodes of a data storage system in a network environment are allocated to one or more tiered resource pools such that the performance-based storage nodes and the capacity-based storage nodes allocated to each one of the one or more tiered resource pools are addressable via a given virtual address for each tiered resource pool. Access to the performance-based storage nodes and the capacity-based storage nodes in the one or more tiered resource pools by a plurality of compute nodes is managed transparent to the compute nodes via a given storage policy. At least portions of the compute nodes, the performance-based storage nodes, and the capacity-based storage nodes are operatively coupled via a plurality of network devices. One or more of the allocating and managing steps are automatically performed under control of at least one processing device.

Abstract: A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

Abstract: A music and audio playback system is implemented on a computer with a playback engine that enables the operator to apply a variety of effects. The system may store one or more snapshots, or a combination of settings for a plurality of controls that are applied by the playback engine. These snapshots allow for changes to settings for effects, mixing and playback to be made quickly, some of which would normally be difficult to perform. A sampler module permits a user to specify one or more samples that may be triggered for playback. The most frequently used samples may be designated as scratching files that may be quickly activated through the push of a button (or other control). Additionally, a waveform display represents a window of audio samples around a current playback time.

Abstract: A driver assisting system and method for a vehicle are provided. The system includes a processor and a display system. The display system is adapted to display information on a screen of a vehicle. The screen is adapted to show the environment in front of the vehicle or a representation thereof. The vehicle extends in a longitudinal direction and a lateral direction, the longitudinal direction corresponding to the intended direction of vehicle travel. The processor is adapted to receive a first input data signal indicative of a velocity of the vehicle, and a second input data signal indicative of an actual performed and/or on-going and/or impending lateral position change of the vehicle. The processor is further adapted to process at least the first and the second input data signals to calculate an estimated vehicle path, and the display system is adapted to display the estimated vehicle path on the screen.

Abstract: A normal-line detection method for finding the normal vector of a measurement surface of a measurement target by means of at least one distance detector and calculating the normal vector from the measurement results thus obtained is provided. The normal vector of the measurement surface is found by calculating the exterior product of a first vector which connects a first measurement point and a second measurement point and a second vector which connects a third measurement point and a fourth measurement point and is shifted in parallel such that an end thereof is set at any one of the first measurement point and the second measurement point.

Abstract: A method includes receiving a set of parameters for a given project and generating, using information from a knowledge database, a plurality of combinations of group members based at least in part on the set of parameters. The method also includes evaluating a set of metrics for each of the combinations of group members, the set of metrics comprising at least one novelty metric and at least one collective intelligence metric. The method further includes generating one or more strategy matrices for each of at least a subset of the combinations of group members using information from the knowledge database, evaluating the combinations of group members in the subset using the strategy matrices to determine respective predicted success values, and selecting a given one of the combinations of group members for the given project based at least in part on the sets of metrics and predicted success values.

Abstract: Methods and apparatus for various embodiments of a text adjustment tool provide direct modification of typographic attributes of displayed text by translating indications of movement across a display, received via user input, into typographic attribute modifications. The text adjustment tool allows a user an intuitive method for modifying typographic attributes of displayed text without a user needing to access any menu windows or without even knowing which typographic attribute is being modified. The intuitive nature of the text adjustment tool is reflected by the fact that at no point during a modification of a typographic attribute of targeted text does a user's eyes ever need to leave the text being modified.

Abstract: Implementing an electronic calendar can include accessing a first electronic calendar owned by a first party, accessing a second electronic calendar owned by a second party, and presenting a view that combines at least one existing entry from within each of the first and second electronic calendars. Source information for each of the first and second electronic calendars may be electronically maintained. The combined view may be updated electronically to reflect a change to at least one of the existing entries from within at least one of the first and second electronic calendars. Electronic calendars may be accessed and overlaid without importing events, thus enabling simple updating. Event information may be imported and source or other attributes may be associated with imported information to enable updating and other sorting functions.

Abstract: A mobile multimedia content aggregation and dissemination platform is provided that aims to automate the creation, collection, aggregation, and dissemination of RSS and non-RSS information for and to interested parties. This platform may be used for the construction of a personalized blogging agent as well as for a personalized news aggregator.

Abstract: Techniques pertaining to embedding fonts in a PDF document are disclosed. A processing component executing a PDF application programming interface (API) may be operative to identify each character in a PDF file associated with an un-embedded font. The PDF API may store a bitmap representation for each identified character in the PDF file associated with the un-embedded font. The PDF API may then create a bitmap font character from the bitmap representation for each identified character in the PDF file associated with an un-embedded font and replace each reference to a character in the PDF file associated with an un-embedded font with a reference to its corresponding bitmap font character.

Abstract: A system and machine-implemented method for providing a font is provided. A request is received from a client device to download a font. The requested font is accessed, where the accessed font includes a corresponding character map and a corresponding glyph table. A supported character list and a modified font based on the corresponding character map, the modified font is compressed, and the supported character list and the compressed modified font are sent to the client device. Character data is also sent to the client device, wherein the character data is for merging the at least one character into the modified font based on information in the character data.