Abstract: Systems and methods for growing hexagonal crystal structure piezoelectric material with a c-axis that is tilted (e.g., 25 to 50 degrees) relative to normal of a face of a substrate are provided. A deposition system includes a linear sputtering apparatus, a translatable multi-aperture collimator, and a translatable substrate table arranged to hold multiple substrates, with the substrate table and/or the collimator being electrically biased to a nonzero potential. An enclosure includes first and second deposition stations each including a linear sputtering apparatus, a collimator, and a deposition aperture.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting characteristics of an input signal. One aspect includes a first finite input response (FIR) filter, a second FIR filter, and a controller coupled with the first and second FIR filters. The first FIR filter receives an input signal and a first reference signal. The first FIR filter filters the first reference signal to generate a first sinusoidal signal and mixes the first sinusoidal signal and the input signal to generate a first mixed signal. The second FIR filter receives the input signal and a second reference signal. The second FIR filter filters the second reference signal to generate a second sinusoidal signal and mixes the second sinusoidal signal and the input signal to generate a second mixed signal. The controller determines characteristics of the input signal based on the first and second mixed signals.

Abstract: A method for data filtering includes segmenting a to-be-detected vector to obtain k to-be-detected sub-vectors, respectively performing an inner product operation on the k to-be-detected sub-vectors and corresponding detection vectors among preset k detection vectors to obtain k first operation results, determining a first operation result whose value is the maximum among the k first operation results and obtaining an identifier of a detection vector corresponding to the first operation result, where a detection vector is in a one-to-one correspondence to an identifier, and mapping the to-be-detected vector to a preset data filter according to the obtained identifier of the detection vector corresponding to the first operation result whose value is the maximum, and determining, using the data filter, whether to filter out the to-be-detected vector.

Abstract: The invention is a method that combines the following components: 1. a high pass filter designed to have sufficiently small phase delay and roll-off value in transition band as well as sufficiently good attenuation; 2. a distortion detection and reconstruction introduced by the application of the high pass filter by extraction the significant frequency components in relevant frequency band; 3. a signal compensation that reshapes the output of the high pass filter by matching the filter's phase delay and attenuation characteristics so as to approximate low frequency component extraction that would be produced by an ideal filter (very sharp frequency transition and no delay); 4. a time-domain detection and correction method that addresses special circumstances under which the compensation would be inaccurate to achieve real-time estimate in normal circumstances, and 5. a time-domain correction method during and immediately after sudden changes in composite signal (spike) is detected.

Abstract: A semiconductor integrated circuit device includes a chip main circuit, a damper and a passive component. The chip main circuit is coupled to a power source and performs a predetermined function. The damper is coupled to an output terminal of the chip main circuit. The passive component is coupled to the chip main circuit via the damper.

Abstract: A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.

Abstract: According to an embodiment, a buffer circuit may be provided. The buffer circuit may include a first buffer configured to receive first and second external clock signals and generate a first pre-clock signal based on falling timings of the first and second external clock signals. The buffer circuit may include a second buffer configured to receive the first and second external clock signals and generate a second pre-clock signal based on raising timings of the first and second external clock signals.

Abstract: An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.

Abstract: A duty cycle detector (DCD) circuit may include: a duty cycle detector including one or more capacitor sets which are charged, discharged, or charged and discharged a clock, and suitable for detecting a duty cycle of the clock; and a frequency detector suitable for detecting a frequency of the clock. Each of the one or more capacitor sets has an adjustable capacity according to the frequency detection result of the frequency detector.

Abstract: A semiconductor device includes a plurality of semiconductor switching elements disposed on a single semiconductor substrate comprising a semiconductor having a bandgap that is wider than that of silicon; and a plurality of electrode pads that are disposed in a predetermined planar layout on a front surface of the semiconductor substrate, the plurality of electrode pads each being electrically connected to the plurality of semiconductor switching elements. A plurality of terminal pins to externally carry out voltage of the electrode pads is bonded through a plated film to all of the plurality of electrode pads by solder.

Abstract: A semiconductor device includes a high side driver, in which the high side driver has an output transistor configured to supply a power voltage to an output terminal based on a driving voltage applied to a gate electrode of the output transistor; a short circuit transistor configured to couple the gate electrode of the output transistor with the output terminal; and a switch transistor connected in series between the gate electrode of the output transistor and a drain electrode of the short circuit transistor. The switch transistor is controlled by a back gate of the switch transistor.

Abstract: A power-on-reset (POR) circuit is suitable for use in an integrated circuit including at least one CMOS logic block that includes PMOS and NMOS transistors respectively characterized by threshold voltages Vtp and Vtn, the CMOS circuitry operable with a power supply voltage Vdd. The POR circuit is operable to transition between a POR_active state and a POR_inactive state, including outputting a corresponding POR_state signal. The POR circuit includes: (a) VDD/VT threshold circuitry coupled to receive the Vdd voltage as an input to the POR circuit, and to provide a Vtp_threshold voltage based on Vdd and Vtp, and a Vtn_threshold voltage based on Vdd and Vtn; (b) POR transition detect circuitry coupled to the VDD/VT threshold circuitry to provide a POR_transition signal based on a function(Vtp,Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry coupled to the POR transition detect circuitry to provide the POW_state signal based on the POR_transition signal.

Abstract: There are provided a switch driving device and a switch driving method capable of preventing a self-turn-on phenomenon. The switch driving device includes: a first signal output unit configured to output a pulsed first driving signal from a first output terminal thereof; a second signal output unit configured to output a pulsed second driving signal to a control terminal of a switching element from a second output terminal thereof; and a negative power supply generating unit configured to generate a negative voltage relative to a ground voltage and bias a low level of the second driving signal toward a negative side by the negative voltage. The negative power supply generating unit includes: a first capacitor configured to store charge by the first driving signal; and a second capacitor configured to generate the negative voltage across terminals thereof by the transfer of the charge from the first capacitor.

Abstract: An emitter switched bipolar transistor circuit includes a bipolar junction transistor (BJT) having a collector coupled to an output terminal, a metal oxide semiconductor field effect transistor (MOSFET) coupled to an emitter of the BJT, a bias voltage supply coupled to the base of the BJT, a buffer coupled to the base of the BJT, and a comparator. The comparator includes a first input coupled to the collector of the BJT, a second input coupled to a voltage reference, and an output coupled to an input of the buffer. The comparator is configured to receive a collector voltage of the BJT at the first input of the comparator, compare the received collector voltage with the voltage reference, and cause the buffer to inject a current pulse to the base of the BJT until the collector voltage is less than the voltage reference, indicating the BJT is substantially saturated.

Abstract: There is provided an integrated circuit device; a feedback circuit; a transistor which generates an amplification modulation signal amplified from a modulation signal pulse-modulated from a source signal, based on an amplification control signal; a low pass filter which demodulates the amplification modulation signal and generates a driving signal for a capacitive load.

Abstract: An operation unit comprises a touch panel display, a home key and a power saving key. The power saving key includes an indication portion, and a first indication portion out of the indication portion has light permeability, and a color of its surface is a dark color, and a second indication portion has no light permeability or has it hardly, which is constituted by a double-layered print. In a surface side of this second indication portion, a figure indicative of a power saving key is printed in silver ink, and in a rear side thereof, a figure indicative of the power saving key is printed in black ink. In a normal state, when a backlight is lit, a surface of the first indication portion is bright, and a surface of the second indication portion is darker than the surface of the first indication portion.

Abstract: A capacitive sensitive key structure includes a key, support component, fixing pad, substrate and conductive portion. The key includes a key body and a connection wall which encloses a receiving space. The support component is disposed in the receiving space and includes a body, conical wall, buffering space, and extending pad connected to the conical wall. The body abuts against the key body. The conductive portion is disposed at the bottom of the body and inside the buffering space. The substrate is connected to the fixing pad and has thereon a circuit unit and a sensing layer. The substrate is coated with an insulating layer which covers the sensing layer. When the key body is pressed to press against the support component, electrostatic changes occur because of changes in the distance between the conductive portion and the sensing layer; hence, the circuit unit sends electrical signals for driving electronic apparatuses.

Abstract: Implementations of the present disclosure provide a human interface including a light emitter and a pressure sensitive material. The pressure sensitive material has electrical properties configured to vary in relation to an amount of pressure applied thereto. The light emitter is coupled to the pressure sensitive material, wherein variation of the electrical properties of the pressure sensitive material causes variation of at least one illumination characteristic. Advantageously, the pressure sensitive material provides an additional control component allowing bundling of controls in a simpler interface. At the same time, operation of the human interface in low-light or distracted environments is facilitated and rendered more intuitive by incorporation of the light emitter into its operation.

Abstract: Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits.

Abstract: A buffer circuit includes a buffer group including an odd number of cascade buffers, where the buffers may be different from each other; a PMOS transistor and an NMOS transistor; where a source of the PMOS transistor is coupled to a power source, a drain thereof is connected to an output terminal of the buffer group, and a gate thereof is connected to an input terminal of the buffer group; a source of the NMOS transistor is coupled to ground, a drain thereof is connected to the output terminal of the buffer group, and a gate thereof is connected to the input terminal of the buffer group.

Abstract: In some embodiments, a PLC system includes a memory unit configured to back up user data stored in a MCU thereto when the power supply from the power module is interrupted, a capacitor configured to be charged by the power module and supply accumulated power to the memory unit when the power from the power module to the MCU is interrupted, a variable resistor unit configured to be coupled between the power module and the capacitor, and a switching unit configured to alternatively couple either the power module or the capacitor to the memory unit depending on a state of power being supplied from the power module. Some embodiments may provide advantages that a PLC system can supply much more power while reducing a charging period of time of an auxiliary power supply for supplying power with urgency when an abnormality occurs in a power module of the PLC system.

Abstract: A counter circuit includes a first Johnson counter circuit and a second Johnson counter circuit coupled in cascade. Each Johnson counter circuit includes a clock input, a data input, a first clock data output, a second clock data output and a feedback from the second clock data input to first data input. The clock input of the first Johnson counter circuit is configured to receive an input clock signal. The clock input of the second Johnson counter circuit is connected to the second clock data output of the first Johnson counter circuit. A ripple counter circuit has a clock input and additional clock data outputs. The clock input of the ripple counter circuit is connected to the second clock data output of the preceding Johnson counter circuit.

Abstract: A receiving circuit includes: a detector configured to detect a position at which logics of first data and second data acquired by sampling received data using two clocks having mutually-different phases do not match each other as an edge; and an adjustment circuit configured to perform an adjustment causing an internal clock frequency to be close to a data frequency in the received data based on a first probability that logics of third data in a next cycle of the first data and the second data match each other and a second probability that logics of fourth data in a next cycle of the second data and the third data match each other.

Abstract: A frequency generating circuit includes: a differential delay circuit arranged to operably delay an input signal to generate a first delayed signal and a second delayed signal; a quartz crystal resonator arranged to operably conduct a band-pass filtering operation on one of the first and second delayed signals to generate a frequency signal; a compensation capacitor, coupled between another output of the differential delay circuit and an output of the quartz crystal resonator, arranged to operably suppress noise in the frequency signal; an oscillator arranged to operably generate an oscillating signal under control of a control signal; a frequency divider arranged to operably conduct a frequency-dividing operation on the oscillating signal to generate the input signal; and a feedback control circuit arranged to operably generate the control signal according to the frequency signal.

Abstract: Methods and systems for charge compensation for switched-capacitor circuits may comprise, in an electronics device comprising a first voltage source, a switched capacitor load, and a switched capacitor compensation circuit: switching a capacitor in the switched capacitor load from a first voltage to a second voltage; providing a charge to the switched capacitor load from the switched capacitor compensation circuit without requiring added charge from the first voltage source. A reference voltage may be generated utilizing the first voltage source. A replica reference voltage for the switched capacitor compensation circuit may be generated utilizing a second voltage source. The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device. Capacitors may couple outputs of the first and second voltage sources to ground.

Abstract: An analog to digital converter includes an analog input and a voltage comparator coupled to the analog input for comparing a voltage at the analog input to a digitally synthesized waveform. A digital to analog converter (DAC) generates the digitally synthesized waveform. The DAC includes a plurality of capacitors selectively connected in parallel wherein the period between the selection of capacitors is less than the settling time of the voltage across the capacitors.

Abstract: Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module.

Abstract: An analog-to-digital converter (ADC) may include a comparator and a metastability detector. The comparator may be configured to compare an input signal to a reference signal to determine whether the input signal exceeds the reference signal. The comparator may also be configured to output a comparator output based on the determination. An ADC output may be based at least in part on the comparator output. The metastability detector may be coupled to the comparator and may be configured to determine, based at least in part on the comparator output, that the comparator is operating under metastable conditions and may output a metastability detector output.

Abstract: A current mode sigma-delta modulator comprises an input node; a comparator that compares a voltage of the input node to a reference voltage and outputs a comparison result; an integrating capacitor connected to an input of the comparator; and a switched capacitor circuit connected at a first end to the input node, the input of the comparator, and the integrating capacitor, and connected at a second end to an output of the comparator. The current mode sigma-delta modulator is a component of an analog-to-digital converter.

Abstract: A method and apparatus for adjusting a bandwidth of a sigma delta converter by adjusting a reference voltage provided to the sigma delta converter. The apparatus includes a switched capacitor digital-to-analog converter in the feedback loop of the sigma delta modulator. The sigma delta modulator determines the bandwidth mode of the converter and adjusts the reference voltage to deliver high performance functionality. In one embodiment, a multi-bit digital signal is received by the digital-to-analog converter. The reference voltage is provided to multiple capacitive circuits of the digital-to-analog converter and the capacitive circuits are activated and deactivated based on the multi-bit digital signal. The digital-to-analog converter, thus, provides a feedback analog signal using dynamic element matching.

Abstract: Data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a system for compressing data comprises: a processor, and a plurality of data compression encoders wherein at least one data encoder utilizes asymmetric data compression. The processor is configured to determine one or more parameters, attributes, or values of the data within at least a portion of a data block containing either video or audio data, to select one or more data compression encoders from the plurality of data compression encoders based upon the determined one or more parameters, attributes, or values of the data and a throughput of a communications channel, and to perform data compression with the selected one or more data compression encoders on at least the portion of the data block.

Abstract: A processing device includes an accelerator circuit to identify a byte in a byte stream, determine whether a first byte string starting from a first byte position of the byte matches a second byte string starting from a second byte position, responsive to determining that the first byte string matches the second byte string, generate a token comprising a first symbol encoding a length of the first byte string and a second symbol encoding a byte distance between the first byte position and the second byte position, and responsive to determining that the first byte string does not match another byte string, generate the token comprising the first symbol comprising the byte and a second symbol encoding a determined value.

Abstract: A method and a device for performing a polar codes channel-aware procedure are provided. A plurality of bit-channels have a polar code construction which is dynamic. The method includes the following steps. A plurality of reliability indices of some of the bit-channels are ranked. Whether an updating condition is satisfied is determined according to a ranking sequence of the reliability indices. If the updating condition is satisfied, the polar code construction is updated according to the ranking sequence of the reliability indices.

Abstract: An apparatus for data coding includes an encoder and a decoder. The encoder is configured to receive input data including one or more m-bit data groups that are associated with respective group indices, to generate a code word that includes the input data and an m-bit redundancy that depends on the data groups and on the respective group indices, and to send the code word over a channel. The decoder is connected to the channel and is configured to produce a syndrome that equals zero when the code word is error-free, and when the code word contains a single error caused by the channel, is indicative of an erroneous group in which the single error occurred, and of a location of the single error within the erroneous group, and to recover the input data by correcting the single error at the location in the erroneous group.

Abstract: A wireless communication device including: a mixer configured to generate two mixed signal in a lower frequency band than a frequency of a local signal and two mixed signals in a higher frequency band than the frequency of the local signal by mixing the local signal with two intermediate frequency signals, and a filter configured to pass one of the two mixed signal in the lower frequency band and one of the two mixed signal in the higher frequency band.

Abstract: A receiver front end arrangement comprises a radio frequency signal input suitable to be connected to an antenna arrangement, a filter bank of non-overlapping band filters associated with respective band for the multi-band reception, a signal conditioning arrangement connected to the filter bank, and a low-noise amplifier arrangement connected to the signal conditioning arrangement. The low-noise amplifier arrangement comprises a path for each band of bands of the multi-band reception. For each path associated with a band for the multi-band reception the low-noise amplifier arrangement comprises a low-noise amplifier. The respective low-noise amplifier has band pass characteristics, or has a band filter connected where the band filter output has a direct connection to the input of the low-noise amplifier, corresponding to a band of the multi-band reception, respectively.

Abstract: A distortion compensation device includes an address generating unit, a look up table (LUT), and a multiplier. The address generating unit calculates pieces of difference information for different combinations each including transmission signals at different timings. Each of the pieces of difference information is the difference in amplitude or power between the transmission signals in a corresponding one of the combinations. The LUT specifies a distortion compensation coefficient by using the above pieces of difference information calculated by the address generating unit. The multiplier performs predistortion, using a distortion compensation coefficient specified by the LUT, on a transmission signal to be input to an amplifier.

Abstract: A radio-frequency module comprises a low-noise amplifier including a common source transistor having a gate node that receives a radio-frequency input signal and a drain node that transmits a combined radio-frequency output signal, and a correction signal input path configured to receive a correction signal and provide the correction signal to a source node of the common source transistor to generate, at least in part, the combined radio-frequency output signal.

Abstract: In an embodiment, an apparatus includes a first transmit path, a second transmit path, and a switch element. The first transmit path can provide a first radio frequency (RF) signal in accordance with a nominal specification. The second transmit path can provide a second RF signal in accordance with an intermittent specification, in which the first and second RF signals are within the same transmit band. The switch element can provide the first RF signal as a transmit mode output in a first state and provide the second RF signal as the transmit mode output in a second state.

Abstract: A system, method, and array of transceivers are disclosed. The disclosed method enables an efficient mechanism for managing electromagnetic radiation by a first processing device and a second processing device into a common area. Concepts of employing different time-varying phase delays at the different emitters of electromagnetic radiation help to minimize the otherwise cumulative effects of multiple emitters being located in close proximity to one another.

Abstract: A wireless receiver includes an RF muting circuit that opens and closes a signal line of a demodulated signal according to a received carrier strength level, a noise muting circuit that opens and closes the signal line according to a noise level in the modulated signal, and an RF attenuation circuit that attenuates a RF signal handled in a RF amplifier circuit, and additionally includes a reception mode switching circuit which can simultaneously select at least any two values from those comprising one of a plurality of predetermined threshold values of the RF muting circuit, one of a plurality of predetermined threshold values of the noise muting circuit and one of a plurality of predetermined amount of attenuation of the RF attenuation circuits. This configuration allows to provide a wireless receiver having a stable reception characteristics without sound interruption or interferences in a multi-wave operation of wireless microphones.

Abstract: Under one aspect, a method is provided for processing a received signal, the received signal including a desired signal and an interference signal that spectrally overlaps the desired signal. The method can include obtaining an amplitude of the received signal. The method also can include obtaining an average amplitude of the received signal based on at least one prior amplitude of the received signal. The method also can include subtracting the amplitude from the average amplitude to obtain an amplitude residual. The method also can include, based upon an absolute value of the amplitude residual being less than or equal to a first threshold, inputting the received signal into an interference suppression algorithm so as to generate a first output including the desired signal with reduced contribution from the interference signal.

Abstract: A wireless receiver includes an RSSI generation circuit that obtains RSSI output corresponding to a carrier strength level of a received RF signal; a lookup table from which a threshold value corresponding to temperature information from a temperature sensor is read based on the temperature information; a comparison circuit that generates comparison output when the RSSI output is below the threshold value read from the lookup table, in which the threshold value is one input, and the RSSI output from the RSSI generation circuit is the other input; and a muting circuit that closes a signal line of an audio signal demodulated from the RF signal, and cuts off output of the audio signal, based on the comparison output from the comparison circuit. The above configuration enables the wireless receiver to eliminate fluctuation of a reception reaching distance relative to temperature change, and ensure stable mute operation.

Abstract: A method of operating a receiver includes a controller of the receiver determining whether a full initialization or a partial initialization of the receiver is needed; the controller adjusting alternating current (AC) characteristics and direct current (DC) characteristics of the receiver in a full initialization mode, and the controller adjusting the DC characteristics of the receiver in a partial initialization mode when the controller determines the partial initialization is needed.

Abstract: A method is provided that comprises tuning a radio system to a frequency band that contains a locally-broadcast terrestrial radio signal. The locally-broadcast terrestrial radio signal comprising a main signal component and a side data component is thereby received. In response to receiving the locally-broadcast terrestrial radio signal a determination is made as to a permissible time for processing the side data component using a time slot schedule. The side data component is processed at the permissible time. A message corresponding to the side data component is outputted to an output device. In some instances, the side data component includes the message. In other instances, the method further includes searching a message lookup list using a code included in the side data component. When a stored code is found that matches the code, the message corresponding to the matching stored code is outputted.

Abstract: A device includes, in part, an antenna adapted to receive an RF signal that includes modulated data, a splitter/coupler adapted to split the received RF signal, a receiver adapted to demodulate the data from a first portion of the RF signal, and a power recovery unit adapted to convert to a DC power a second portion of the RF signal. The splitter/coupler is optionally adjustable to split the RF signal in accordance with a value that may be representative of a number of factors, such as the target data rate, the DC power requirement of the device, and the like. The device optionally includes a switch and/or a power combiner adapted to deliver all the received RF power to the receiver depending on any number of operation conditions of the device or the device's distance from an RF transmitting device.

Abstract: In an embodiment, an apparatus includes a first transmit path, a second transmit path, and a switch element. The first transmit path can provide a first radio frequency (RF) signal in accordance with a nominal specification. The second transmit path can provide a second RF signal in accordance with an intermittent specification, in which the first and second RF signals are within the same transmit band. The switch element can provide the first RF signal as a transmit mode output in a first state and provide the second RF signal as the transmit mode output in a second state.

Abstract: A casing comprising a flip cover, configured to encase at least a part of a mobile device having a camera, the flip cover comprising an optical filter located to enable image capturing by the camera through the optical filter.

Abstract: An electronic device may include: at least one protective member disposed in at least one area of the electronic device; at least one sensor configured to detect the drop of the electronic device; a protective member driving module configured to activate the protective member to change the shape of the protective member according to whether the drop of the electronic device is detected; and at least one processor configured to receive a drop sensing signal detected by the sensor and to control the protective member driving module to change the shape of the protective member.

Abstract: The disclosure provides a portable terminal including an electronic device and a case disposed thereon that provides water resistant, dust resistant, and insulation for the electronic device by proper positioning of an aperture of the electronic device that uses an area of the case as an antenna. The case includes a body part that comprises a main body with a metallic portion formed of a metallic material, and an auxiliary body disposed adjacent to the metallic portion, and at least a portion of the auxiliary body is used as an antenna for transmission and reception of signals. An insulation member is disposed between the at least a portion of the auxiliary body and the main body, and a bonding layer is disposed in at least one of an area between the insulation member and at least one area of the main body, or between the insulation member and the auxiliary body.