Abstract: An information processing apparatus includes a memory, a second processor, and a first processor. The second processor is configured to implement a virtual machine that accesses the memory. The first processor is coupled with the memory. The first processor is configured to read out first data from a first area of the memory. The first area is to be accessed by the virtual machine. The first processor is configured to store the first data in a cache of the first processor.

Abstract: Technology is provided for partitioning a shared unified cache in a multi-processor computer system. The technology can receive a request to allocate a portion of a shared unified cache memory for storing only executable instructions, partition the cache memory into multiple partitions, and allocate one of the partitions for storing only executable instructions. The technology can further determine the size of the portion of the cache memory to be allocated for storing only executable instructions as a function of the size of the multi-processor's L1 instruction cache and the number of cores in the multi-processor.

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

Abstract: A computing system includes multiple compute nodes that include respective processors and respective cache memories. The processors are configured to determine a default compute node in which a given data item is to be cached, to make a decision whether to cache the given data item in the default compute node or in an alternative compute node, based on cache-quality metrics that are evaluated for respective cache memories of the compute nodes, and to cache the given data item in the default compute node or in the alternative compute node, depending on the decision.

Abstract: A storage system, maintains a cache and a non-volatile storage. Active tracks in the non-volatile storage are determined. The determined active tracks in the non-volatile storage are validated between the cache and the non-volatile storage during a warmstart recovery.

Abstract: Provided are a computer program product, system, and method for populating a second cache with tracks from a first cache when transferring management of the tracks from a first node to a second node. Management of a first group of tracks in the storage managed by the first node is transferred to the second node managing access to a second group of tracks in the storage. After the transferring the management of the tracks, the second node manages access to the first and second groups of tracks and caches accessed tracks from the first and second groups in the second cache of the second node.

Abstract: A request is received over a link that requests a particular line in memory. A directory state record is identified in memory that identifies a directory state of the particular line. A type of the request is identified from the request. It is determined that the directory state of the particular line is to change from the particular state to a new state based on the directory state of the particular line and the type of the request. The directory state record is changed, in response to receipt of the request, to reflect the new state.

Abstract: A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback.

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract: In one embodiment, a method for predicting false sharing includes running code on a plurality of cores and determining whether there is potential false sharing between a first cache line and a second cache line, and where the first cache line is adjacent to the second cache line. The method also includes tracking the potential false sharing and reporting the potential false sharing.

Abstract: An apparatus and method are provided for operating a virtually indexed, physically tagged cache. The apparatus has processing circuitry for performing data processing operations on data, and a virtually indexed, physically tagged cache for storing data for access by the processing circuitry. The cache is accessed using a virtual address portion of a virtual address in order to identify a number of cache entries, and then physical address portions stored in those cache entries are compared with the physical address derived from the virtual address in order to detect whether a hit condition exists.

Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.

Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.

Abstract: In a memory system including a memory device including a plurality of storage regions, and a controller suitable for selecting storage regions indicated by logical addresses from among the plurality of storage regions using a mapping table storing a plurality of pieces of mapping information for mapping a plurality of logical addresses to a plurality of physical addresses corresponding to the plurality of storage regions. The controller may narrow a search range in which a second requested logical address of N logical addresses (N is an integer greater than 2) is to be searched for in the mapping table based on a position in which the mapping information corresponding to a first requested logical address of the N logical addresses has been stored in the mapping table when the N logical addresses are sequentially searched for in the mapping table.

Abstract: Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing and managing storage class memory (SCM) enabled main-memory database structures. An embodiment operates by traversing a first node to find a location of a second node corresponding to a search key, calculating a hash value for the search key, comparing the calculated hash value with at least one fingerprint value stored in the second node, wherein the fingerprint value is determined by hashing a stored key, accessing at least one key-value pair having a matching hash value, and returning a value associated with the matching key-value pair, wherein at least one of the traversing, calculating, comparing, accessing, and returning are performed by one or more computers.

Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.

Abstract: A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.

Abstract: A storage device includes a storage unit having a plurality of routing circuits networked with each other, each of the routing circuits configured to route packets to a plurality of node modules that are connected thereto, each of the node modules including nonvolatile memory, and a plurality of connection units, each coupled with one or more of the routing circuits, and configured to access each of the node modules through one or more of the routing circuits. Each of the connection units is configured to transmit an inquiry to a target node module, to initiate a write operation, and determine whether or not to transmit a write command based on a notice returned by the target node module in response to the inquiry.

Abstract: A system can include at least one computing module comprising a physical interface for connection to a memory bus, a processing section configured to decode at least a predetermined range of physical address signals received over the memory bus into computing instructions for the computing module, and at least one computing element configured to execute the computing instructions.

Abstract: An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.

Abstract: In certain information handling system environments, users may collaborate or communicate via remote conferencing software. In some instances an attendee may request that a selected universal serial bus (USB) device associated with another attendee be redirected such that the content of the selected USB device may be available to one or more attendees or that content may be communicated to the selected USB device. The server may receive requests associated with a selected USB device and redirect those requests to the selected USB device. The selected USB device may only be redirected to a selection of the one or more attendees based on one or more parameters associated with the one or more attendees.

Abstract: A camera includes an input/out system and one or more input/output ports. The camera configures the pins of the input/output port according to a default pin configuration. The camera detects a peripheral device is connected the input/output ports and receives an identifier from the peripheral device indicating whether the peripheral device is a USB3 device or a non-USB3 device. If the peripheral device is a non-USB3 device, the camera remaps the pins to a first configuration. The camera authenticates with the peripheral device to determine if the peripheral device meets a criteria for an approved device. If the authentication is successful, the camera enables communication with the peripheral device and remaps the pins to a second configuration. If the authentication is unsuccessful, the camera disables communication with the peripheral device and remaps the pins of the input/output port to the default configuration.

Abstract: The present invention discloses a data output dispatching device and method capable of reducing the probability of packets from the same queue being transmitted sequentially. An embodiment of the method comprises the following steps: providing a plurality of buffers capable of storing the data of Q queues respectively while each queue is associated with a weighting and the sum Ws of all the weightings is between 2(M-1) and 2M and not greater than a maximum sum in which Q is an integer greater than 1, M is a positive integer and N is an integer not less than M; providing a binary bit reverse count value not greater than 2N; and assigning a token to one of the Q queues for data output according to the reverse count value.

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract: A system having master and slave devices and communicating over an I2C bus has SDA and a SCL lines that are normally high unless a device pulls the voltage of the line Low. Normal data signals on the SDA line are set during the low phase of the clock signals on the SCL line and transferred to a receiver during the high phase of the clock signals. A slave device provides an alert signal on the SDA line during the low phase of the clock signals to send an alert signal to the master device. The alert signal may be a pulse signaling the slave device wakeup or a pulse pattern identifying the alerting slave device.

Abstract: A method is provided that compensates for misalignment on a synchronous data bus.

Abstract: An information processing apparatus includes a plurality of processing modules that are connected to each other on a ring bus, a connector for optionally attaching to an extension processing unit, a detection unit configured to detect attachment of the extension processing unit to the connector, and a bus switching unit configured to change, in a case where the detection unit detects the attachment of the extension processing unit, a path of the ring bus in such a manner that an extension processing module in the extension processing unit is connected.

Abstract: A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

Abstract: Embodiments of a method, a device and a computer-readable storage medium are disclosed. In an embodiment, a method for operating a Controller Area Network (CAN) device involves in response to receiving bits of an arbitration field of a CAN data frame at the CAN device, selecting a timing engine from a plurality of timing engines and sampling subsequent bits of the CAN data frame using the selected timing engine. The timing engines have different sample clock frequencies.

Abstract: This invention expands the scope of application of a pass-through technology in which a guest OS directly controls a remote device that is connected via a network. This data-processing apparatus is provided with a host OS that provides a virtual hardware environment to a guest OS that performs I/O processing with respect to a device implemented in a remote apparatus connected via a network. The host OS has a bus extension unit that traps I/O instructions issued by the guest OS, encapsulates the trapped I/O instructions, and delivers the encapsulated I/O instructions to the remote apparatus as network packets.

Abstract: A Universal Serial Bus (USB) split cable is disclosed. In one aspect, the USB split cable provides a USB full-featured Type-C host plug for connecting to a USB Type-C receptacle in a USB host. In another aspect, the USB split cable provides a plurality of USB device plugs for connecting to a plurality of device clients, respectively. The plurality of USB device plugs can be configured individually with different data pin combinations to concurrently support different device clients. By providing the USB split cable, it is possible to support point-to-multipoint USB connection via the plurality of USB device plugs without a USB hub, thus improving mobility of the USB host while reducing costs and power consumption associated with the USB hub.

Abstract: A USB Type-C secondary data channel communication system includes a controller system coupled to a first USB Type-C connector. The controller system determines a second USB Type-C connector orientation when a second USB Type-C connector is connected to the first USB Type-C connector. The controller system then communicates with a connected system through a first data channel available through the second USB Type-C connector and determines that the connected system provides a second data channel mode. In response to determining the connected system provides the second data channel mode, the controller system uses the second USB Type-C connector orientation to configure the provisioning of first data through the first data channel and second data through a second data channel that is available through the second USB Type-C connector. Different data communications may then be provided to the connected system using the first and second data channels.

Abstract: System, methods, and apparatus are described for transmitting encoded bits over a bus by conditionally embedding dynamically shielded information, in an example, the apparatus transmits a first group of encoded bits over a bus, generates a second group of encoded bits to be transmitted over the bus, where a first subset of the second group of encoded bits are encoded to avoid crosstalk-inducing bit transitions on adjacent lines of the bus, and configures one or more encoded bits of a second subset of the second group of encoded bits to ensure that the second group of encoded bits includes parity information and/or clock information, while further ensuring that crosstalk-inducing bit transitions in the second group of encoded bits are avoided.

Abstract: A peripheral controller, and method of operation, for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, are described. A FIFO includes a FIFO controller and a FIFO memory and has a plurality of inputs. A multiplexer circuit is connected to the plurality of inputs, and is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A cache management system performs cache management in a Remote Direct Memory Access (RDMA) key value data store. The cache management system receives a request from at least one client configured to access a data item stored in a data location of a remote server, and determines a popularity of the data item based on a frequency at which the data location is accessed by the at least one client. The system is further configured to determine a lease period of the data item based on the frequency and assigning the lease period to the data location.

Abstract: A cache management system performs cache management in a Remote Direct Memory Access (RDMA) key value data store. The cache management system receives a request from at least one client configured to access a data item stored in a data location of a remote server, and determines a popularity of the data item based on a frequency at which the data location is accessed by the at least one client. The system is further configured to determine a lease period of the data item based on the frequency and assigning the lease period to the data location.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Systems and methods of determining a global model are provided. In particular, one or more local updates can be received from a plurality of user devices. Each local update can be determined by the respective user device based at least in part on one or more data examples stored on the user device. The one or more data examples stored on the plurality of user devices are distributed on an uneven basis, such that no user device includes a representative sample of the overall distribution of data examples. The local updates can then be aggregated to determine a global model.

Abstract: Techniques to perform data reduction for statistical tests are described. An apparatus may comprise an evaluation component to receive a computational representation arranged to generate an approximate probability distribution for statistics of a statistical test, the computational representation to include a simulated data structure with information for estimated cumulative distribution function (CDF) curves for one or more parameter vectors of the statistical test, each parameter vector represented with a single point in a grid of points, the evaluation component to evaluate the simulated data structure to determine whether any points in the grid of points are removable from the simulated data structure with a target level of precision, and a data reduction generator to reduce the simulated data structure in accordance with the evaluation to produce a reduced simulated data structure having a smaller data storage size relative to the simulated data structure. Other embodiments are described and claimed.

Abstract: This factor analysis device is provided with a feature extraction unit (1021) that extracts feature quantities from an explanatory time series, a feature conversion unit (1022) that converts said feature quantities to a feature time series, a feature-time-series influence-degree computation unit (1031) that uses said feature time series and a response time series to compute an influence degree indicating the degree to which the feature time series influences the change over time represented by the response time series, and an explanatory-time-series influence-degree computation unit (1032) that uses said influence degree to compute an influence degree indicating the degree to which the explanatory time series influences the change over time represented by the response time series.

Abstract: The present subject matter discloses system and method for generating a scalar vector graphics (SVG) image in an imaginary console. The system receives one or more image parameters, corresponding to the image, from the user. Further, the imaginary console emulates a browser environment by using a JavaScript Engine and a browser emulator. The SVG executer processes the one or more image parameters corresponding to the image to render the image on the imaginary console, and produces the image having SVG format. Further, the document generator module may convert the image having the SVG format into the raster image based on report format specified by the user. Further, the document generator module embeds the image into the offline readable format to be used by the user.

Abstract: Embodiments of the present invention are related to systems and methods for detecting intentional or unintentional copying of text and further markup of similar text in digital documents. Further, it is an aspect of certain embodiments of the present invention to compare digital documents with published digital documents in order to identify and analyze risk associated with plagiarism.

Abstract: The present invention discloses a method for webpage processing and the system thereof, which comprises steps of: when a handheld device is visiting an HTML text file, the file will be parsed, addresses of multimedia contents in the file will be separated according to the current tag, and composed into a corresponding playlist, before distributed to a plurality of matched devices, while the HTML text file will be reorganized after the separation; the handheld device then opens the reorganized HTML file and shows the corresponding text format webpage, while a playback device plays the corresponding multimedia contents. The present invention takes full advantages of the playing back functions of each family used playback device, to play multimedia content, while a handheld device is used to show the text information only, and a playback device plays the corresponding multimedia contents, according to the type of data it is suitable to deal with.