Abstract: A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.

Abstract: A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X22. The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a C1 term of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a X2 term of the second instruction.

Abstract: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.

Abstract: A processor, apparatus and method to use a multiple store instruction based on physical addresses of registers are provided. The processor is configured to execute an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating apparatus is configured to generate an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating method includes detecting a code area that instructs to store data of a plurality of registers in a memory, from a program code. The instruction generating method further includes generating an instruction corresponding to the code area by mapping physical addresses of the registers to a first area of the instruction.

Abstract: Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.

Abstract: A data processing system is used to evaluate a data processing function by executing a sequence of program instructions including an intermediate value generating instruction Inst0 and an intermediate value consuming instruction Inst1. In dependence upon one or more input operands to the evaluation, an embedded opcode within the intermediate value passed between the intermediate value generating instruction and the intermediate value consuming instruction may be set to have a value indicating that a substitute instruction should be used in place of the intermediate value consuming instruction. The instructions may be floating point instructions, such as a floating point power instruction evaluating the data processing function ab.

Abstract: A trace unit for generating items of trace data indicative of processing activities of a processor executing a stream of instructions, the unit includes trace circuitry for monitoring a behavior of the processor; storage circuitry for storing current trace control data for controlling the trace circuitry; a data store for storing at least some of the trace control data; the trace circuitry being configured to store the trace control data in the data store in response to detection of execution of the group of instructions, wherein the trace circuitry is responsive to detecting the at least one processor cancelling at least one group of the speculatively executed instructions to retrieve at least some of the trace control data stored in the data store for the group of instructions executed before the cancelled speculatively executed instructions and to store the retrieved trace control data in the storage circuitry.

Abstract: An integrated circuit device comprising at least one instruction processing module arranged to receive a bit-manipulation instruction, and in response to receiving the bit-manipulation instruction to select at least one bit from at least one source data register in accordance with a value of at least one control bit, select from candidate values a manipulation value for the at least one selected bit in accordance with a value of at least one further control bit, and store the selected manipulation value for the at least one selected bit in at least one output data register.

Abstract: A processor core includes a front end, and first and second back ends, the front end including a fetch engine configured to retrieve the sequence of data processing instructions for both the first back end and the second back end from a memory, and the first and second back ends are each configured to execute the sequence of program instructions. The core operates in a first mode in which the first back end is active and receives the sequence of data processing instructions from the fetch engine and the second back end is inactive, and a second mode in which the first back end is inactive and the second back end is active and receives the sequence of data processing instructions from the fetch engine, where the cycles-per-instruction rate is lower and energy consumption is higher for the first mode than the second mode.

Abstract: A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.

Abstract: An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.

Abstract: One embodiment of the present invention sets forth a technique for managing buffer table entries in a tile-based architecture. The technique includes binding a plurality of shader registers to a buffer table entry. The technique further includes processing at least one tile by reading a buffer table index stored in the shader register to access the buffer table entry, reading a buffer address stored in the buffer table entry, accessing data associated with the buffer address, and unbinding the shader register from the buffer table entry. The technique further includes determining that none of the shader registers is still bound to the buffer table entry and, in response, causing a release packet to be inserted into an instruction stream. The technique further includes determining that a last tile has been processed and, in response, transmitting the release packet to cause the buffer table entry to be released.

Abstract: One embodiment of the present invention sets forth a graphics processing system configured to track event counts in a tile-based architecture. The graphics processing system includes a screen-space pipeline and a tiling unit. The screen-space pipeline includes a first unit, a count memory associated with the first unit, and an accumulating memory associated with the first unit. The first unit is configured to detect an event type and increment the count memory. The tiling unit is configured to cause the screen-space pipeline to update an external memory address to reflect a first value stored in the count memory when the first unit completes processing of a first set of primitives. The tiling unit is also configured to cause the screen-space pipeline to update the accumulating memory to reflect a second value stored in the count memory when the first unit completes processing of a second set of primitives.

Abstract: Branch prediction using a correlating event, such as an unconditional branch that calls a routine including the branch, instead of the branch itself, to predict the behavior of the branch. The circumstances in which the branch is employed, and not the actual branch itself, is used to predict how strongly taken or not taken the branch is to behave. An anchor point associated with the branch (e.g., an address of the instruction calling a routine that includes the branch), an address of the branch, and a value that represents the number of selected branch instructions between the anchor point and the branch are used to select information to be used to predict the direction of the branch.

Abstract: In an embodiment, a processor includes a register file having multiple widths corresponding to different operands sizes of a given data type implemented by the processor. For example, the integer register file may have 32 bit and 64 bit widths for 32 and 64 bit operand sizes. The register file may have a section of registers for each operand size, and the map unit may allocate registers from the appropriate section for each instruction operation based on the operand size of that instruction operation. The register file may consume less integrated circuit area than another register file having the same number of registers, all of which are implemented at the largest operand size. In some embodiments, only the register file and the map unit (specifically the free list management logic in the map unit) are changed to implement the multiple-width register file.

Abstract: Techniques relate to dynamic branch history pattern adjustment. Past histories of branch instruction results are collected as part of a branch history pattern. A branch prediction structure with a pattern history buffer predicts a direction of a branch instruction using the branch history pattern. The branch prediction structure executes one or more branch history pattern recording adjustment instructions prior to one or more branch instructions. Executing the one or more branch history pattern recording adjustment instructions changes default behaviors of recording and usage of the branch history pattern.

Abstract: A system and method for efficiently processing instructions in hardware parallel execution lanes within a processor. In response to a given divergent point within an identified loop, a compiler generates code wherein when executed determines a size of a next very large instruction world (VLIW) to process and determine multiple pointer values to store in multiple corresponding PC registers in a target processor. The updated PC registers point to instructions intermingled from different basic blocks between the given divergence point and a corresponding convergence point. The target processor includes a single instruction multiple data (SIMD) micro-architecture. The assignment for a given lane is based on branch direction found at runtime for the given lane at the given divergent point. The processor includes a vector register for mapping PC registers to execution lanes.

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Abstract: An information processing apparatus providing a specific function includes a non-volatile function program memory that stores a function program for providing the specific function, a main memory, and an arithmetic device that reads and stores the function program from the function program memory into the main memory at startup of the information processing apparatus and performs an arithmetic operation based on the function program to execute the function program. The arithmetic device operates at a start frequency set for startup as a clock frequency for accessing the function program memory when reading and storing the function program from the function program memory into the main memory at the startup, and operates at a frequency lower than the start frequency as the clock frequency for accessing the function program memory after reading and storing the function program into the main memory.

Abstract: A method and system is provided for optimizing a boot time of a computer system with at least one CPU, in response to a boot command. The system includes memory and a processor. The processor executes instructions stored in the memory to access a task description chart (TDC) comprising essential tasks related to the booting of the system. The TDC is processed offline to create two sets of scheduling charts: an independent task chart (ITC) and a dependent task chart (DTC). The ITC includes all the independent tasks and the DTC includes all the dependent tasks. The DTC is further divided into DTC1 and DTC2. The tasks from all the charts are selected for execution based on priority. The method and system solve the scheduling overhead problem during the boot process, by optimizing the scheduling.

Abstract: Described herein is a method and apparatus for generating automatic language bindings. The method includes receiving a request for a first program module in a first language from a second program module in a second language. A binding module is created in the second language in response to the request, where the binding module is generated from debug data of the first program module. The binding module is returned to the second program module. The second program module can then access the functionality of the first program module through use of the functions of the binding module.

Abstract: Methods and systems for creating and rendering skins are described. In one described embodiment skins can be defined as sets of script files, art files, media files, and text files. These files can be used to create new and different skin appearances, layouts and functionalities. The files are organized for use using a hierarchical tag-based data structure, an example of which is an XML data structure. The data structure is processed to provide an object model. The object model can be a scriptable object model that enables script to execute to provide an interactive, dynamic skin that can respond to internal and external events. In one embodiment, a computer architecture used for rendering the skin includes a layout manager that processes an intermediate representation of the XML data structure to provide the scriptable object model. Various components of the scriptable object model can include a script engine for receiving and executing script, and one or more rendering elements.

Abstract: A linker or loader, and associated method, is described, whereby the application of security transformations to object-code modules can be deferred until link or load-time, through, for example, memory relocation, selection from diverse instances of a module, and late-binding of constants. This provides several benefits over conventional source-to-source security transformations. These deferred security transformations can be applied in a very light-weight manner and create many opportunities for diversity in the resulting executable program, enhancing security, while at the same time minimizing the impact on execution performance and correctness, and reducing the complexity of debugging.

Abstract: An extensible three-dimensional (3D) asset plug-in framework is disclosed. In various embodiments, files having different 3D file formats may be processed by respective plug-ins. The plug-ins may be configured to be downloaded and installed, to receive input files describing one or more 3D models and having a respective 3D file format, to read the respective 3D file format, and to generate and return a common 3D description to be previewed and manipulated by an application or an operating system. The different 3D file formats and their respective plug-ins may be proprietary or developed by third parties.

Abstract: A method and apparatus are disclosed to identify the operations/processes performed by one or more virtual machines. In one example method of operation, the system may perform identifying processes currently operating in an operating system and recording process information corresponding to each of the processes in a memory. The method may also include determining a priority for each of the processes currently operating in the operating system and incrementing a current priority of at least one of the processes.

Abstract: In one or more embodiments, a system can configure a physical mobile device via configuring a configuration for an emulator of the physical mobile device. For example, a user (e.g., a customer) can request a physical mobile device, and a system can provide the user with an emulation of the physical mobile device, where the user can configure the emulation of the physical mobile device. In one or more embodiments, the user can be provided with the configuration via at least one of a network and a physical delivery of the physical mobile device, configured with the configuration. In one example, the user can execute an emulation of the physical mobile device configured with the configuration, received via the network. In another example, the physical mobile device can be configured with the configuration, and subsequently, the physical mobile device can be physically delivered to the user.

Abstract: Disclosed are various embodiments for executing multiple applications in a single virtual machine. The classes of an application executing in the virtual machine are traversed to identify non-sharable static fields. Upon identifying a non-sharable static field, mapping data is created that corresponds to the non-sharable static field. During another traversal of the classes of the application, access to the identified non-sharable static field is translated into an access to the mapping data that is associated with the non-sharable static field.

Abstract: An interactive intermediate representation (IR) viewer displays a view of the intermediate representation of client side code during a just-in-time compilation of the client side code in a live environment. The interactive IR viewer allows a developer to request the intermediate representation generated during one or more of the phases of the JIT compilation of the client side code. Modifications may be made to the intermediate representation before executable code is generated. The analysis of the intermediate representation during the live environment provides a developer with insight as to how the executable code is being compiled so that improvements may be made to improve the performance of the client side code.

Abstract: A computer implemented method, system, and computer program product for moving a virtual volume from a first consistency group to a second consistency group in continuous replication without loss of a journal, wherein the volume is being replicated, the method comprising notifying a splitter that the volume is being moved, creating a bookmark, and moving the volume from the first virtual consistency group to the second virtual consistency group.

Abstract: Techniques are disclosed for provisioning a virtual desktop. A VM hosting the desktop may be joined to a domain using offline domain join and customized by modifying contents of a virtual disk of the VM, as per the customization requirements, without powering on the VM. While the VM is powered off, a composer application customizes the VM by applying system and user profile configuration changes and network configuration changes, as well as optionally creating a user data disk and pushing to the VM a script for formatting said disk during the VM's first power-on. In addition, while the VM is powered off, the composer invokes a domain joining tool to join the VM to a domain controller without having to reboot the VM. A snapshot is then taken of the VM, after which the VM is then powered on and the script for formatting the user data disk executes.

Abstract: Systems, methods, and software are described herein for operating a data management system, including a virtual machine agent running within a virtual machine responding to an attach-triggering event, determining selected storage volumes to be attached to the virtual machine based on a request generated by the virtual agent in response to the attach-triggering event, and dynamically attaching the selected storage volumes to the virtual machine.

Abstract: In one embodiment, a method includes coupling a plurality of virtual machines to a plurality of peripheral devices via a central switch where the plurality of virtual machines are running a plurality of virtual desktops. A data packet is received from a virtual machine where the data packet is received in a first format compatible with a virtual desktop being run in the virtual machine. The central switch determines a peripheral device that corresponds to the virtual desktop. Then, the central switch generates a peripheral signal from the data packet that is configured to be sent to the peripheral device. The peripheral signal is in a second format compatible with the peripheral device and different from the first format. The peripheral signal is sent to the peripheral device where the peripheral device can process the peripheral signal for the virtual desktop being run in the virtual machine.

Abstract: A method including downloading a streaming model file and at least one initial execution file from a server via a conventional download protocol without using a specialized streaming protocol. When executed, the initial execution file only partially implements an application. The model file stores information identifying additional portions of the application file to be downloaded from the server. Data is read from the initial execution file, and stored in a local copy of the application file. Then, the application is executed by executing the local copy. Until the entire application file has been downloaded and as the application is executing, the information is read from the model file to identify a next file to download, the next file is downloaded via the conventional download protocol without using a specialized streaming protocol, next data is read from the next file, and the next data is stored in the local copy.

Abstract: Systems and methods for deferred assignment of devices in virtual machine migration. An example method comprises: starting, by a processing device of a first host computer system, a virtual machine being migrated from a second host computer system in a post-copy migration mode; receiving a request to associate an input/output (I/O) device with the virtual machine; and responsive to receiving, from the second host computer system, one or more memory pages comprised by a memory buffer associated with the I/O device, performing at least one of: associating an identifier of the I/O device with the memory buffer or allowing the virtual machine to access the I/O device.

Abstract: For managing a pool of virtual computer systems, master status and a rebasing task are assigned to at least one virtual computer system of the pool. A non-reserved status is assigned to virtual computer systems of the pool that are not assigned tasks. A virtual computer system of the pool is selected to respond to a rebasing request. The selecting includes selecting one of the at least one virtual computer system that currently has a master status and that currently has a processing load less than a predetermined threshold and, when no virtual computer system of the pool currently has a master status and a processing load less than the predetermined threshold, selecting a non-reserved one of the virtual computer systems to perform rebasing for the request and changing the non-reserved status of the selected, non-reserved one of the virtual computer systems to master status.

Abstract: A cloud manager monitors available resources on host computer systems, including a number of hardware threads supported by CPUs on the host computer systems. The cloud manager receives a request to provision a virtual machine (VM) that includes a hardware multithreading parameter that specifies the amount of hardware multithreading required on the host computer system. The cloud manager then selects a host computer system for the VM taking the hardware multithreading parameter into consideration.

Abstract: Embodiments of the present invention provide efficient systems and methods for scaling past the Java Virtual Machine (JVM) thread limit in a Java Virtual Machine. Embodiments of the present invention can be used to ensure that a received workload is executed, even if the workload is greater than a JVM thread limit of the system, by spawning a reduced number of threads from a main process, in order to provide enough resources for the effective execution of a received workload.

Abstract: A processing device implementing unbounded transactional memory with forward progress guarantees using a hardware global lock is disclosed. A processing device of the disclosure includes a hardware transactional memory (HTM) hardware contention manager to cause a bounded transaction to be translated to an unbounded transaction, the unbounded transaction to acquire a global hardware lock for the unbounded transaction, the global hardware lock read by bounded transactions that abort when the global hardware lock is taken. The processing device further includes an execution unit communicably coupled to the HTM hardware contention manager to execute instructions of the unbounded transaction without speculation, the unbounded transaction to release the global hardware lock upon completion of execution of the instructions.

Abstract: A method includes, with a hypervisor, detecting that a virtual processor of a virtual machine has accessed a designated address, the designated address being associated with a time value, causing the virtual processor to enter a halt state for a period of time, and causing the virtual processor to exit the halt state after a period of time has passed, the period of time being based on the time value.

Abstract: A method includes a processor for determining a life cycle of a first performance of a task flow for a telecommunication service order, determining that a performance of a first task within the first performance of the task flow has exceeded a threshold processing time, and determining that there is a problem with a first centralized system component in response to determining that the performance of the first task within the first performance of the task flow has exceeded the threshold processing time. The method may further include identifying the centralized system component for servicing when it is determined that there is a problem with the centralized system component.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for memory requests by a virtual machine. One of the methods includes initiating a migration process to move an application executing on a first device from the first device to a second device by copying pages of data, stored in a memory of the first device and used for the execution of the application, from the first device to the second device while continuing to execute the application on the first device, updating, by the first device, one or more bytes in at least one of the pages of data in response to executing the application on the first device during the migration process, stopping execution of the application on the first device, and copying the updated bytes from the first device to the second device to cause the second device to continue execution of the application.

Abstract: A data processing system (100) includes a main list (126) of tasks, main scheduling scheme, a starvation list (128) of tasks, and a secondary scheduling scheme. A method identifies tasks in the main list that are potentially-starving tasks and places the potentially-starving tasks in the starvation list. A starvation monitor (130) controls starvation of tasks in the system by determining when to use the secondary scheduling scheme to schedule, for execution on a CPU (132), a highest priority task in the starvation list prior to scheduling, pursuant to the main scheduling scheme, other tasks in the main list. The starvation monitor determines a number of times that a task in the main list is pre-empted, by other tasks in the main list, from being scheduled for execution on the CPU. A counter (131) is incremented each occasion that any task not in the starvation list is executed on the CPU.

Abstract: Burst throttling methods may be used manage computing resources of a data storage service. Tokens may represent I/O operations executed by a customer of the data storage service. A global token bucket may contain a set of tokens representing the overall I/O operation capacity of the data storage service. Additionally, a work token bucket may contain a set of tokens for a given logical volume maintained by the data storage service. When I/O requests are received the data storage service may dynamically determine an amount of tokens to be removed from the global token bucket and/or work token bucket for each received request. Furthermore, if there is sufficient capacity the data storage service may charge a reduced number of tokens to the work token bucket.

Abstract: Burst throttling methods may be used manage computing resources of a data storage service. Tokens may represent I/O operations executed by a customer of the data storage service. A global token bucket may contain a set of tokens representing the overall I/O operation capacity of the data storage service. Additionally, a work token bucket may contain a set of tokens for a given logical volume maintained by the data storage service. When I/O request are received the data storage service may determine if the I/O request is a member of a sequence and removed a reduced number for tokens from the work token bucket as a result. Furthermore, if there is sufficient capacity the data storage service may charge a reduced number of tokens to the work token bucket.

Abstract: A method is provided for memory releasing. The method includes obtaining a first memory space value of a terminal system, where the first memory space represents a size of current idle memory space on the terminal system. The method also includes requesting a memory space whose size equals to a second memory space value from the terminal system, where the second memory space value is greater than the first memory space value. Further, the method includes releasing occupied memory after the terminal system receives a memory space request and detects that the second memory space value is greater than the first memory space value. The method includes confirming allocation of the memory space whose size equals to the second memory space value. The method includes releasing the memory space whose size equals to the second memory space value as the idle memory space after receiving allocation confirmation of the memory space of the terminal system.

Abstract: A resource allocation system begins with an ordered plan for matching requests to resources that is sorted by priority. The resource allocation system optimizes the plan by determining those requests in the plan that will fail if performed. The resource allocation system removes or defers the determined requests. In addition, when a request that is performed fails, the resource allocation system may remove requests that require similar resources from the plan. Moreover, when resources are released by a request, the resource allocation system may place the resources in a temporary holding area until the resource allocation returns to the top of the ordered plan so that lower priority requests that are lower in the plan do not take resources that are needed by waiting higher priority requests higher in the plan.

Abstract: A multicore adaptive scheduler of tasks in an ARINC 653-compliant avionics system allocates flight critical tasks execution time equivalent to their worst case execution time and allocates quality-driven tasks minimum execution time equivalent to their minimum completion time. The scheduler may also offset the start time of a task or define an upper bound for completion time of a quality-driven task. The scheduler generates and executes partition schedules of tasks, reallocating execution time unused by completed tasks and reallocating execution time from interrupt handlers to tasks preempted by interrupts. The scheduler may also analyze the viability of a generated schedule. The scheduler uses rate limiting and flow control techniques to ensure a predictable amount of execution time to be reallocated for interrupt handling.

Abstract: Systems and methods are provided for automatically provisioning resources based on application characteristics. In accordance with an embodiment, a system can include a computer, including a computer readable medium and processor, and a template engine, executing on the computer. The template engine is configured to receive applications and associated metadata. The system can also include a virtualized environment, and a plurality of templates, each defining a different resource available within the virtualized environment. When the template engine receives an application and associated metadata, the template engine determines resource requirements for the application based on the associated metadata, compares the resource requirements with the plurality of templates, identifies appropriate templates for the resource requirements, and provisions resources in the virtualized environment using the appropriate templates.

Abstract: A system, method, and computer program product are provided for receiving an incoming data stream. The system comprises a multi-core processor with a memory unit that is configured to include a circular queue that receives a data stream. The circular queue is divided into a plurality of sub-queues determined as a multiple of the number of processing cores, and each sub-queue is assigned to one processing core such that as data is received into a region covered by a particular sub-queue, the processing core assigned to the particular sub-queue processes the data. The system is also configured to update a head pointer and a tail pointer of the circular queue. The head pointer is updated as data is received into the circular queue and the tail pointer is updated by a particular processing core as it processes data in its assigned sub-queue.

Abstract: Software that uses machine logic based algorithms to help determine and/or prioritize an application programming interface's (API) desirability to a user based on how closely the API's terms of service (ToS) meet the users' ToS preferences. The software performs the following steps: (i) receiving a set of API ToS feature information that includes identifying information for at least one API and respectively associated ToS features for each identified API; (ii) receiving ToS preference information that relates to ToS related preferences for a user; and (iii) evaluating a strength of a match between each respective API identified in the API ToS feature information set and the ToS preference information to yield a match value for each API identified in the API ToS feature information set.