Abstract: Autonomous media version testing is described. A method may include testing, by a processing device of a server and without human interaction, a plurality of versions of a game, each having a different set of test conditions, using information received from play of the plurality of versions of the game after a first game move has been made in the game. The method may also include determining, by the processing device and without human interaction, which of the plurality of versions of the game to publicly release based on the testing.

Abstract: A network-based testing method and service integrated with a tool that publishes one or more tagged test cases with tags being executable to reproduce a sequence of events for a system under test, SUT, caused by an original test case. The method is performed in a network and is intended for testing software or hardware by first creating an original test case for a system under test, SUT, and performing a sequence of events for the original test case for testing it. The tested case is stored and information of the performed sequence of events is tagged to the tested case. The tagged test case is then sent to a service that publishes tagged test cases. The service publishes the tagged case in a way to be reproduced via the service.

Abstract: In the data storage system the storage area network performs XOR operations on incoming data for parity generation without buffering data through a centralized RAID engine or processor. The hardware for calculating the XOR data is distributed to incrementally calculate data parity in parallel across each data channel and may be implemented as a set of FPGAs with low bandwidths to efficiently scale as the amount of storage memory increases. A host adaptively appoints data storage controllers in the storage area network to perform XOR parity operations on data passing therethrough. The system provides data migration and parity generation in a simple and effective matter and attains a reduction in cost and power consumption.

Abstract: A memory storage system is that includes a memory element having a memory address for a physical memory. A memory controller receives a command for accessing the memory element using a program-generated address and dynamically transforms the program-generated address into the memory address for the physical memory using a rotation module and configuration information. A data word accessed by the physical address is then provided to a set of arithmetic logic units (ALUs) where multiple computations are performed simultaneously so as top reduce program execution time and energy. The configuration information provided to the rotation unit configures the set of ALUs.

Abstract: A storage system receives an anticipatory write command corresponding to a potential subsequent write command to be received by the storage system, wherein the anticipatory write command indicates an anticipated region of logical address space that may be written to by the potential subsequent write command. The storage system determines that physical storage is not allocated to the anticipated region of logical address space. The storage system allocates physical storage to the anticipated region of logical address space from a pool of available storage managed by the storage system. The storage system creates an association between the anticipated region of logical address space and the allocated physical storage in a virtual-to-physical mapping.

Abstract: A system and method for providing a print formatted string wherein a format object is created for a format string a format string having a set of format specifiers, an amount of memory to allocate to a string buffer for the format object is determined, and the determined amount of memory is allocated to the string buffer. For each set of parameter values received with the format object, where each parameter value corresponds to a format specifier in the format string, a determination is made whether the determined amount of memory for the string buffer is sufficient to hold the set of input parameter values in accordance with the format string. If the determined amount of memory is insufficient, an amount of memory sufficient for the set of input parameter values in accordance with the format string is re-determined, and the string buffer is reallocated to the re-determined amount of memory.

Abstract: A data storage device includes a memory and a controller. A method may be performed at the data storage device. The method includes receiving a request to write data, generating a signature of the data, and searching a signature table to determine if the generated signature is in the signature table. The signature table includes at least one signature table entry that includes a signature of stored data and a physical address of the stored data.

Abstract: Device for selecting a level for at least one read voltage for reading data stored in a multi-level memory device. The multi-level memory device includes a plurality of memory blocks, in which each of the memory blocks includes a plurality of word lines, each of the word lines being allocated to a plurality of memory pages and being indexed by a word line index. The device includes a first mapping unit for mapping each of the word line indices to one bin label, in which the number of bin labels is smaller than the number of word lines, and a second mapping unit for mapping each of the bin labels to a voltage information being indicative for at least one read voltage, in which the level for the at least one read voltage for reading data is selectable for each word line based on the respective word line index.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable heuristic aware garbage collection in storage systems (e.g., non-volatile data storage systems using one or more flash memory devices). In one aspect, a time parameter (e.g., dwell time) and/or heuristics (e.g., error count, error rate, number of reads, number of times programmed, etc.) are used in a garbage collection scheme. For example, in some implementations, the method of garbage collection for a storage medium in a storage system includes (1) determining a time parameter for a block in the storage medium, and (2) in accordance with a determination that the time parameter for the block is greater than a first threshold time, enabling garbage collection of the block.

Abstract: A method for data transfer includes receiving in an operating system of a host computer an instruction initiated by a user application running on the host processor identifying a page of virtual memory of the host computer that is to be used in receiving data in a message that is to be transmitted over a network to the host computer but has not yet been received by the host computer. In response to the instruction, the page is loaded into the memory, and upon receiving the message, the data are written to the loaded page.

Abstract: A method and apparatus for controlling a frequency of CMI are disclosed. The method may include classifying request types into one or more request groups, wherein each of the request types is a type of CMI request. A number of clock cycles that is sufficient to process a request in each request group may be assigned, and requests that are made to CMI may be monitored with one or more performance counters. A number of requests that occur during a length of time in each request group may be determined, and a frequency of the CMI may be periodically adjusted based upon the number of requests occurring per second in each request group and the assigned number of clock cycles per request for each request group.

Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty.

Abstract: A computing system performs an environment-aware cache flushing method. When a processor in the system receives a signal to flush at least a portion of the caches to the system memory, the processor determines a flushing mechanism among multiple candidate flushing mechanisms. The processor also determines one or more of the active processors in the system for performing the flushing mechanism. The determinations are based on the extent of flushing indicated in the signal and a runtime environment that includes the number of active processors. The system then flushes the caches to the system memory according to the flushing mechanism.

Abstract: Techniques are provided for using bitmaps to indicate which items, in a set of items, are invalid. The bitmaps include an “active” bitmap and one or more “temporal clones”. The active bitmap indicates which items in the set are currently valid. The temporal clones are outdated versions of the active bitmap that indicate which items in the set were invalid at previously points in time. Temporal clones may not be very different from each other. Therefore, temporal clones may be efficiently compressed. For example, a bitmap may be selected as a “base bitmap”, and one or more other bitmaps are encoded using delta encoding. Run length encoding may then be applied to further compress the bitmap information. These bitmaps may then be used to determine which items are valid relative to past-version requests.

Abstract: A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store.

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract: Attributes of access requests can be used to distinguish one set of access requests from another set of access requests. The prefetcher can determine a pattern for each set of access requests and then prefetch cache lines accordingly. In an embodiment in which there are multiple caches, a prefetcher can determine a destination for prefetched cache lines associated with a respective set of access requests. For example, the prefetcher can prefetch one set of cache lines into one cache, and another set of cache lines into another cache. Also, the prefetcher can determine a prefetch distance for each set of access requests. For example, the prefetch distances for the sets of access requests can be different.

Abstract: Method and apparatus for tracking a prefetch list of a list prefetcher associated with a computer program in the event the list prefetcher cannot track the computer program. During a first execution of a computer program, the computer program outputs checkpoint indications. Also during the first execution of the computer program, a list prefetcher builds a prefetch list for subsequent executions of the computer program. As the computer program executes for the first time, the list prefetcher associates each checkpoint indication with a location in the building prefetch list. Upon subsequent executions of the computer program, if the list prefetcher cannot track the prefetch list to the computer program, the list prefetcher waits until the computer program outputs the next checkpoint indication. The list prefetcher is then able to jump to the location of the prefetch list associated with the checkpoint indication.

Abstract: Described herein are systems and methods to prevent a controller in a DDIO (data direct input output) system from shifting currently-required data out of a cache memory. In one embodiment, a compute element disables caching of some specific addresses in a non-cache memory, but still enables caching of other addresses in the non-cache memory, thereby practically disabling the DDIO system, so that data sets not currently needed are placed in the addresses in the non-cache memory which are not cached. As a result, currently-required data are not shifted out of cache memory. The compute element then determines that the data sets, which formerly avoided being cached, are now required. The system therefore copies the data sets that are now required from addresses in non-cache memory not accessible to cache memory, to addresses in non-cache memory accessible to cache memory, thereby allowing the caching and processing of such data sets.

Abstract: Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed.

Abstract: A buffer memory management method, a memory control circuit unit and a memory storage device are provided. The buffer memory management method includes allocating a mapping table zone having a first zone and a second zone in the buffer memory, and temporarily storing a plurality of logical address-physical address mapping tables into the first zone and the second zone, and receiving a first write command which indicates writing first data into a first logical address. A first logical address-physical address mapping table to which the first logical address belongs is temporarily stored into a first buffer unit in the second zone. The method also includes updating the first logical address-physical address mapping table, moving the updated first logical address-physical address mapping table into a second buffer unit in the first zone, and marking the second buffer unit as a dirty status.

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache.

Abstract: In some embodiments, a memory corruption prevention process includes detecting a memory instruction of a program, where the memory instruction specifies a virtual memory address of data. The memory corruption prevention process further includes accessing, in response to the memory instruction, a translation lookaside buffer (TLB) using at least a portion of the virtual memory address. The memory corruption prevention process further includes, in response to accessing the TLB, obtaining a physical memory address corresponding to the virtual memory address, where the physical memory address corresponds to the data. The memory corruption prevention process further includes, in response to accessing the TLB, obtaining an authentication value corresponding to the physical memory address. The memory corruption prevention process further includes determining, using the authentication value, whether the memory instruction is authorized to proceed.

Abstract: A method for controlling access to a memory of a computer system configured with at least one logical partition may include receiving a first request to map a first page of the memory, the request identifying a first requester. A first logical partition associated with the first page may be determined. It may be determined that an attribute of the first logical partition limits access to individual pages of the first logical partition to a single requester, and that the first page is available to be mapped to a requester. The first page may be mapped to the first requester and a flag indicating that the first page is unavailable for an additional mapping may be set. The first request may be from a device driver on behalf of an input/output adapter, as the first requester, to use the first page in a direct memory access transfer.

Abstract: A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.

Abstract: The configuration of a cache is adjusted within a computer system that includes at least one entity that submits a stream of references, each reference corresponding to a location identifier corresponding to data storage locations in a storage system. The reference stream is spatially sampled using reference hashing. Cache utility values are determined for each of a plurality of caching simulations and an optimal configuration is selected based on the results of the simulations.

Abstract: Systems and methods for managing records stored in a storage cache are provided. A cache index is created and maintained to track where records are stored in buckets in the storage cache. The cache index maps the memory locations of the cached records to the buckets in the cache storage and can be quickly traversed by a metadata manager to determine whether a requested record can be retrieved from the cache storage. Bucket addresses stored in the cache index include a generation number of the bucket that is used to determine whether the cached record is stale. The generation number allows a bucket manager to evict buckets in the cache without having to update the bucket addresses stored in the cache index. In an alternative embodiment, non-contiguous portions of computing system working memory are used to cache data instead of a dedicated storage cache.

Abstract: Security of information—both code and data—stored in a computer's system memory is provided by an agent loaded into and at run time resident in a CPU cache. Memory writes from the CPU are encrypted by the agent before writing and reads into the CPU are decrypted by the agent before they reach the CPU. The cache-resident agent also optionally validates the encrypted information stored in the system memory. Support for I/O devices and cache protection from unsafe DMA of the cache by devices is also provided.

Abstract: A method, system, and computer program product are provided for protecting state data of computer system code. The computer system code may be operating system code, subsystem code or application code and the item of state data is not expected to change within the execution of the computer system code. The method includes: creating or modifying an item of state data having a field value and being stored in memory for access by computer system code; registering an item of state data for protection; preserving the field value of the item of state data in a form inaccessible to third party software; validating the field value of the item of state data by comparing a current field value with the preserved field value to determine if the field value has been modified; and, if the field value has been modified, taking appropriate action.

Abstract: A data processing system (2) includes memory protection circuitry (10) storing access control data for controlling accesses to data at memory addresses within a main memory (16). An access control cache (14) may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry (10) to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache (14) is storing access control data for a memory access request, then the access control data stored within the access control cache (14) is used in place of access control data retrieved form the memory protection circuitry (10).

Abstract: A method and apparatus for transmitting data in an Android platform based terminal device are provided. In the method, when the terminal device establishes a connection for data transmission with another device over a USB, the terminal device transmits data in an internal storage of the terminal device to the another device based upon a file transfer protocol and receives and writes into the internal storage data transmitted from the another device based upon the file transfer protocol; and the terminal device transmits data in an external storage of the terminal device to the another device in a UMS mode and receives and writes into the external storage data transmitted from the another device in the UMS mode.

Abstract: A computer, having: a first OS to which a first processor core group is allocated; and a virtualization module to which a second processor core group is allocated, wherein a virtualization module registers interrupt handler processing for resetting the second processor core group, wherein a first OS has: a monitoring module for monitoring the virtualization module; and an interrupt control module for obtaining identifiers of the second processor core group at a time of booting of the virtualization module, and, when the monitoring module determines to reboot the virtualization module, issuing resetting interrupt to the processor cores of the second processor core group that are associated with the kept identifiers, wherein the second processor core group receives the resetting interrupt and executes the interrupt handler processing to reset its own processor cores, wherein the interrupt control module issues startup interrupt to the second processor core group.

Abstract: An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.

Abstract: Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.

Abstract: An I/O device sharing system characterized by comprising: an I/O device (50) shared by a plurality of hosts (20-1 to 20-N); a system manager (10) which sets the I/O device (50); a virtual bridge (40) which virtualizes the I/O device (50); and a network (3) which connects the I/O device (50), the system manager (10), the plurality of hosts (20-1 to 20-N) and the virtual bridge (40) to each other, wherein the virtual bridge (40) includes a connection virtualization unit (41) by which it is detected that an address setting of a plurality of virtual functions provided in the I/O device (50) that is set by the system manager (10) is performed, the virtual function is enabled, or both of them are performed and each host is permitted to access each virtual function.

Abstract: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.

Abstract: A connection interface switching device for multiple portable devices provides a communication channel between an I/O peripheral set and for a plurality of portable devices which are bundled with a default control program installed in the portable devices, and switches among the portable devices to establish a communication channel selected between one portable device and the I/O peripheral set according to a switch instruction generated by the default control program of the portable device. The connection interface switching device includes plural I/O ports, a controller, a memory module, a storage module and an I/O peripheral port, and an origin of the computer signal is controlled and switched to achieve the effect of sharing the same I/O peripheral set among multiple portable devices through the communication channel.

Abstract: Methods, systems, and computer program products for notifying a virtual machine of an expander coupled to a first virtual root bus, probing the expander to detect an additional root bus, probing the additional root bus to detect a second device, and assigning the second device to a second virtual root bus of the virtual machine.

Abstract: Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include or be coupled to a results buffer, which may have a plurality of records, a write-control module configured to write data relevant to search results in the plurality of records, and a read control module configured to read data from the plurality of records.

Abstract: One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One advantage of the disclosed embodiments is providing flexibility for engineers who develop the devices while also reducing the likelihood that a third party can counterfeit the device.

Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

Abstract: A system and method for mounting multiple devices on an SLR enable information handling system is disclosed herein. A drive-letter may be assigned to a first user session in a first user session namespace only. A second user may have access to the same drive-letter as the mounting of drive-letters is specific to each specific user session and not the global namespace. A symbolic link is created for each assigned drive-letter and the corresponding drive-letter in the global namespace is deleted allowing for more than the standard mounting of only twenty-six different devices.

Abstract: A physical layer network interface module (PHY-NIM) adaptation system provides a PHY-NIM device and an attachable media access control (MAC) device. The PHY-NIM device interconnects with the attachable MAC device and the attachable MAC device interconnects to a network appliance where the network appliance does not have at least one of an internal network switch and a MAC device in a southbridge input/output (I/O) interface chip of the network appliance. The PHY-NIM device interconnects directly to the network appliance without the attachable MAC device where the network appliance has at least one of the internal network switch and the MAC device in the southbridge I/O interface chip of the network appliance.

Abstract: An Ethernet/Fibre Channel conversion system includes a chassis having a first end and a second end that is located opposite the chassis from the first end. An Ethernet interface is located on the first end and is configured to directly mate with an Ethernet port on an Ethernet device. A Fibre Channel interface is located on the second end. An Ethernet/Fibre Channel conversion engine is housed in the chassis and configured to receive Ethernet protocol signals through the Ethernet interface, convert the Ethernet protocol signals to Fibre Channel protocol signals, and send the Fibre Channel protocol signals through the Fibre Channel interface. The Ethernet/Fibre Channel conversion engine is also configured to receive Fibre channel protocol signals from the Fibre Channel IHS through the Fibre Channel interface, convert the Fibre channel protocol signals to Ethernet protocol signals, and send the Ethernet protocol signals through the Ethernet interface.

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

Abstract: A method for transmitting data over a single-wire bus wherein a first communication channel is defined by pulses of different durations according to the state of the transmitted bit and depending on a reference duration, and a second communication channel is defined by the reference duration.

Abstract: Systems and techniques relating to processing of network communications include, according to an aspect, a network device that includes circuitry configured to receive value bits selected from a group consisting of a zero bit, a one bit, and a don't care bit; and circuitry configured to store encoded representations of the value bits for use in network packet routing, wherein the encoded representations are position bits selected from a group consisting of a zero bit and a one bit; wherein the circuitry configured to store includes a first memory location and a second memory location that each eliminate a different combination of the value bits from being available for storage respectively in the first memory location and the second memory location.

Abstract: Techniques for managing computing resources are disclosed. In one particular embodiment, the techniques may be realized as a method for managing computing resources including receiving a desired resource configuration, determining currently available resources, determining, via at least one computer processor, whether the currently available resources satisfy the desired resource configuration, and determining a resource implementation based on the determination of whether the currently available resources satisfy the desired resource configuration.

Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

Abstract: Some embodiments provide a method that efficiently designs a document. The method provides the user with a selection of templates, each with a default configuration for content. After the user selects a template, the method provides the user with a selection of page designs to add to the selected template. When the user selects one of the page designs, the method adds the page design to a document that it presents to the user based on the selected template. Some embodiments provide methods for modifying default content of template documents that have several default text fields. When a user selects a default text field, the method of some embodiments selects the entire default text field for immediate editing by the user.