Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.

Abstract: A computer device including a node having a storage device having a plurality of first internal address spaces, a cache memory, and a processor may be provided. The processor may provide a virtual volume. The virtual volume may have a plurality of virtual address spaces including first virtual address spaces corresponding to the plurality of first internal address spaces. The processor may cache data of a virtual address space in a first cache space of the cache memory by associating the virtual address space with the first cache space. Further, the processor may cache data of a first internal address space of the first internal address spaces in a second cache space of the cache memory by associating the first internal address space with the second cache space.

Abstract: A method and system for implementing a directory structure of a host system are disclosed. The method includes: multiple basic computing units interconnecting via a high speed internetwork to construct a system computing unit set; wherein each basic computing unit comprises a protocol processing chip and a system resource management firmware; and dividing a part implementing a logic function in the protocol processing chip into a static part and a dynamic part in advance, wherein the dynamic part can be reconstructed; constructing a system cache directory storage architecture through the dynamic part; and the system resource management firmware managing system resources by means of configuration.

Abstract: Techniques are disclosed for identifying data streams in a processor that are likely to benefit from data prefetching. A prefetcher receives at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams. The prefetcher assigns a confidence level to the the first request based on an amount of confirmations observed in the stream. The request is in a confident state if the confidence level exceeds a specified value. The first request is in a non-confident state if the confidence level does not exceed the specified value. Doing so allows a memory controller to determine whether to drop the at least the first request based on the confidence level and a memory resource utilization threshold.

Abstract: Provided are a computer program product, system, and method to allocate a segment of a buffer to each of a plurality of threads to use for writing data. Each of a plurality of threads are assigned to one of a plurality of segments in a buffer, wherein the threads write to the segment to which they are assigned. A free segment list indicates segments which are not assigned to one of the threads. In response to one of the segments assigned to one of the threads becoming a full segment having less than a threshold amount of free space, indicating the full segment assigned to the thread in the free segment list and assigning one of the segments in the free segment list to the thread different from the full segment.

Abstract: A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted in the global memory device. Memory access traces relating to executed tasks are accessed from the signal list. Memory locations accessed in the global memory device from the access traces are identified. A correlation value for each pair of memory locations accessed in the global memory device is determined. Correlation values of the pairs of memory locations are determined, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations. Accessed memory locations within the global memory device are reordered as a function of the determined correlation values. An executable file accessing the global memory device is modified.

Abstract: In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.

Abstract: Systems, methods, and software described herein facilitate an enhanced service architecture for large-scale data processing. In one implementation, a method of providing data to a large-scale data processing architecture includes identifying a data request from a container in a plurality of containers executing on a host system, wherein the plurality of containers each run an instance of a large-scale processing framework. The method further provides identifying a storage repository for the data request, and accessing data associated with the data request from the storage repository. The method also includes caching the data in a portion of a cache memory on the host system allocated to the container, wherein the cache memory comprises a plurality of portions each allocated to one of the plurality of containers.

Abstract: A semiconductor device includes a memory for storing a plurality of instructions therein, an instruction queue which temporarily stores the instructions fetched from the memory therein, a central processing unit which executes the instruction supplied from the instruction queue, an instruction cache which stores therein the instructions executed in the past by the central processing unit, and a control circuit which controls fetching of each instruction. When the central processing unit executes a branch instruction, and an instruction of a branch destination is being in the instruction cache and an instruction following the instruction of the branch destination is stored in the instruction queue, the control circuit causes the instruction queue to fetch the instruction of the branch destination from the instruction cache and causes the instruction queue not to fetch the instruction following the instruction of the branch destination.

Abstract: In a method to provide scalable and distributed address mapping in a storage device, a host command that specifies an operation to be performed and a logical address corresponding to a portion of memory within the storage device is received or accessed. A storage controller of the storage device maps the specified logical address to a first subset of a physical address, using a first address translation table, and identifies an NVM module of the plurality of NVM modules, in accordance with the first subset of a physical address. The method further includes, at the identified NVM module, mapping the specified logical address to a second subset of the physical address, using a second address translation table, identifying the portion of non-volatile memory within the identified NVM module corresponding to the specified logical address, and executing the specified operation on the portion of memory in the identified NVM module.

Abstract: A computer program product for optimizing page table manipulations is provided and includes a computer readable storage medium having program instructions that are readable and executable by a processing circuit to cause the processing circuit to create and maintain a translation table with a translation look-aside buffer (TLB) disposed to cache priority translations, update the translation table upon de-registration of a DMA address, allocate entries in the translation table from low to high memory addresses during memory registration, maintain a cursor for identifying where to search for available entries upon performance of a new registration, advance the cursor from entry-to-entry in the translation table and wrap the cursor from an end of the translation table to a beginning of the translation table and issue a synchronous TLB invalidation instruction to invalidate the TLB upon at least one wrapping and an entry being identified and updated.

Abstract: A system and methods for migrating a virtual machine (VM). In one embodiment, a hypervisor receives a request to migrate the contents of a memory of a source VM in a first physical memory area to a destination VM in a second physical memory area, where the first and second physical memory areas are disjoint. The hypervisor executes the destination VM in response to the request, and detects an access of a page of memory of the destination VM. The hypervisor determines, in view of a data structure maintained by a guest operating system executing in the destination VM, that a first page of a memory of the source VM in the first physical memory area is currently in use by the destination VM.

Abstract: This technology relates to a memory system for processing data into a memory device and an operating method of the same. The memory system may include a memory device comprising a plurality of memory blocks, each memory block comprising a plurality of pages each page having a plurality of memory cells coupled to a plurality of word lines, the memory device being suitable for storing data requested by a host, and a controller suitable for programming data corresponding to a first write command received from the host into a first memory block of the memory blocks, receiving a second write command for the data programmed into the first memory block from the host, performing an update program on the data programmed into the first memory block into the memory blocks, and generating a map list for the first memory block according to the update program.

Abstract: A memory system includes a memory device including first and second storage regions, each comprising a plurality of memory blocks and a controller suitable for selecting a first mode or a second mode based on a method for accessing data stored in the memory device and mapping a logical address of the data into a physical address of the first storage region in the first mode and into a physical address of the second storage region in the second mode.

Abstract: A data storage device utilized for storing at least one data includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks has a different respective physical address. The controller is coupled to the memory for mapping the physical addresses to a plurality of logical addresses. After the controller receives a conversion-requesting instruction, it converts a specific logical address from being mapped to a first physical address to being mapped to a second physical address.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.

Abstract: Method and apparatus for direct memory access of dynamically allocated memory. The apparatus includes: a state receiving module operable to receive a reallocation state of a dynamically allocated memory; an address receiving module operable to receive a dynamic address of a data segment stored in the dynamically allocated memory; a data access module operable to access the dynamic address via a direct memory access (DMA) protocol; and a determining module operable to determine whether a reallocation state received before access to the dynamic address is identical to a reallocation state received after access to the dynamic address. Also provided, a method for verification of data accessed from a dynamically allocated memory and a method and apparatus for allowing a server to provide access to data from a dynamically allocated memory by a client device.

Abstract: Methods and systems are provided for accessing data stored in a memory. An example system may comprise a memory and one or more control circuits for managing access to the memory. The memory may comprise a first portion for storing a plurality of data items, and a second portion, distinct from the first portion, for storing access related information. The access related information may comprise a plurality of access entries, with each access entry corresponding to a particular respective data item. In response to request for a particular data item, the one or more control circuits may search for a match in the access related information access, and may provide access to a data item in the first portion of the memory, corresponding to the requested data item, only in response to detecting a match in the plurality of access entries, based on item related information provided in the request.

Abstract: A memory, a data processing system comprising a memory, a method of operating a memory and a memory compiler apparatus and method of memory compilation are provided, which relate to a memory comprising data storage circuitry to store data values at data locations. Addressing circuitry is provided to access the data value at a storage location in dependence on a received address and readout circuitry to provide an output value in dependence on the accessed data value. The memory further comprises scrambling circuitry to select at least one of: a mapping between the address and the storage location; and a mapping between the data value and the output value, in dependence on a received scrambling value. The mapping between the address and the storage location and/or the data value and the output value can thus be easily and rapidly changed.

Abstract: A system and method for deterring malicious network attacks. The system and method is configured to execute instructions on at least one of the processors to generate a plurality of random blocks of data; generate a first XOR result by using the XOR function with the plurality of random blocks of data as the XOR function inputs; generate a tail value by using the XOR function with the first XOR result and a random encryption key as the XOR function inputs; encrypt a designated file using the random encryption key; write the plurality of random blocks and tail value to at least one storage medium; and write the encrypted designated file to at least one storage medium.

Abstract: A hypervisor receives, from a guest virtual machine, a request to disable access to a memory range. The hypervisor disables access to the memory range. The hypervisor detects a prohibited access attempt. The prohibited access attempt is an access attempt to the memory range. Responsive to detecting the prohibited access attempt, the hypervisor stops the guest virtual machine. The hypervisor receives a request to reboot the guest virtual machine. The hypervisor reboots the guest virtual machine. Responsive to rebooting the guest virtual machine, the hypervisor enables access to the memory range.

Abstract: Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation specifying both a user key and a version identifier, the storage system may permanently delete the specified version of an object having the specified key. In response to a delete operation specifying a user key, but not a version identifier, the storage system may create a delete marker object that does not contain object data, and may generate a new version identifier for the delete marker. The delete marker may be stored as the latest object version of the user key, and may be addressable in the storage system using a composite key comprising the user key and the new version identifier. Subsequent attempts to retrieve the user key without specifying a version identifier may return an error, although the object was not actually deleted.

Abstract: A shared program memory and related components configured to distribute data from a memory block to multiple processors at the same time. An arbiter determines what processors are requesting data from the same memory locations. Data from that memory location is then accessed and sent to the requesting processors so that the data arrives at about the same time to each processor, for example, during the same clock cycle. Such distribution is made possible using a configuration such as a shared data bus with corresponding valid bits for each register or using a multicaster and separate data busses for each processor.

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.

Abstract: Various embodiments for protecting keyboard data inputted by a user in a computer having a keyboard hardware are disclosed. According to one exemplary embodiment, a method for protecting keyboard data, where the keyboard hardware comprises an I/O port having an input buffer and an output buffer, includes: receiving scan code data based on keyboard data inputted by the user, wherein the scan code data are latched in the output buffer of the I/O port; executing an interrupt routine to fetch the scan code data from the output buffer to a CPU of the computer, wherein the latched scan code data remains in the output buffer after the latched scan code data are read from the output buffer; transmitting a control command to the keyboard hardware through the input buffer of the I/O port; and receiving from the keyboard hardware a response signal generated in response to the control command, wherein the keyboard hardware is configured to transmit the response signal to the output buffer of the I/O port.

Abstract: A system is described that includes a data bus communicatively coupled to a host processor, a graphics processing unit (GPU), and a data storage unit. The GPU is configured to receive instructions from the host processor to perform direct communication over the data bus with the data storage unit. Responsive to receiving instructions to communicate directly with the data storage unit, the GPU will initiate a direct communication channel over the data bus. Once established, a direct communications channel allows the data storage unit and the GPU to directly exchange information and bypass the host CPU and system memory.

Abstract: A direct memory access (DMA) system is implemented in an electronic device that communicates with a host device via a communication bus, and includes an available descriptor notification circuit and a DMA controller. The available descriptor notification circuit indicates whether at least one valid descriptor is available in the host device. The available descriptor notification circuit is set by at least the host device. The at least one valid descriptor records DMA data transfer control information. The DMA controller fetches the at least one valid descriptor from the host device when the available descriptor notification circuit indicates that the at least one valid descriptor is available in the host device, and refers to the at least one valid descriptor fetched from the host device to perform a DMA data transfer between the electronic device and the host device.

Abstract: A method for storage includes storing multiple memory pages in a memory of a first compute node. Using a second compute node that communicates with the first compute node over a communication network, duplicate memory pages are identified among the memory pages stored in the memory of the first compute node by directly accessing the memory of the first compute node. One or more of the identified duplicate memory pages are evicted from the first compute node. The identification of duplicate pages is performed by a node selected responsive to available processing or bandwidth resources.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.

Abstract: Orthogonal differential vector signaling codes are described which support encoded subchannels allowing transport of distinct data and clocking signals over the same transport medium. Embodiments are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Abstract: Systems, methods, and apparatus for data communication are provided. An apparatus maybe configured to generate a mask field in a packet to be transmitted through an interface to a slave device, the mask field having a first number of bits, provide a control-bit field in the packet, the control-bit field having a second number of bits, where the second number of bits is less than the first number of bits, and transmit the packet through the interface. The packet may be addressed to a control register of the slave device. The control register may have the first number of bits. Each bit in the control-bit field may correspond to a bit of the control register that is identified by the mask field.

Abstract: Systems and methods described herein facilitate configuration changes to an NIC teaming device while enabling multiple I/O threads continue to run through the NIC teaming device concurrently without interruption. At a given time, multiple configurations of the NIC teaming device, e.g., one for a current configuration of the NIC teaming device and one for a new configuration of the NIC teaming device, can co-exist. For the duration of one iteration, the current configuration of the NIC teaming device used by a specific I/O thread does not change and the new configuration of the NIC teaming device is not adopted by the I/O thread until the start of the next iteration. Once all of the I/O threads finish their current iteration, the configuration of the NIC teaming device is flipped from the current configuration to the new configuration and the current configuration is deleted.

Abstract: A technique is realized that provides a routing operation while using a Point-to-Point communication method as in PCI-Express. A routing address is inserted to a data portion in TLP of PCI-Express. When a routing unit connected to a computer receives TLP from the computer, then a routing switch reads the routing address of a data portion of this TLP to refer to a routing table to determine a slot to which the TLP should be sent. Based on this determination, the routing switch sends the TLP to the predetermined slot. Thus, the routing based on the routing address can be executed.

Abstract: An input/output switching system for a server is disclosed herein. The input/output switching system includes a logic-determination device and at least one connector. The at least one connector electrically connects with at least one electronic card. The at least one connector comprises at least one first standard-bus pin group, at least one second standard-bus pin group, and a first distinguishing-signal pin group. The logic-determination device generates a first determination result which is used for determination of type of the at least one electronic card by receiving a distinguishing signal transmitted from the first distinguishing-signal pin group.

Abstract: A method for determining cable connections identifies a plurality of cables connected to a link included in a first device. The method identifies a first cable connected to the link included in the first device. The method determines that a second cable connected to is connected to a link included in a second device The method further determines that only one of an inbound and an outbound channel of a signaling lane included in the first cable is operable. The method utilizes a second cable to perform one of disabling signal transmission or detecting los of signal on the operable channel. The method enables and disables signal transmission on the operable channel to determine that the first cable is connected to the link included in the remote device.

Abstract: A service redirect operation mode allows a tester device to perform software burn-in, firmware upgrade, and other related device interrogation via a USB Type-C connection. The service redirect operation mode is implemented by modifying a termination state of the configuration channel pins of the USB Type-C receptacle of the device under test. Software and/or hardware executing on the device under test re-configure the resistive arrangement of the configuration channel pins, causing one pin to be connected to a reference voltage via a pull-up resistor and the other pin to be connected to ground via a pull-down resistor. When operating in the service redirect operating mode, two additional signal lines of the USB Type-C receptacles may be used to exchange information between the tester and the device under test using a user-specified interface protocol.

Abstract: Systems for managing shared content in a cloud-based service platform. A method commences upon identifying one or more storage devices that store one or more content objects. The storage devices may be partitioned into geographically distant locations. A first partition in one geography is associated with a first set of content objects and a second partition is associated with a second set of content objects. An inviter-collaborator generates a set of outgoing collaboration attributes pertaining to a shared content object from the first partition. The outgoing collaboration attributes are stored on the inviter's partition. An invitee-collaborator accepts the invitation and generates a set of incoming collaboration attributes that derive from the set of outgoing collaboration attributes. The set of incoming collaboration attributes are stored on the invitee's partition.

Abstract: The present invention discloses a method for integrating a many-core processor system with a network router. The method comprises a subnet division step used for dividing an on-chip network into network requests in multiple subnet balance chips, and a network interface device deployment step used for deploying at least one network interface device in a subnet in a distributed mode in order to guarantee optimization of the connectivity between the deployed network interface device and the processor cores in the subnets and to implement rapid data exchange of the on-chip network or the inter-chip network. The present invention also discloses a many-core processor system integrated with a network router. The system comprises a network router used for network interfacing and data exchange, and comprising multiple network interface devices embedded into the on-chip network in a distributed mode.

Abstract: Technology to suppress the drop in SIMD processor efficiency that occurs when exchanging two-dimensional data in a plurality of rectangular regions, between an external section and a plurality of processor elements in an SIMD processor, so that one rectangular region corresponds to one processor element. In the SIMD processor, an address storage unit in a memory controller is capable of setting N number of addresses Ai (i=1 through N) in an external memory by utilizing a control processor. A parameter storage unit is capable of setting a first parameter OSV, a second parameter W, and a third parameter L by utilizing a control processor. A data transfer unit executes the transfer of data between an external memory, and the buffers in N number of processor elements contained in the applicable SIMD processor, based on the contents of the address storage unit and the parameter storage unit.

Abstract: Embodiments include performing sparse matrix-matrix multiplication. Aspects include receiving a first matrix and a second matrix, providing a pseudo-space for the first and second matrices, and defining pseudo-space segments and assigning the pseudo-space segments to certain processes. Aspects also include assigning matrix elements of the first and second matrix to pseudo-space segments using a midpoint method thereby assigning the matrix elements to processes associated with the pseudo-space segments, assigning a result matrix element of a result matrix to a pseudo-space segment using a midpoint method thereby assigning the result matrix element to a further process associated with the pseudo-space segment and transmitting matrix elements of the first and second matrix required to establish a result matrix element to the further process which processes the result matrix element.

Abstract: According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads t0 to tk-1, wherein a first result of thread t0 is ready one cycle after the first input of thread tk-1 is fed into the pipeline, and outputting a result matrix Y.

Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.

Abstract: Some embodiments of the invention provide a novel method for generating a page that contains summaries of a number of documents. In some embodiments, the page includes several sections (e.g., rows). The method receives a set of documents to summarize. The documents in the received set are sorted in an order (e.g., based on relevance to a viewer of the page). In some embodiments, the method uses a layout generator to identify an arrangement of one or more document summaries for each section on the page.

Abstract: Various technologies described herein pertain to creating transformed third-party content for inclusion in a page of a publisher for display on a client computing device. A request for the page of the publisher generated by the client computing device can be received. In response to receiving the request, a template for the transformed third-party content can be selected based on an identity of the publisher of the page and a type of the page. Further, in response to receiving the request, third-party content from a data repository comprising available third-party content can be selected. The third-party content can be selected based on publisher provided content in the page. The third-party content can be formatted according to the template to compose the transformed third-party content. Moreover, the transformed third-party content can be transmitted to the client computing device for native inclusion in the page amongst the publisher provided content.

Abstract: A method for identifying a font displayed within an electronic document. In one embodiment, the method includes a computer processor identifying a string of two or more characters that correspond to a custom ligature within an electronic document, wherein the custom ligature is associated with at least one character of the electronic document. The method further includes accessing a font library associated with the electronic document. The method further includes identifying a font file within the font library that corresponds to the at least one character of the electronic document that is associated with the custom ligature. The method further includes identifying a glyph within the identified font file that corresponds to the custom ligature. The method further includes substituting the identified glyph into the electronic document to replace at least the custom ligature. The method further includes displaying the substituted glyph within the electronic document.

Abstract: An automotive text display arrangement is described which includes a driver text display positioned directly in front of an automobile driver and displaying a limited amount of text to the driver without impairing forward visual attention of the driver. The arrangement may include a boundary insertion mode wherein when the active text position is an active text boundary, new text is inserted between the text items separated by the active text boundary, and when the active text position is an active text item, new text replaces the active text item. In addition or alternatively, there may be a multifunctional text control knob offering multiple different user movements, each performing an associated text processing function.

Abstract: A method of reproducing a document defined in a page description language (PDL) data structure. The PDL data structure defining content of the document including marked content is received. The PDL data structure comprises an authoring intent data structure defining an output constraint for reproducing the marked content. The authoring intent data structure is interpreted to determine whether reproducing the marked content in accordance with received user input would violate said output constraint. The document including the marked content is reproduced in a form which satisfies the output constraint by processing the marked content in isolation from the other content of the document using the authoring intent data structure if reproducing the marked content violates the output constraint.

Abstract: Methods, devices, and computer-readable storage medium are disclosed for inputting content coded in a sequence of key presses by a user of an application running on an electronic device. In one embodiment, a method includes: obtaining a first sequence of one or more key presses typed by the user of the application in the electronic device as a representation of an intended input content, obtaining a second sequence of one or more key presses as a representation of a context content of the application under the input coding scheme, identifying a subsequence in the second sequence that matches or closely matches the first sequence, and displaying on a display screen of the electronic device at least a portion of the context content corresponding to the identified subsequence in the second sequence as a candidate for the intended input content.

Abstract: A generation apparatus that generates a mapping between individual properties included in an object in a program and individual elements of a structured document. The generation apparatus includes: an object tree generation unit that generates a tree structure representing hierarchical structure of the object by assigning the individual properties included in the object to nodes of the tree structure; and a selection unit that selects a mapping minimizing conversion cost of converting the tree structure of the object to a tree structure that includes the individual elements of the structured document as its nodes. The selection is from mappings that associate the individual properties included in the object with the individual elements of the structured document.